1 // SPDX-License-Identifier: GPL-2.0-only
3 * omap_hwmod_2420_data.c - hardware modules present on the OMAP2420 chips
5 * Copyright (C) 2009-2011 Nokia Corporation
6 * Copyright (C) 2012 Texas Instruments, Inc.
9 * XXX handle crossbar/shared link difference for L3?
10 * XXX these should be marked initdata for multi-OMAP kernels
13 #include <linux/platform_data/i2c-omap.h>
14 #include <linux/omap-dma.h>
16 #include "omap_hwmod.h"
20 #include "omap_hwmod_common_data.h"
22 #include "cm-regbits-24xx.h"
23 #include "prm-regbits-24xx.h"
30 * OMAP2420 hardware module integration data
32 * All of the data in this section should be autogeneratable from the
33 * TI hardware database or other technical documentation. Data that
34 * is driver-specific or driver-kernel integration-specific belongs
43 static struct omap_hwmod_class iva1_hwmod_class = {
47 static struct omap_hwmod_rst_info omap2420_iva_resets[] = {
48 { .name = "iva", .rst_shift = 8 },
51 static struct omap_hwmod omap2420_iva_hwmod = {
53 .class = &iva1_hwmod_class,
54 .clkdm_name = "iva1_clkdm",
55 .rst_lines = omap2420_iva_resets,
56 .rst_lines_cnt = ARRAY_SIZE(omap2420_iva_resets),
57 .main_clk = "iva1_ifck",
61 static struct omap_hwmod_class dsp_hwmod_class = {
65 static struct omap_hwmod_rst_info omap2420_dsp_resets[] = {
66 { .name = "logic", .rst_shift = 0 },
67 { .name = "mmu", .rst_shift = 1 },
70 static struct omap_hwmod omap2420_dsp_hwmod = {
72 .class = &dsp_hwmod_class,
73 .clkdm_name = "dsp_clkdm",
74 .rst_lines = omap2420_dsp_resets,
75 .rst_lines_cnt = ARRAY_SIZE(omap2420_dsp_resets),
76 .main_clk = "dsp_fck",
80 static struct omap_hwmod_class_sysconfig i2c_sysc = {
84 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
85 .sysc_fields = &omap_hwmod_sysc_type1,
88 static struct omap_hwmod_class i2c_class = {
91 .reset = &omap_i2c_reset,
95 static struct omap_hwmod omap2420_i2c1_hwmod = {
97 .main_clk = "i2c1_fck",
100 .module_offs = CORE_MOD,
102 .idlest_idle_bit = OMAP2420_ST_I2C1_SHIFT,
107 * From mach-omap2/pm24xx.c: "Putting MPU into the WFI state
108 * while a transfer is active seems to cause the I2C block to
109 * timeout. Why? Good question."
111 .flags = (HWMOD_16BIT_REG | HWMOD_BLOCK_WFI),
115 static struct omap_hwmod omap2420_i2c2_hwmod = {
117 .main_clk = "i2c2_fck",
120 .module_offs = CORE_MOD,
122 .idlest_idle_bit = OMAP2420_ST_I2C2_SHIFT,
126 .flags = HWMOD_16BIT_REG,
130 static struct omap_dma_dev_attr dma_dev_attr = {
131 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
132 IS_CSSA_32 | IS_CDSA_32,
136 static struct omap_hwmod omap2420_dma_system_hwmod = {
138 .class = &omap2xxx_dma_hwmod_class,
139 .main_clk = "core_l3_ck",
140 .dev_attr = &dma_dev_attr,
141 .flags = HWMOD_NO_IDLEST,
145 static struct omap_hwmod omap2420_mailbox_hwmod = {
147 .class = &omap2xxx_mailbox_hwmod_class,
148 .main_clk = "mailboxes_ick",
151 .module_offs = CORE_MOD,
153 .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
160 * multi channel buffered serial port controller
163 static struct omap_hwmod_class omap2420_mcbsp_hwmod_class = {
167 static struct omap_hwmod_opt_clk mcbsp_opt_clks[] = {
168 { .role = "pad_fck", .clk = "mcbsp_clks" },
169 { .role = "prcm_fck", .clk = "func_96m_ck" },
173 static struct omap_hwmod omap2420_mcbsp1_hwmod = {
175 .class = &omap2420_mcbsp_hwmod_class,
176 .main_clk = "mcbsp1_fck",
179 .module_offs = CORE_MOD,
181 .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT,
184 .opt_clks = mcbsp_opt_clks,
185 .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks),
189 static struct omap_hwmod omap2420_mcbsp2_hwmod = {
191 .class = &omap2420_mcbsp_hwmod_class,
192 .main_clk = "mcbsp2_fck",
195 .module_offs = CORE_MOD,
197 .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT,
200 .opt_clks = mcbsp_opt_clks,
201 .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks),
204 static struct omap_hwmod_class_sysconfig omap2420_msdi_sysc = {
208 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
209 .sysc_fields = &omap_hwmod_sysc_type1,
212 static struct omap_hwmod_class omap2420_msdi_hwmod_class = {
214 .sysc = &omap2420_msdi_sysc,
215 .reset = &omap_msdi_reset,
219 static struct omap_hwmod omap2420_msdi1_hwmod = {
221 .class = &omap2420_msdi_hwmod_class,
222 .main_clk = "mmc_fck",
225 .module_offs = CORE_MOD,
227 .idlest_idle_bit = OMAP2420_ST_MMC_SHIFT,
230 .flags = HWMOD_16BIT_REG,
234 static struct omap_hwmod omap2420_hdq1w_hwmod = {
236 .main_clk = "hdq_fck",
239 .module_offs = CORE_MOD,
241 .idlest_idle_bit = OMAP24XX_ST_HDQ_SHIFT,
244 .class = &omap2_hdq1w_class,
251 /* L4 CORE -> I2C1 interface */
252 static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = {
253 .master = &omap2xxx_l4_core_hwmod,
254 .slave = &omap2420_i2c1_hwmod,
256 .user = OCP_USER_MPU | OCP_USER_SDMA,
259 /* L4 CORE -> I2C2 interface */
260 static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = {
261 .master = &omap2xxx_l4_core_hwmod,
262 .slave = &omap2420_i2c2_hwmod,
264 .user = OCP_USER_MPU | OCP_USER_SDMA,
267 /* IVA <- L3 interface */
268 static struct omap_hwmod_ocp_if omap2420_l3__iva = {
269 .master = &omap2xxx_l3_main_hwmod,
270 .slave = &omap2420_iva_hwmod,
272 .user = OCP_USER_MPU | OCP_USER_SDMA,
275 /* DSP <- L3 interface */
276 static struct omap_hwmod_ocp_if omap2420_l3__dsp = {
277 .master = &omap2xxx_l3_main_hwmod,
278 .slave = &omap2420_dsp_hwmod,
280 .user = OCP_USER_MPU | OCP_USER_SDMA,
283 /* l4_wkup -> timer1 */
284 static struct omap_hwmod_ocp_if omap2420_l4_wkup__timer1 = {
285 .master = &omap2xxx_l4_wkup_hwmod,
286 .slave = &omap2xxx_timer1_hwmod,
288 .user = OCP_USER_MPU | OCP_USER_SDMA,
291 /* l4_wkup -> wd_timer2 */
292 static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = {
293 .master = &omap2xxx_l4_wkup_hwmod,
294 .slave = &omap2xxx_wd_timer2_hwmod,
295 .clk = "mpu_wdt_ick",
296 .user = OCP_USER_MPU | OCP_USER_SDMA,
299 /* l4_wkup -> gpio1 */
300 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio1 = {
301 .master = &omap2xxx_l4_wkup_hwmod,
302 .slave = &omap2xxx_gpio1_hwmod,
304 .user = OCP_USER_MPU | OCP_USER_SDMA,
307 /* l4_wkup -> gpio2 */
308 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio2 = {
309 .master = &omap2xxx_l4_wkup_hwmod,
310 .slave = &omap2xxx_gpio2_hwmod,
312 .user = OCP_USER_MPU | OCP_USER_SDMA,
315 /* l4_wkup -> gpio3 */
316 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio3 = {
317 .master = &omap2xxx_l4_wkup_hwmod,
318 .slave = &omap2xxx_gpio3_hwmod,
320 .user = OCP_USER_MPU | OCP_USER_SDMA,
323 /* l4_wkup -> gpio4 */
324 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio4 = {
325 .master = &omap2xxx_l4_wkup_hwmod,
326 .slave = &omap2xxx_gpio4_hwmod,
328 .user = OCP_USER_MPU | OCP_USER_SDMA,
331 /* dma_system -> L3 */
332 static struct omap_hwmod_ocp_if omap2420_dma_system__l3 = {
333 .master = &omap2420_dma_system_hwmod,
334 .slave = &omap2xxx_l3_main_hwmod,
336 .user = OCP_USER_MPU | OCP_USER_SDMA,
339 /* l4_core -> dma_system */
340 static struct omap_hwmod_ocp_if omap2420_l4_core__dma_system = {
341 .master = &omap2xxx_l4_core_hwmod,
342 .slave = &omap2420_dma_system_hwmod,
344 .user = OCP_USER_MPU | OCP_USER_SDMA,
347 /* l4_core -> mailbox */
348 static struct omap_hwmod_ocp_if omap2420_l4_core__mailbox = {
349 .master = &omap2xxx_l4_core_hwmod,
350 .slave = &omap2420_mailbox_hwmod,
351 .user = OCP_USER_MPU | OCP_USER_SDMA,
354 /* l4_core -> mcbsp1 */
355 static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp1 = {
356 .master = &omap2xxx_l4_core_hwmod,
357 .slave = &omap2420_mcbsp1_hwmod,
359 .user = OCP_USER_MPU | OCP_USER_SDMA,
362 /* l4_core -> mcbsp2 */
363 static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp2 = {
364 .master = &omap2xxx_l4_core_hwmod,
365 .slave = &omap2420_mcbsp2_hwmod,
367 .user = OCP_USER_MPU | OCP_USER_SDMA,
370 /* l4_core -> msdi1 */
371 static struct omap_hwmod_ocp_if omap2420_l4_core__msdi1 = {
372 .master = &omap2xxx_l4_core_hwmod,
373 .slave = &omap2420_msdi1_hwmod,
375 .user = OCP_USER_MPU | OCP_USER_SDMA,
378 /* l4_core -> hdq1w interface */
379 static struct omap_hwmod_ocp_if omap2420_l4_core__hdq1w = {
380 .master = &omap2xxx_l4_core_hwmod,
381 .slave = &omap2420_hdq1w_hwmod,
383 .user = OCP_USER_MPU | OCP_USER_SDMA,
384 .flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
388 /* l4_wkup -> 32ksync_counter */
389 static struct omap_hwmod_ocp_if omap2420_l4_wkup__counter_32k = {
390 .master = &omap2xxx_l4_wkup_hwmod,
391 .slave = &omap2xxx_counter_32k_hwmod,
392 .clk = "sync_32k_ick",
393 .user = OCP_USER_MPU | OCP_USER_SDMA,
396 static struct omap_hwmod_ocp_if omap2420_l3__gpmc = {
397 .master = &omap2xxx_l3_main_hwmod,
398 .slave = &omap2xxx_gpmc_hwmod,
400 .user = OCP_USER_MPU | OCP_USER_SDMA,
403 static struct omap_hwmod_ocp_if *omap2420_hwmod_ocp_ifs[] __initdata = {
404 &omap2xxx_l3_main__l4_core,
405 &omap2xxx_mpu__l3_main,
407 &omap2xxx_l4_core__mcspi1,
408 &omap2xxx_l4_core__mcspi2,
409 &omap2xxx_l4_core__l4_wkup,
410 &omap2_l4_core__uart1,
411 &omap2_l4_core__uart2,
412 &omap2_l4_core__uart3,
413 &omap2420_l4_core__i2c1,
414 &omap2420_l4_core__i2c2,
417 &omap2420_l4_wkup__timer1,
418 &omap2xxx_l4_core__timer2,
419 &omap2xxx_l4_core__timer3,
420 &omap2xxx_l4_core__timer4,
421 &omap2xxx_l4_core__timer5,
422 &omap2xxx_l4_core__timer6,
423 &omap2xxx_l4_core__timer7,
424 &omap2xxx_l4_core__timer8,
425 &omap2xxx_l4_core__timer9,
426 &omap2xxx_l4_core__timer10,
427 &omap2xxx_l4_core__timer11,
428 &omap2xxx_l4_core__timer12,
429 &omap2420_l4_wkup__wd_timer2,
430 &omap2xxx_l4_core__dss,
431 &omap2xxx_l4_core__dss_dispc,
432 &omap2xxx_l4_core__dss_rfbi,
433 &omap2xxx_l4_core__dss_venc,
434 &omap2420_l4_wkup__gpio1,
435 &omap2420_l4_wkup__gpio2,
436 &omap2420_l4_wkup__gpio3,
437 &omap2420_l4_wkup__gpio4,
438 &omap2420_dma_system__l3,
439 &omap2420_l4_core__dma_system,
440 &omap2420_l4_core__mailbox,
441 &omap2420_l4_core__mcbsp1,
442 &omap2420_l4_core__mcbsp2,
443 &omap2420_l4_core__msdi1,
444 &omap2xxx_l4_core__rng,
445 &omap2xxx_l4_core__sham,
446 &omap2xxx_l4_core__aes,
447 &omap2420_l4_core__hdq1w,
448 &omap2420_l4_wkup__counter_32k,
453 int __init omap2420_hwmod_init(void)
456 return omap_hwmod_register_links(omap2420_hwmod_ocp_ifs);