arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c

   1 /*
   2  *
   3  * Copyright (C) 2013 Texas Instruments Incorporated
   4  *
   5  * Hwmod common for AM335x and AM43x
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation version 2.
  10  *
  11  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  12  * kind, whether express or implied; without even the implied warranty
  13  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <linux/types.h>
  18
  19 #include "omap_hwmod.h"
  20 #include "cm33xx.h"
  21 #include "prm33xx.h"
  22 #include "omap_hwmod_33xx_43xx_common_data.h"
  23 #include "prcm43xx.h"
  24 #include "common.h"
  25
  26 #define CLKCTRL(oh, clkctrl) ((oh).prcm.omap4.clkctrl_offs = (clkctrl))
  27 #define RSTCTRL(oh, rstctrl) ((oh).prcm.omap4.rstctrl_offs = (rstctrl))
  28 #define RSTST(oh, rstst) ((oh).prcm.omap4.rstst_offs = (rstst))
  29 #define PRCM_FLAGS(oh, flag) ((oh).prcm.omap4.flags = (flag))
  30
  31 /*
  32  * 'l3' class
  33  * instance(s): l3_main, l3_s, l3_instr
  34  */
  35 static struct omap_hwmod_class am33xx_l3_hwmod_class = {
  36         .name           = "l3",
  37 };
  38
  39 struct omap_hwmod am33xx_l3_main_hwmod = {
  40         .name           = "l3_main",
  41         .class          = &am33xx_l3_hwmod_class,
  42         .clkdm_name     = "l3_clkdm",
  43         .flags          = HWMOD_INIT_NO_IDLE,
  44         .main_clk       = "l3_gclk",
  45         .prcm           = {
  46                 .omap4  = {
  47                         .modulemode     = MODULEMODE_SWCTRL,
  48                 },
  49         },
  50 };
  51
  52 /* l3_s */
  53 struct omap_hwmod am33xx_l3_s_hwmod = {
  54         .name           = "l3_s",
  55         .class          = &am33xx_l3_hwmod_class,
  56         .clkdm_name     = "l3s_clkdm",
  57 };
  58
  59 /* l3_instr */
  60 struct omap_hwmod am33xx_l3_instr_hwmod = {
  61         .name           = "l3_instr",
  62         .class          = &am33xx_l3_hwmod_class,
  63         .clkdm_name     = "l3_clkdm",
  64         .flags          = HWMOD_INIT_NO_IDLE,
  65         .main_clk       = "l3_gclk",
  66         .prcm           = {
  67                 .omap4  = {
  68                         .modulemode     = MODULEMODE_SWCTRL,
  69                 },
  70         },
  71 };
  72
  73 /*
  74  * 'l4' class
  75  * instance(s): l4_ls, l4_hs, l4_wkup, l4_fw
  76  */
  77 struct omap_hwmod_class am33xx_l4_hwmod_class = {
  78         .name           = "l4",
  79 };
  80
  81 /* l4_ls */
  82 struct omap_hwmod am33xx_l4_ls_hwmod = {
  83         .name           = "l4_ls",
  84         .class          = &am33xx_l4_hwmod_class,
  85         .clkdm_name     = "l4ls_clkdm",
  86         .flags          = HWMOD_INIT_NO_IDLE,
  87         .main_clk       = "l4ls_gclk",
  88         .prcm           = {
  89                 .omap4  = {
  90                         .modulemode     = MODULEMODE_SWCTRL,
  91                 },
  92         },
  93 };
  94
  95 /* l4_wkup */
  96 struct omap_hwmod am33xx_l4_wkup_hwmod = {
  97         .name           = "l4_wkup",
  98         .class          = &am33xx_l4_hwmod_class,
  99         .clkdm_name     = "l4_wkup_clkdm",
 100         .flags          = HWMOD_INIT_NO_IDLE,
 101         .prcm           = {
 102                 .omap4  = {
 103                         .modulemode     = MODULEMODE_SWCTRL,
 104                 },
 105         },
 106 };
 107
 108 /*
 109  * 'mpu' class
 110  */
 111 static struct omap_hwmod_class am33xx_mpu_hwmod_class = {
 112         .name   = "mpu",
 113 };
 114
 115 struct omap_hwmod am33xx_mpu_hwmod = {
 116         .name           = "mpu",
 117         .class          = &am33xx_mpu_hwmod_class,
 118         .clkdm_name     = "mpu_clkdm",
 119         .flags          = HWMOD_INIT_NO_IDLE,
 120         .main_clk       = "dpll_mpu_m2_ck",
 121         .prcm           = {
 122                 .omap4  = {
 123                         .modulemode     = MODULEMODE_SWCTRL,
 124                 },
 125         },
 126 };
 127
 128 /*
 129  * 'wakeup m3' class
 130  * Wakeup controller sub-system under wakeup domain
 131  */
 132 struct omap_hwmod_class am33xx_wkup_m3_hwmod_class = {
 133         .name           = "wkup_m3",
 134 };
 135
 136 /*
 137  * 'pru-icss' class
 138  * Programmable Real-Time Unit and Industrial Communication Subsystem
 139  */
 140 static struct omap_hwmod_class am33xx_pruss_hwmod_class = {
 141         .name   = "pruss",
 142 };
 143
 144 static struct omap_hwmod_rst_info am33xx_pruss_resets[] = {
 145         { .name = "pruss", .rst_shift = 1 },
 146 };
 147
 148 /* pru-icss */
 149 /* Pseudo hwmod for reset control purpose only */
 150 struct omap_hwmod am33xx_pruss_hwmod = {
 151         .name           = "pruss",
 152         .class          = &am33xx_pruss_hwmod_class,
 153         .clkdm_name     = "pruss_ocp_clkdm",
 154         .main_clk       = "pruss_ocp_gclk",
 155         .prcm           = {
 156                 .omap4  = {
 157                         .modulemode     = MODULEMODE_SWCTRL,
 158                 },
 159         },
 160         .rst_lines      = am33xx_pruss_resets,
 161         .rst_lines_cnt  = ARRAY_SIZE(am33xx_pruss_resets),
 162 };
 163
 164 /* gfx */
 165 /* Pseudo hwmod for reset control purpose only */
 166 static struct omap_hwmod_class am33xx_gfx_hwmod_class = {
 167         .name   = "gfx",
 168 };
 169
 170 static struct omap_hwmod_rst_info am33xx_gfx_resets[] = {
 171         { .name = "gfx", .rst_shift = 0, .st_shift = 0},
 172 };
 173
 174 struct omap_hwmod am33xx_gfx_hwmod = {
 175         .name           = "gfx",
 176         .class          = &am33xx_gfx_hwmod_class,
 177         .clkdm_name     = "gfx_l3_clkdm",
 178         .main_clk       = "gfx_fck_div_ck",
 179         .prcm           = {
 180                 .omap4  = {
 181                         .modulemode     = MODULEMODE_SWCTRL,
 182                 },
 183         },
 184         .rst_lines      = am33xx_gfx_resets,
 185         .rst_lines_cnt  = ARRAY_SIZE(am33xx_gfx_resets),
 186 };
 187
 188 /*
 189  * 'prcm' class
 190  * power and reset manager (whole prcm infrastructure)
 191  */
 192 static struct omap_hwmod_class am33xx_prcm_hwmod_class = {
 193         .name   = "prcm",
 194 };
 195
 196 /* prcm */
 197 struct omap_hwmod am33xx_prcm_hwmod = {
 198         .name           = "prcm",
 199         .class          = &am33xx_prcm_hwmod_class,
 200         .clkdm_name     = "l4_wkup_clkdm",
 201 };
 202
 203 /*
 204  * 'emif' class
 205  * instance(s): emif
 206  */
 207 static struct omap_hwmod_class_sysconfig am33xx_emif_sysc = {
 208         .rev_offs       = 0x0000,
 209 };
 210
 211 struct omap_hwmod_class am33xx_emif_hwmod_class = {
 212         .name           = "emif",
 213         .sysc           = &am33xx_emif_sysc,
 214 };
 215
 216
 217
 218 /* ocmcram */
 219 static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = {
 220         .name = "ocmcram",
 221 };
 222
 223 struct omap_hwmod am33xx_ocmcram_hwmod = {
 224         .name           = "ocmcram",
 225         .class          = &am33xx_ocmcram_hwmod_class,
 226         .clkdm_name     = "l3_clkdm",
 227         .flags          = HWMOD_INIT_NO_IDLE,
 228         .main_clk       = "l3_gclk",
 229         .prcm           = {
 230                 .omap4  = {
 231                         .modulemode     = MODULEMODE_SWCTRL,
 232                 },
 233         },
 234 };
 235
 236 /* 'smartreflex' class */
 237 static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = {
 238         .name           = "smartreflex",
 239 };
 240
 241 /* smartreflex0 */
 242 struct omap_hwmod am33xx_smartreflex0_hwmod = {
 243         .name           = "smartreflex0",
 244         .class          = &am33xx_smartreflex_hwmod_class,
 245         .clkdm_name     = "l4_wkup_clkdm",
 246         .main_clk       = "smartreflex0_fck",
 247         .prcm           = {
 248                 .omap4  = {
 249                         .modulemode     = MODULEMODE_SWCTRL,
 250                 },
 251         },
 252 };
 253
 254 /* smartreflex1 */
 255 struct omap_hwmod am33xx_smartreflex1_hwmod = {
 256         .name           = "smartreflex1",
 257         .class          = &am33xx_smartreflex_hwmod_class,
 258         .clkdm_name     = "l4_wkup_clkdm",
 259         .main_clk       = "smartreflex1_fck",
 260         .prcm           = {
 261                 .omap4  = {
 262                         .modulemode     = MODULEMODE_SWCTRL,
 263                 },
 264         },
 265 };
 266
 267 /*
 268  * 'control' module class
 269  */
 270 struct omap_hwmod_class am33xx_control_hwmod_class = {
 271         .name           = "control",
 272 };
 273
 274
 275 /* gpmc */
 276 static struct omap_hwmod_class_sysconfig gpmc_sysc = {
 277         .rev_offs       = 0x0,
 278         .sysc_offs      = 0x10,
 279         .syss_offs      = 0x14,
 280         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
 281                         SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 282         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 283         .sysc_fields    = &omap_hwmod_sysc_type1,
 284 };
 285
 286 static struct omap_hwmod_class am33xx_gpmc_hwmod_class = {
 287         .name           = "gpmc",
 288         .sysc           = &gpmc_sysc,
 289 };
 290
 291 struct omap_hwmod am33xx_gpmc_hwmod = {
 292         .name           = "gpmc",
 293         .class          = &am33xx_gpmc_hwmod_class,
 294         .clkdm_name     = "l3s_clkdm",
 295         /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
 296         .flags          = DEBUG_OMAP_GPMC_HWMOD_FLAGS,
 297         .main_clk       = "l3s_gclk",
 298         .prcm           = {
 299                 .omap4  = {
 300                         .modulemode     = MODULEMODE_SWCTRL,
 301                 },
 302         },
 303 };
 304
 305
 306 /*
 307  * 'rtc' class
 308  * rtc subsystem
 309  */
 310 static struct omap_hwmod_class_sysconfig am33xx_rtc_sysc = {
 311         .rev_offs       = 0x0074,
 312         .sysc_offs      = 0x0078,
 313         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 314         .idlemodes      = (SIDLE_FORCE | SIDLE_NO |
 315                           SIDLE_SMART | SIDLE_SMART_WKUP),
 316         .sysc_fields    = &omap_hwmod_sysc_type3,
 317 };
 318
 319 static struct omap_hwmod_class am33xx_rtc_hwmod_class = {
 320         .name           = "rtc",
 321         .sysc           = &am33xx_rtc_sysc,
 322         .unlock         = &omap_hwmod_rtc_unlock,
 323         .lock           = &omap_hwmod_rtc_lock,
 324 };
 325
 326 struct omap_hwmod am33xx_rtc_hwmod = {
 327         .name           = "rtc",
 328         .class          = &am33xx_rtc_hwmod_class,
 329         .clkdm_name     = "l4_rtc_clkdm",
 330         .main_clk       = "clk_32768_ck",
 331         .prcm           = {
 332                 .omap4  = {
 333                         .modulemode     = MODULEMODE_SWCTRL,
 334                 },
 335         },
 336 };
 337
 338 /* 'timer 2-7' class */
 339 static struct omap_hwmod_class_sysconfig am33xx_timer_sysc = {
 340         .rev_offs       = 0x0000,
 341         .sysc_offs      = 0x0010,
 342         .syss_offs      = 0x0014,
 343         .sysc_flags     = SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 344                           SYSC_HAS_RESET_STATUS,
 345         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 346                           SIDLE_SMART_WKUP),
 347         .sysc_fields    = &omap_hwmod_sysc_type2,
 348 };
 349
 350 struct omap_hwmod_class am33xx_timer_hwmod_class = {
 351         .name           = "timer",
 352         .sysc           = &am33xx_timer_sysc,
 353 };
 354
 355 /* timer1 1ms */
 356 static struct omap_hwmod_class_sysconfig am33xx_timer1ms_sysc = {
 357         .rev_offs       = 0x0000,
 358         .sysc_offs      = 0x0010,
 359         .syss_offs      = 0x0014,
 360         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
 361                         SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
 362                         SYSS_HAS_RESET_STATUS),
 363         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 364         .sysc_fields    = &omap_hwmod_sysc_type1,
 365 };
 366
 367 static struct omap_hwmod_class am33xx_timer1ms_hwmod_class = {
 368         .name           = "timer",
 369         .sysc           = &am33xx_timer1ms_sysc,
 370 };
 371
 372 struct omap_hwmod am33xx_timer1_hwmod = {
 373         .name           = "timer1",
 374         .class          = &am33xx_timer1ms_hwmod_class,
 375         .clkdm_name     = "l4_wkup_clkdm",
 376         .main_clk       = "timer1_fck",
 377         .prcm           = {
 378                 .omap4  = {
 379                         .modulemode     = MODULEMODE_SWCTRL,
 380                 },
 381         },
 382 };
 383
 384 struct omap_hwmod am33xx_timer2_hwmod = {
 385         .name           = "timer2",
 386         .class          = &am33xx_timer_hwmod_class,
 387         .clkdm_name     = "l4ls_clkdm",
 388         .main_clk       = "timer2_fck",
 389         .prcm           = {
 390                 .omap4  = {
 391                         .modulemode     = MODULEMODE_SWCTRL,
 392                 },
 393         },
 394 };
 395
 396 /* tpcc */
 397 static struct omap_hwmod_class am33xx_tpcc_hwmod_class = {
 398         .name           = "tpcc",
 399 };
 400
 401 struct omap_hwmod am33xx_tpcc_hwmod = {
 402         .name           = "tpcc",
 403         .class          = &am33xx_tpcc_hwmod_class,
 404         .clkdm_name     = "l3_clkdm",
 405         .main_clk       = "l3_gclk",
 406         .prcm           = {
 407                 .omap4  = {
 408                         .modulemode     = MODULEMODE_SWCTRL,
 409                 },
 410         },
 411 };
 412
 413 static struct omap_hwmod_class_sysconfig am33xx_tptc_sysc = {
 414         .rev_offs       = 0x0,
 415         .sysc_offs      = 0x10,
 416         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 417                           SYSC_HAS_MIDLEMODE),
 418         .idlemodes      = (SIDLE_FORCE | SIDLE_SMART | MSTANDBY_FORCE),
 419         .sysc_fields    = &omap_hwmod_sysc_type2,
 420 };
 421
 422 /* 'tptc' class */
 423 static struct omap_hwmod_class am33xx_tptc_hwmod_class = {
 424         .name           = "tptc",
 425         .sysc           = &am33xx_tptc_sysc,
 426 };
 427
 428 /* tptc0 */
 429 struct omap_hwmod am33xx_tptc0_hwmod = {
 430         .name           = "tptc0",
 431         .class          = &am33xx_tptc_hwmod_class,
 432         .clkdm_name     = "l3_clkdm",
 433         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
 434         .main_clk       = "l3_gclk",
 435         .prcm           = {
 436                 .omap4  = {
 437                         .modulemode     = MODULEMODE_SWCTRL,
 438                 },
 439         },
 440 };
 441
 442 /* tptc1 */
 443 struct omap_hwmod am33xx_tptc1_hwmod = {
 444         .name           = "tptc1",
 445         .class          = &am33xx_tptc_hwmod_class,
 446         .clkdm_name     = "l3_clkdm",
 447         .flags          = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
 448         .main_clk       = "l3_gclk",
 449         .prcm           = {
 450                 .omap4  = {
 451                         .modulemode     = MODULEMODE_SWCTRL,
 452                 },
 453         },
 454 };
 455
 456 /* tptc2 */
 457 struct omap_hwmod am33xx_tptc2_hwmod = {
 458         .name           = "tptc2",
 459         .class          = &am33xx_tptc_hwmod_class,
 460         .clkdm_name     = "l3_clkdm",
 461         .flags          = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
 462         .main_clk       = "l3_gclk",
 463         .prcm           = {
 464                 .omap4  = {
 465                         .modulemode     = MODULEMODE_SWCTRL,
 466                 },
 467         },
 468 };
 469
 470 static void omap_hwmod_am33xx_clkctrl(void)
 471 {
 472         CLKCTRL(am33xx_timer2_hwmod, AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET);
 473         CLKCTRL(am33xx_smartreflex0_hwmod,
 474                 AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET);
 475         CLKCTRL(am33xx_smartreflex1_hwmod,
 476                 AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET);
 477         CLKCTRL(am33xx_timer1_hwmod, AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET);
 478         CLKCTRL(am33xx_rtc_hwmod, AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET);
 479         PRCM_FLAGS(am33xx_rtc_hwmod, HWMOD_OMAP4_ZERO_CLKCTRL_OFFSET);
 480         CLKCTRL(am33xx_gpmc_hwmod, AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET);
 481         CLKCTRL(am33xx_l4_ls_hwmod, AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET);
 482         CLKCTRL(am33xx_l4_wkup_hwmod, AM33XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET);
 483         CLKCTRL(am33xx_l3_main_hwmod, AM33XX_CM_PER_L3_CLKCTRL_OFFSET);
 484         CLKCTRL(am33xx_tpcc_hwmod, AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET);
 485         CLKCTRL(am33xx_tptc0_hwmod, AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET);
 486         CLKCTRL(am33xx_tptc1_hwmod, AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET);
 487         CLKCTRL(am33xx_tptc2_hwmod, AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET);
 488         CLKCTRL(am33xx_gfx_hwmod, AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET);
 489         CLKCTRL(am33xx_pruss_hwmod, AM33XX_CM_PER_PRUSS_CLKCTRL_OFFSET);
 490         CLKCTRL(am33xx_mpu_hwmod , AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET);
 491         CLKCTRL(am33xx_l3_instr_hwmod , AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET);
 492         CLKCTRL(am33xx_ocmcram_hwmod , AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET);
 493 }
 494
 495 static void omap_hwmod_am33xx_rst(void)
 496 {
 497         RSTCTRL(am33xx_pruss_hwmod, AM33XX_RM_PER_RSTCTRL_OFFSET);
 498         RSTCTRL(am33xx_gfx_hwmod, AM33XX_RM_GFX_RSTCTRL_OFFSET);
 499         RSTST(am33xx_gfx_hwmod, AM33XX_RM_GFX_RSTST_OFFSET);
 500 }
 501
 502 void omap_hwmod_am33xx_reg(void)
 503 {
 504         omap_hwmod_am33xx_clkctrl();
 505         omap_hwmod_am33xx_rst();
 506 }
 507
 508 static void omap_hwmod_am43xx_clkctrl(void)
 509 {
 510         CLKCTRL(am33xx_timer2_hwmod, AM43XX_CM_PER_TIMER2_CLKCTRL_OFFSET);
 511         CLKCTRL(am33xx_smartreflex0_hwmod,
 512                 AM43XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET);
 513         CLKCTRL(am33xx_smartreflex1_hwmod,
 514                 AM43XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET);
 515         CLKCTRL(am33xx_timer1_hwmod, AM43XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET);
 516         CLKCTRL(am33xx_rtc_hwmod, AM43XX_CM_RTC_RTC_CLKCTRL_OFFSET);
 517         CLKCTRL(am33xx_gpmc_hwmod, AM43XX_CM_PER_GPMC_CLKCTRL_OFFSET);
 518         CLKCTRL(am33xx_l4_ls_hwmod, AM43XX_CM_PER_L4LS_CLKCTRL_OFFSET);
 519         CLKCTRL(am33xx_l4_wkup_hwmod, AM43XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET);
 520         CLKCTRL(am33xx_l3_main_hwmod, AM43XX_CM_PER_L3_CLKCTRL_OFFSET);
 521         CLKCTRL(am33xx_tpcc_hwmod, AM43XX_CM_PER_TPCC_CLKCTRL_OFFSET);
 522         CLKCTRL(am33xx_tptc0_hwmod, AM43XX_CM_PER_TPTC0_CLKCTRL_OFFSET);
 523         CLKCTRL(am33xx_tptc1_hwmod, AM43XX_CM_PER_TPTC1_CLKCTRL_OFFSET);
 524         CLKCTRL(am33xx_tptc2_hwmod, AM43XX_CM_PER_TPTC2_CLKCTRL_OFFSET);
 525         CLKCTRL(am33xx_gfx_hwmod, AM43XX_CM_GFX_GFX_CLKCTRL_OFFSET);
 526         CLKCTRL(am33xx_pruss_hwmod, AM43XX_CM_PER_PRUSS_CLKCTRL_OFFSET);
 527         CLKCTRL(am33xx_mpu_hwmod , AM43XX_CM_MPU_MPU_CLKCTRL_OFFSET);
 528         CLKCTRL(am33xx_l3_instr_hwmod , AM43XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET);
 529         CLKCTRL(am33xx_ocmcram_hwmod , AM43XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET);
 530 }
 531
 532 static void omap_hwmod_am43xx_rst(void)
 533 {
 534         RSTCTRL(am33xx_pruss_hwmod, AM43XX_RM_PER_RSTCTRL_OFFSET);
 535         RSTCTRL(am33xx_gfx_hwmod, AM43XX_RM_GFX_RSTCTRL_OFFSET);
 536         RSTST(am33xx_pruss_hwmod, AM43XX_RM_PER_RSTST_OFFSET);
 537         RSTST(am33xx_gfx_hwmod, AM43XX_RM_GFX_RSTST_OFFSET);
 538 }
 539
 540 void omap_hwmod_am43xx_reg(void)
 541 {
 542         omap_hwmod_am43xx_clkctrl();
 543         omap_hwmod_am43xx_rst();
 544 }