arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c

   1 /*
   2  *
   3  * Copyright (C) 2013 Texas Instruments Incorporated
   4  *
   5  * Hwmod common for AM335x and AM43x
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation version 2.
  10  *
  11  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  12  * kind, whether express or implied; without even the implied warranty
  13  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <linux/types.h>
  18
  19 #include "omap_hwmod.h"
  20 #include "wd_timer.h"
  21 #include "cm33xx.h"
  22 #include "prm33xx.h"
  23 #include "omap_hwmod_33xx_43xx_common_data.h"
  24 #include "prcm43xx.h"
  25 #include "common.h"
  26
  27 #define CLKCTRL(oh, clkctrl) ((oh).prcm.omap4.clkctrl_offs = (clkctrl))
  28 #define RSTCTRL(oh, rstctrl) ((oh).prcm.omap4.rstctrl_offs = (rstctrl))
  29 #define RSTST(oh, rstst) ((oh).prcm.omap4.rstst_offs = (rstst))
  30 #define PRCM_FLAGS(oh, flag) ((oh).prcm.omap4.flags = (flag))
  31
  32 /*
  33  * 'l3' class
  34  * instance(s): l3_main, l3_s, l3_instr
  35  */
  36 static struct omap_hwmod_class am33xx_l3_hwmod_class = {
  37         .name           = "l3",
  38 };
  39
  40 struct omap_hwmod am33xx_l3_main_hwmod = {
  41         .name           = "l3_main",
  42         .class          = &am33xx_l3_hwmod_class,
  43         .clkdm_name     = "l3_clkdm",
  44         .flags          = HWMOD_INIT_NO_IDLE,
  45         .main_clk       = "l3_gclk",
  46         .prcm           = {
  47                 .omap4  = {
  48                         .modulemode     = MODULEMODE_SWCTRL,
  49                 },
  50         },
  51 };
  52
  53 /* l3_s */
  54 struct omap_hwmod am33xx_l3_s_hwmod = {
  55         .name           = "l3_s",
  56         .class          = &am33xx_l3_hwmod_class,
  57         .clkdm_name     = "l3s_clkdm",
  58 };
  59
  60 /* l3_instr */
  61 struct omap_hwmod am33xx_l3_instr_hwmod = {
  62         .name           = "l3_instr",
  63         .class          = &am33xx_l3_hwmod_class,
  64         .clkdm_name     = "l3_clkdm",
  65         .flags          = HWMOD_INIT_NO_IDLE,
  66         .main_clk       = "l3_gclk",
  67         .prcm           = {
  68                 .omap4  = {
  69                         .modulemode     = MODULEMODE_SWCTRL,
  70                 },
  71         },
  72 };
  73
  74 /*
  75  * 'l4' class
  76  * instance(s): l4_ls, l4_hs, l4_wkup, l4_fw
  77  */
  78 struct omap_hwmod_class am33xx_l4_hwmod_class = {
  79         .name           = "l4",
  80 };
  81
  82 /* l4_ls */
  83 struct omap_hwmod am33xx_l4_ls_hwmod = {
  84         .name           = "l4_ls",
  85         .class          = &am33xx_l4_hwmod_class,
  86         .clkdm_name     = "l4ls_clkdm",
  87         .flags          = HWMOD_INIT_NO_IDLE,
  88         .main_clk       = "l4ls_gclk",
  89         .prcm           = {
  90                 .omap4  = {
  91                         .modulemode     = MODULEMODE_SWCTRL,
  92                 },
  93         },
  94 };
  95
  96 /* l4_wkup */
  97 struct omap_hwmod am33xx_l4_wkup_hwmod = {
  98         .name           = "l4_wkup",
  99         .class          = &am33xx_l4_hwmod_class,
 100         .clkdm_name     = "l4_wkup_clkdm",
 101         .flags          = HWMOD_INIT_NO_IDLE,
 102         .prcm           = {
 103                 .omap4  = {
 104                         .modulemode     = MODULEMODE_SWCTRL,
 105                 },
 106         },
 107 };
 108
 109 /*
 110  * 'mpu' class
 111  */
 112 static struct omap_hwmod_class am33xx_mpu_hwmod_class = {
 113         .name   = "mpu",
 114 };
 115
 116 struct omap_hwmod am33xx_mpu_hwmod = {
 117         .name           = "mpu",
 118         .class          = &am33xx_mpu_hwmod_class,
 119         .clkdm_name     = "mpu_clkdm",
 120         .flags          = HWMOD_INIT_NO_IDLE,
 121         .main_clk       = "dpll_mpu_m2_ck",
 122         .prcm           = {
 123                 .omap4  = {
 124                         .modulemode     = MODULEMODE_SWCTRL,
 125                 },
 126         },
 127 };
 128
 129 /*
 130  * 'wakeup m3' class
 131  * Wakeup controller sub-system under wakeup domain
 132  */
 133 struct omap_hwmod_class am33xx_wkup_m3_hwmod_class = {
 134         .name           = "wkup_m3",
 135 };
 136
 137 /*
 138  * 'pru-icss' class
 139  * Programmable Real-Time Unit and Industrial Communication Subsystem
 140  */
 141 static struct omap_hwmod_class am33xx_pruss_hwmod_class = {
 142         .name   = "pruss",
 143 };
 144
 145 static struct omap_hwmod_rst_info am33xx_pruss_resets[] = {
 146         { .name = "pruss", .rst_shift = 1 },
 147 };
 148
 149 /* pru-icss */
 150 /* Pseudo hwmod for reset control purpose only */
 151 struct omap_hwmod am33xx_pruss_hwmod = {
 152         .name           = "pruss",
 153         .class          = &am33xx_pruss_hwmod_class,
 154         .clkdm_name     = "pruss_ocp_clkdm",
 155         .main_clk       = "pruss_ocp_gclk",
 156         .prcm           = {
 157                 .omap4  = {
 158                         .modulemode     = MODULEMODE_SWCTRL,
 159                 },
 160         },
 161         .rst_lines      = am33xx_pruss_resets,
 162         .rst_lines_cnt  = ARRAY_SIZE(am33xx_pruss_resets),
 163 };
 164
 165 /* gfx */
 166 /* Pseudo hwmod for reset control purpose only */
 167 static struct omap_hwmod_class am33xx_gfx_hwmod_class = {
 168         .name   = "gfx",
 169 };
 170
 171 static struct omap_hwmod_rst_info am33xx_gfx_resets[] = {
 172         { .name = "gfx", .rst_shift = 0, .st_shift = 0},
 173 };
 174
 175 struct omap_hwmod am33xx_gfx_hwmod = {
 176         .name           = "gfx",
 177         .class          = &am33xx_gfx_hwmod_class,
 178         .clkdm_name     = "gfx_l3_clkdm",
 179         .main_clk       = "gfx_fck_div_ck",
 180         .prcm           = {
 181                 .omap4  = {
 182                         .modulemode     = MODULEMODE_SWCTRL,
 183                 },
 184         },
 185         .rst_lines      = am33xx_gfx_resets,
 186         .rst_lines_cnt  = ARRAY_SIZE(am33xx_gfx_resets),
 187 };
 188
 189 /*
 190  * 'prcm' class
 191  * power and reset manager (whole prcm infrastructure)
 192  */
 193 static struct omap_hwmod_class am33xx_prcm_hwmod_class = {
 194         .name   = "prcm",
 195 };
 196
 197 /* prcm */
 198 struct omap_hwmod am33xx_prcm_hwmod = {
 199         .name           = "prcm",
 200         .class          = &am33xx_prcm_hwmod_class,
 201         .clkdm_name     = "l4_wkup_clkdm",
 202 };
 203
 204 /*
 205  * 'emif' class
 206  * instance(s): emif
 207  */
 208 static struct omap_hwmod_class_sysconfig am33xx_emif_sysc = {
 209         .rev_offs       = 0x0000,
 210 };
 211
 212 struct omap_hwmod_class am33xx_emif_hwmod_class = {
 213         .name           = "emif",
 214         .sysc           = &am33xx_emif_sysc,
 215 };
 216
 217 /*
 218  * 'aes0' class
 219  */
 220 static struct omap_hwmod_class_sysconfig am33xx_aes0_sysc = {
 221         .rev_offs       = 0x80,
 222         .sysc_offs      = 0x84,
 223         .syss_offs      = 0x88,
 224         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 225 };
 226
 227 static struct omap_hwmod_class am33xx_aes0_hwmod_class = {
 228         .name           = "aes0",
 229         .sysc           = &am33xx_aes0_sysc,
 230 };
 231
 232 struct omap_hwmod am33xx_aes0_hwmod = {
 233         .name           = "aes",
 234         .class          = &am33xx_aes0_hwmod_class,
 235         .clkdm_name     = "l3_clkdm",
 236         .main_clk       = "aes0_fck",
 237         .prcm           = {
 238                 .omap4  = {
 239                         .modulemode     = MODULEMODE_SWCTRL,
 240                 },
 241         },
 242 };
 243
 244 /* sha0 HIB2 (the 'P' (public) device) */
 245 static struct omap_hwmod_class_sysconfig am33xx_sha0_sysc = {
 246         .rev_offs       = 0x100,
 247         .sysc_offs      = 0x110,
 248         .syss_offs      = 0x114,
 249         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 250 };
 251
 252 static struct omap_hwmod_class am33xx_sha0_hwmod_class = {
 253         .name           = "sha0",
 254         .sysc           = &am33xx_sha0_sysc,
 255 };
 256
 257 struct omap_hwmod am33xx_sha0_hwmod = {
 258         .name           = "sham",
 259         .class          = &am33xx_sha0_hwmod_class,
 260         .clkdm_name     = "l3_clkdm",
 261         .main_clk       = "l3_gclk",
 262         .prcm           = {
 263                 .omap4  = {
 264                         .modulemode     = MODULEMODE_SWCTRL,
 265                 },
 266         },
 267 };
 268
 269 /* rng */
 270 static struct omap_hwmod_class_sysconfig am33xx_rng_sysc = {
 271         .rev_offs       = 0x1fe0,
 272         .sysc_offs      = 0x1fe4,
 273         .sysc_flags     = SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE,
 274         .idlemodes      = SIDLE_FORCE | SIDLE_NO,
 275         .sysc_fields    = &omap_hwmod_sysc_type1,
 276 };
 277
 278 static struct omap_hwmod_class am33xx_rng_hwmod_class = {
 279         .name           = "rng",
 280         .sysc           = &am33xx_rng_sysc,
 281 };
 282
 283 struct omap_hwmod am33xx_rng_hwmod = {
 284         .name           = "rng",
 285         .class          = &am33xx_rng_hwmod_class,
 286         .clkdm_name     = "l4ls_clkdm",
 287         .flags          = HWMOD_SWSUP_SIDLE,
 288         .main_clk       = "rng_fck",
 289         .prcm           = {
 290                 .omap4  = {
 291                         .modulemode     = MODULEMODE_SWCTRL,
 292                 },
 293         },
 294 };
 295
 296 /* ocmcram */
 297 static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = {
 298         .name = "ocmcram",
 299 };
 300
 301 struct omap_hwmod am33xx_ocmcram_hwmod = {
 302         .name           = "ocmcram",
 303         .class          = &am33xx_ocmcram_hwmod_class,
 304         .clkdm_name     = "l3_clkdm",
 305         .flags          = HWMOD_INIT_NO_IDLE,
 306         .main_clk       = "l3_gclk",
 307         .prcm           = {
 308                 .omap4  = {
 309                         .modulemode     = MODULEMODE_SWCTRL,
 310                 },
 311         },
 312 };
 313
 314 /* 'smartreflex' class */
 315 static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = {
 316         .name           = "smartreflex",
 317 };
 318
 319 /* smartreflex0 */
 320 struct omap_hwmod am33xx_smartreflex0_hwmod = {
 321         .name           = "smartreflex0",
 322         .class          = &am33xx_smartreflex_hwmod_class,
 323         .clkdm_name     = "l4_wkup_clkdm",
 324         .main_clk       = "smartreflex0_fck",
 325         .prcm           = {
 326                 .omap4  = {
 327                         .modulemode     = MODULEMODE_SWCTRL,
 328                 },
 329         },
 330 };
 331
 332 /* smartreflex1 */
 333 struct omap_hwmod am33xx_smartreflex1_hwmod = {
 334         .name           = "smartreflex1",
 335         .class          = &am33xx_smartreflex_hwmod_class,
 336         .clkdm_name     = "l4_wkup_clkdm",
 337         .main_clk       = "smartreflex1_fck",
 338         .prcm           = {
 339                 .omap4  = {
 340                         .modulemode     = MODULEMODE_SWCTRL,
 341                 },
 342         },
 343 };
 344
 345 /*
 346  * 'control' module class
 347  */
 348 struct omap_hwmod_class am33xx_control_hwmod_class = {
 349         .name           = "control",
 350 };
 351
 352 /*
 353  * dcan class
 354  */
 355 static struct omap_hwmod_class am33xx_dcan_hwmod_class = {
 356         .name = "d_can",
 357 };
 358
 359 /* dcan0 */
 360 struct omap_hwmod am33xx_dcan0_hwmod = {
 361         .name           = "d_can0",
 362         .class          = &am33xx_dcan_hwmod_class,
 363         .clkdm_name     = "l4ls_clkdm",
 364         .main_clk       = "dcan0_fck",
 365         .prcm           = {
 366                 .omap4  = {
 367                         .modulemode     = MODULEMODE_SWCTRL,
 368                 },
 369         },
 370 };
 371
 372 /* dcan1 */
 373 struct omap_hwmod am33xx_dcan1_hwmod = {
 374         .name           = "d_can1",
 375         .class          = &am33xx_dcan_hwmod_class,
 376         .clkdm_name     = "l4ls_clkdm",
 377         .main_clk       = "dcan1_fck",
 378         .prcm           = {
 379                 .omap4  = {
 380                         .modulemode     = MODULEMODE_SWCTRL,
 381                 },
 382         },
 383 };
 384
 385 /* elm */
 386 static struct omap_hwmod_class_sysconfig am33xx_elm_sysc = {
 387         .rev_offs       = 0x0000,
 388         .sysc_offs      = 0x0010,
 389         .syss_offs      = 0x0014,
 390         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
 391                         SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
 392                         SYSS_HAS_RESET_STATUS),
 393         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 394         .sysc_fields    = &omap_hwmod_sysc_type1,
 395 };
 396
 397 static struct omap_hwmod_class am33xx_elm_hwmod_class = {
 398         .name           = "elm",
 399         .sysc           = &am33xx_elm_sysc,
 400 };
 401
 402 struct omap_hwmod am33xx_elm_hwmod = {
 403         .name           = "elm",
 404         .class          = &am33xx_elm_hwmod_class,
 405         .clkdm_name     = "l4ls_clkdm",
 406         .main_clk       = "l4ls_gclk",
 407         .prcm           = {
 408                 .omap4  = {
 409                         .modulemode     = MODULEMODE_SWCTRL,
 410                 },
 411         },
 412 };
 413
 414 /* pwmss  */
 415 static struct omap_hwmod_class_sysconfig am33xx_epwmss_sysc = {
 416         .rev_offs       = 0x0,
 417         .sysc_offs      = 0x4,
 418         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
 419         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 420                         SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
 421                         MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
 422         .sysc_fields    = &omap_hwmod_sysc_type2,
 423 };
 424
 425 struct omap_hwmod_class am33xx_epwmss_hwmod_class = {
 426         .name           = "epwmss",
 427         .sysc           = &am33xx_epwmss_sysc,
 428 };
 429
 430 /* epwmss0 */
 431 struct omap_hwmod am33xx_epwmss0_hwmod = {
 432         .name           = "epwmss0",
 433         .class          = &am33xx_epwmss_hwmod_class,
 434         .clkdm_name     = "l4ls_clkdm",
 435         .main_clk       = "l4ls_gclk",
 436         .prcm           = {
 437                 .omap4  = {
 438                         .modulemode     = MODULEMODE_SWCTRL,
 439                 },
 440         },
 441 };
 442
 443 /* epwmss1 */
 444 struct omap_hwmod am33xx_epwmss1_hwmod = {
 445         .name           = "epwmss1",
 446         .class          = &am33xx_epwmss_hwmod_class,
 447         .clkdm_name     = "l4ls_clkdm",
 448         .main_clk       = "l4ls_gclk",
 449         .prcm           = {
 450                 .omap4  = {
 451                         .modulemode     = MODULEMODE_SWCTRL,
 452                 },
 453         },
 454 };
 455
 456 /* epwmss2 */
 457 struct omap_hwmod am33xx_epwmss2_hwmod = {
 458         .name           = "epwmss2",
 459         .class          = &am33xx_epwmss_hwmod_class,
 460         .clkdm_name     = "l4ls_clkdm",
 461         .main_clk       = "l4ls_gclk",
 462         .prcm           = {
 463                 .omap4  = {
 464                         .modulemode     = MODULEMODE_SWCTRL,
 465                 },
 466         },
 467 };
 468
 469 /* gpmc */
 470 static struct omap_hwmod_class_sysconfig gpmc_sysc = {
 471         .rev_offs       = 0x0,
 472         .sysc_offs      = 0x10,
 473         .syss_offs      = 0x14,
 474         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
 475                         SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 476         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 477         .sysc_fields    = &omap_hwmod_sysc_type1,
 478 };
 479
 480 static struct omap_hwmod_class am33xx_gpmc_hwmod_class = {
 481         .name           = "gpmc",
 482         .sysc           = &gpmc_sysc,
 483 };
 484
 485 struct omap_hwmod am33xx_gpmc_hwmod = {
 486         .name           = "gpmc",
 487         .class          = &am33xx_gpmc_hwmod_class,
 488         .clkdm_name     = "l3s_clkdm",
 489         /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
 490         .flags          = DEBUG_OMAP_GPMC_HWMOD_FLAGS,
 491         .main_clk       = "l3s_gclk",
 492         .prcm           = {
 493                 .omap4  = {
 494                         .modulemode     = MODULEMODE_SWCTRL,
 495                 },
 496         },
 497 };
 498
 499 /*
 500  * 'mailbox' class
 501  * mailbox module allowing communication between the on-chip processors using a
 502  * queued mailbox-interrupt mechanism.
 503  */
 504 static struct omap_hwmod_class_sysconfig am33xx_mailbox_sysc = {
 505         .rev_offs       = 0x0000,
 506         .sysc_offs      = 0x0010,
 507         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
 508                           SYSC_HAS_SOFTRESET),
 509         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 510         .sysc_fields    = &omap_hwmod_sysc_type2,
 511 };
 512
 513 static struct omap_hwmod_class am33xx_mailbox_hwmod_class = {
 514         .name   = "mailbox",
 515         .sysc   = &am33xx_mailbox_sysc,
 516 };
 517
 518 struct omap_hwmod am33xx_mailbox_hwmod = {
 519         .name           = "mailbox",
 520         .class          = &am33xx_mailbox_hwmod_class,
 521         .clkdm_name     = "l4ls_clkdm",
 522         .main_clk       = "l4ls_gclk",
 523         .prcm = {
 524                 .omap4 = {
 525                         .modulemode     = MODULEMODE_SWCTRL,
 526                 },
 527         },
 528 };
 529
 530 /*
 531  * 'mcasp' class
 532  */
 533 static struct omap_hwmod_class_sysconfig am33xx_mcasp_sysc = {
 534         .rev_offs       = 0x0,
 535         .sysc_offs      = 0x4,
 536         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 537         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 538         .sysc_fields    = &omap_hwmod_sysc_type3,
 539 };
 540
 541 static struct omap_hwmod_class am33xx_mcasp_hwmod_class = {
 542         .name           = "mcasp",
 543         .sysc           = &am33xx_mcasp_sysc,
 544 };
 545
 546 /* mcasp0 */
 547 struct omap_hwmod am33xx_mcasp0_hwmod = {
 548         .name           = "mcasp0",
 549         .class          = &am33xx_mcasp_hwmod_class,
 550         .clkdm_name     = "l3s_clkdm",
 551         .main_clk       = "mcasp0_fck",
 552         .prcm           = {
 553                 .omap4  = {
 554                         .modulemode     = MODULEMODE_SWCTRL,
 555                 },
 556         },
 557 };
 558
 559 /* mcasp1 */
 560 struct omap_hwmod am33xx_mcasp1_hwmod = {
 561         .name           = "mcasp1",
 562         .class          = &am33xx_mcasp_hwmod_class,
 563         .clkdm_name     = "l3s_clkdm",
 564         .main_clk       = "mcasp1_fck",
 565         .prcm           = {
 566                 .omap4  = {
 567                         .modulemode     = MODULEMODE_SWCTRL,
 568                 },
 569         },
 570 };
 571
 572 /*
 573  * 'rtc' class
 574  * rtc subsystem
 575  */
 576 static struct omap_hwmod_class_sysconfig am33xx_rtc_sysc = {
 577         .rev_offs       = 0x0074,
 578         .sysc_offs      = 0x0078,
 579         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 580         .idlemodes      = (SIDLE_FORCE | SIDLE_NO |
 581                           SIDLE_SMART | SIDLE_SMART_WKUP),
 582         .sysc_fields    = &omap_hwmod_sysc_type3,
 583 };
 584
 585 static struct omap_hwmod_class am33xx_rtc_hwmod_class = {
 586         .name           = "rtc",
 587         .sysc           = &am33xx_rtc_sysc,
 588         .unlock         = &omap_hwmod_rtc_unlock,
 589         .lock           = &omap_hwmod_rtc_lock,
 590 };
 591
 592 struct omap_hwmod am33xx_rtc_hwmod = {
 593         .name           = "rtc",
 594         .class          = &am33xx_rtc_hwmod_class,
 595         .clkdm_name     = "l4_rtc_clkdm",
 596         .main_clk       = "clk_32768_ck",
 597         .prcm           = {
 598                 .omap4  = {
 599                         .modulemode     = MODULEMODE_SWCTRL,
 600                 },
 601         },
 602 };
 603
 604 /* 'spi' class */
 605 static struct omap_hwmod_class_sysconfig am33xx_mcspi_sysc = {
 606         .rev_offs       = 0x0000,
 607         .sysc_offs      = 0x0110,
 608         .syss_offs      = 0x0114,
 609         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
 610                           SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
 611                           SYSS_HAS_RESET_STATUS),
 612         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 613         .sysc_fields    = &omap_hwmod_sysc_type1,
 614 };
 615
 616 struct omap_hwmod_class am33xx_spi_hwmod_class = {
 617         .name           = "mcspi",
 618         .sysc           = &am33xx_mcspi_sysc,
 619 };
 620
 621 /* spi0 */
 622 struct omap_hwmod am33xx_spi0_hwmod = {
 623         .name           = "spi0",
 624         .class          = &am33xx_spi_hwmod_class,
 625         .clkdm_name     = "l4ls_clkdm",
 626         .main_clk       = "dpll_per_m2_div4_ck",
 627         .prcm           = {
 628                 .omap4  = {
 629                         .modulemode     = MODULEMODE_SWCTRL,
 630                 },
 631         },
 632 };
 633
 634 /* spi1 */
 635 struct omap_hwmod am33xx_spi1_hwmod = {
 636         .name           = "spi1",
 637         .class          = &am33xx_spi_hwmod_class,
 638         .clkdm_name     = "l4ls_clkdm",
 639         .main_clk       = "dpll_per_m2_div4_ck",
 640         .prcm           = {
 641                 .omap4  = {
 642                         .modulemode     = MODULEMODE_SWCTRL,
 643                 },
 644         },
 645 };
 646
 647 /*
 648  * 'spinlock' class
 649  * spinlock provides hardware assistance for synchronizing the
 650  * processes running on multiple processors
 651  */
 652
 653 static struct omap_hwmod_class_sysconfig am33xx_spinlock_sysc = {
 654         .rev_offs       = 0x0000,
 655         .sysc_offs      = 0x0010,
 656         .syss_offs      = 0x0014,
 657         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 658                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 659                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 660         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 661         .sysc_fields    = &omap_hwmod_sysc_type1,
 662 };
 663
 664 static struct omap_hwmod_class am33xx_spinlock_hwmod_class = {
 665         .name           = "spinlock",
 666         .sysc           = &am33xx_spinlock_sysc,
 667 };
 668
 669 struct omap_hwmod am33xx_spinlock_hwmod = {
 670         .name           = "spinlock",
 671         .class          = &am33xx_spinlock_hwmod_class,
 672         .clkdm_name     = "l4ls_clkdm",
 673         .main_clk       = "l4ls_gclk",
 674         .prcm           = {
 675                 .omap4  = {
 676                         .modulemode     = MODULEMODE_SWCTRL,
 677                 },
 678         },
 679 };
 680
 681 /* 'timer 2-7' class */
 682 static struct omap_hwmod_class_sysconfig am33xx_timer_sysc = {
 683         .rev_offs       = 0x0000,
 684         .sysc_offs      = 0x0010,
 685         .syss_offs      = 0x0014,
 686         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
 687         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 688                           SIDLE_SMART_WKUP),
 689         .sysc_fields    = &omap_hwmod_sysc_type2,
 690 };
 691
 692 struct omap_hwmod_class am33xx_timer_hwmod_class = {
 693         .name           = "timer",
 694         .sysc           = &am33xx_timer_sysc,
 695 };
 696
 697 /* timer1 1ms */
 698 static struct omap_hwmod_class_sysconfig am33xx_timer1ms_sysc = {
 699         .rev_offs       = 0x0000,
 700         .sysc_offs      = 0x0010,
 701         .syss_offs      = 0x0014,
 702         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
 703                         SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
 704                         SYSS_HAS_RESET_STATUS),
 705         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 706         .sysc_fields    = &omap_hwmod_sysc_type1,
 707 };
 708
 709 static struct omap_hwmod_class am33xx_timer1ms_hwmod_class = {
 710         .name           = "timer",
 711         .sysc           = &am33xx_timer1ms_sysc,
 712 };
 713
 714 struct omap_hwmod am33xx_timer1_hwmod = {
 715         .name           = "timer1",
 716         .class          = &am33xx_timer1ms_hwmod_class,
 717         .clkdm_name     = "l4_wkup_clkdm",
 718         .main_clk       = "timer1_fck",
 719         .prcm           = {
 720                 .omap4  = {
 721                         .modulemode     = MODULEMODE_SWCTRL,
 722                 },
 723         },
 724 };
 725
 726 struct omap_hwmod am33xx_timer2_hwmod = {
 727         .name           = "timer2",
 728         .class          = &am33xx_timer_hwmod_class,
 729         .clkdm_name     = "l4ls_clkdm",
 730         .main_clk       = "timer2_fck",
 731         .prcm           = {
 732                 .omap4  = {
 733                         .modulemode     = MODULEMODE_SWCTRL,
 734                 },
 735         },
 736 };
 737
 738 struct omap_hwmod am33xx_timer3_hwmod = {
 739         .name           = "timer3",
 740         .class          = &am33xx_timer_hwmod_class,
 741         .clkdm_name     = "l4ls_clkdm",
 742         .main_clk       = "timer3_fck",
 743         .prcm           = {
 744                 .omap4  = {
 745                         .modulemode     = MODULEMODE_SWCTRL,
 746                 },
 747         },
 748 };
 749
 750 struct omap_hwmod am33xx_timer4_hwmod = {
 751         .name           = "timer4",
 752         .class          = &am33xx_timer_hwmod_class,
 753         .clkdm_name     = "l4ls_clkdm",
 754         .main_clk       = "timer4_fck",
 755         .prcm           = {
 756                 .omap4  = {
 757                         .modulemode     = MODULEMODE_SWCTRL,
 758                 },
 759         },
 760 };
 761
 762 struct omap_hwmod am33xx_timer5_hwmod = {
 763         .name           = "timer5",
 764         .class          = &am33xx_timer_hwmod_class,
 765         .clkdm_name     = "l4ls_clkdm",
 766         .main_clk       = "timer5_fck",
 767         .prcm           = {
 768                 .omap4  = {
 769                         .modulemode     = MODULEMODE_SWCTRL,
 770                 },
 771         },
 772 };
 773
 774 struct omap_hwmod am33xx_timer6_hwmod = {
 775         .name           = "timer6",
 776         .class          = &am33xx_timer_hwmod_class,
 777         .clkdm_name     = "l4ls_clkdm",
 778         .main_clk       = "timer6_fck",
 779         .prcm           = {
 780                 .omap4  = {
 781                         .modulemode     = MODULEMODE_SWCTRL,
 782                 },
 783         },
 784 };
 785
 786 struct omap_hwmod am33xx_timer7_hwmod = {
 787         .name           = "timer7",
 788         .class          = &am33xx_timer_hwmod_class,
 789         .clkdm_name     = "l4ls_clkdm",
 790         .main_clk       = "timer7_fck",
 791         .prcm           = {
 792                 .omap4  = {
 793                         .modulemode     = MODULEMODE_SWCTRL,
 794                 },
 795         },
 796 };
 797
 798 /* tpcc */
 799 static struct omap_hwmod_class am33xx_tpcc_hwmod_class = {
 800         .name           = "tpcc",
 801 };
 802
 803 struct omap_hwmod am33xx_tpcc_hwmod = {
 804         .name           = "tpcc",
 805         .class          = &am33xx_tpcc_hwmod_class,
 806         .clkdm_name     = "l3_clkdm",
 807         .main_clk       = "l3_gclk",
 808         .prcm           = {
 809                 .omap4  = {
 810                         .modulemode     = MODULEMODE_SWCTRL,
 811                 },
 812         },
 813 };
 814
 815 static struct omap_hwmod_class_sysconfig am33xx_tptc_sysc = {
 816         .rev_offs       = 0x0,
 817         .sysc_offs      = 0x10,
 818         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 819                           SYSC_HAS_MIDLEMODE),
 820         .idlemodes      = (SIDLE_FORCE | SIDLE_SMART | MSTANDBY_FORCE),
 821         .sysc_fields    = &omap_hwmod_sysc_type2,
 822 };
 823
 824 /* 'tptc' class */
 825 static struct omap_hwmod_class am33xx_tptc_hwmod_class = {
 826         .name           = "tptc",
 827         .sysc           = &am33xx_tptc_sysc,
 828 };
 829
 830 /* tptc0 */
 831 struct omap_hwmod am33xx_tptc0_hwmod = {
 832         .name           = "tptc0",
 833         .class          = &am33xx_tptc_hwmod_class,
 834         .clkdm_name     = "l3_clkdm",
 835         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
 836         .main_clk       = "l3_gclk",
 837         .prcm           = {
 838                 .omap4  = {
 839                         .modulemode     = MODULEMODE_SWCTRL,
 840                 },
 841         },
 842 };
 843
 844 /* tptc1 */
 845 struct omap_hwmod am33xx_tptc1_hwmod = {
 846         .name           = "tptc1",
 847         .class          = &am33xx_tptc_hwmod_class,
 848         .clkdm_name     = "l3_clkdm",
 849         .flags          = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
 850         .main_clk       = "l3_gclk",
 851         .prcm           = {
 852                 .omap4  = {
 853                         .modulemode     = MODULEMODE_SWCTRL,
 854                 },
 855         },
 856 };
 857
 858 /* tptc2 */
 859 struct omap_hwmod am33xx_tptc2_hwmod = {
 860         .name           = "tptc2",
 861         .class          = &am33xx_tptc_hwmod_class,
 862         .clkdm_name     = "l3_clkdm",
 863         .flags          = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
 864         .main_clk       = "l3_gclk",
 865         .prcm           = {
 866                 .omap4  = {
 867                         .modulemode     = MODULEMODE_SWCTRL,
 868                 },
 869         },
 870 };
 871
 872 /* 'wd_timer' class */
 873 static struct omap_hwmod_class_sysconfig wdt_sysc = {
 874         .rev_offs       = 0x0,
 875         .sysc_offs      = 0x10,
 876         .syss_offs      = 0x14,
 877         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
 878                         SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 879         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 880                         SIDLE_SMART_WKUP),
 881         .sysc_fields    = &omap_hwmod_sysc_type1,
 882 };
 883
 884 static struct omap_hwmod_class am33xx_wd_timer_hwmod_class = {
 885         .name           = "wd_timer",
 886         .sysc           = &wdt_sysc,
 887         .pre_shutdown   = &omap2_wd_timer_disable,
 888 };
 889
 890 /*
 891  * XXX: device.c file uses hardcoded name for watchdog timer
 892  * driver "wd_timer2, so we are also using same name as of now...
 893  */
 894 struct omap_hwmod am33xx_wd_timer1_hwmod = {
 895         .name           = "wd_timer2",
 896         .class          = &am33xx_wd_timer_hwmod_class,
 897         .clkdm_name     = "l4_wkup_clkdm",
 898         .flags          = HWMOD_SWSUP_SIDLE,
 899         .main_clk       = "wdt1_fck",
 900         .prcm           = {
 901                 .omap4  = {
 902                         .modulemode     = MODULEMODE_SWCTRL,
 903                 },
 904         },
 905 };
 906
 907 static void omap_hwmod_am33xx_clkctrl(void)
 908 {
 909         CLKCTRL(am33xx_dcan0_hwmod, AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET);
 910         CLKCTRL(am33xx_dcan1_hwmod, AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET);
 911         CLKCTRL(am33xx_elm_hwmod, AM33XX_CM_PER_ELM_CLKCTRL_OFFSET);
 912         CLKCTRL(am33xx_epwmss0_hwmod, AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET);
 913         CLKCTRL(am33xx_epwmss1_hwmod, AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET);
 914         CLKCTRL(am33xx_epwmss2_hwmod, AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET);
 915         CLKCTRL(am33xx_mailbox_hwmod, AM33XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET);
 916         CLKCTRL(am33xx_mcasp0_hwmod, AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET);
 917         CLKCTRL(am33xx_mcasp1_hwmod, AM33XX_CM_PER_MCASP1_CLKCTRL_OFFSET);
 918         CLKCTRL(am33xx_spi0_hwmod, AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET);
 919         CLKCTRL(am33xx_spi1_hwmod, AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET);
 920         CLKCTRL(am33xx_spinlock_hwmod, AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET);
 921         CLKCTRL(am33xx_timer2_hwmod, AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET);
 922         CLKCTRL(am33xx_timer3_hwmod, AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET);
 923         CLKCTRL(am33xx_timer4_hwmod, AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET);
 924         CLKCTRL(am33xx_timer5_hwmod, AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET);
 925         CLKCTRL(am33xx_timer6_hwmod, AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET);
 926         CLKCTRL(am33xx_timer7_hwmod, AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET);
 927         CLKCTRL(am33xx_smartreflex0_hwmod,
 928                 AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET);
 929         CLKCTRL(am33xx_smartreflex1_hwmod,
 930                 AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET);
 931         CLKCTRL(am33xx_timer1_hwmod, AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET);
 932         CLKCTRL(am33xx_wd_timer1_hwmod, AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET);
 933         CLKCTRL(am33xx_rtc_hwmod, AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET);
 934         PRCM_FLAGS(am33xx_rtc_hwmod, HWMOD_OMAP4_ZERO_CLKCTRL_OFFSET);
 935         CLKCTRL(am33xx_gpmc_hwmod, AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET);
 936         CLKCTRL(am33xx_l4_ls_hwmod, AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET);
 937         CLKCTRL(am33xx_l4_wkup_hwmod, AM33XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET);
 938         CLKCTRL(am33xx_l3_main_hwmod, AM33XX_CM_PER_L3_CLKCTRL_OFFSET);
 939         CLKCTRL(am33xx_tpcc_hwmod, AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET);
 940         CLKCTRL(am33xx_tptc0_hwmod, AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET);
 941         CLKCTRL(am33xx_tptc1_hwmod, AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET);
 942         CLKCTRL(am33xx_tptc2_hwmod, AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET);
 943         CLKCTRL(am33xx_gfx_hwmod, AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET);
 944         CLKCTRL(am33xx_pruss_hwmod, AM33XX_CM_PER_PRUSS_CLKCTRL_OFFSET);
 945         CLKCTRL(am33xx_mpu_hwmod , AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET);
 946         CLKCTRL(am33xx_l3_instr_hwmod , AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET);
 947         CLKCTRL(am33xx_ocmcram_hwmod , AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET);
 948         CLKCTRL(am33xx_sha0_hwmod , AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET);
 949         CLKCTRL(am33xx_aes0_hwmod , AM33XX_CM_PER_AES0_CLKCTRL_OFFSET);
 950         CLKCTRL(am33xx_rng_hwmod, AM33XX_CM_PER_RNG_CLKCTRL_OFFSET);
 951 }
 952
 953 static void omap_hwmod_am33xx_rst(void)
 954 {
 955         RSTCTRL(am33xx_pruss_hwmod, AM33XX_RM_PER_RSTCTRL_OFFSET);
 956         RSTCTRL(am33xx_gfx_hwmod, AM33XX_RM_GFX_RSTCTRL_OFFSET);
 957         RSTST(am33xx_gfx_hwmod, AM33XX_RM_GFX_RSTST_OFFSET);
 958 }
 959
 960 void omap_hwmod_am33xx_reg(void)
 961 {
 962         omap_hwmod_am33xx_clkctrl();
 963         omap_hwmod_am33xx_rst();
 964 }
 965
 966 static void omap_hwmod_am43xx_clkctrl(void)
 967 {
 968         CLKCTRL(am33xx_dcan0_hwmod, AM43XX_CM_PER_DCAN0_CLKCTRL_OFFSET);
 969         CLKCTRL(am33xx_dcan1_hwmod, AM43XX_CM_PER_DCAN1_CLKCTRL_OFFSET);
 970         CLKCTRL(am33xx_elm_hwmod, AM43XX_CM_PER_ELM_CLKCTRL_OFFSET);
 971         CLKCTRL(am33xx_epwmss0_hwmod, AM43XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET);
 972         CLKCTRL(am33xx_epwmss1_hwmod, AM43XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET);
 973         CLKCTRL(am33xx_epwmss2_hwmod, AM43XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET);
 974         CLKCTRL(am33xx_mailbox_hwmod, AM43XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET);
 975         CLKCTRL(am33xx_mcasp0_hwmod, AM43XX_CM_PER_MCASP0_CLKCTRL_OFFSET);
 976         CLKCTRL(am33xx_mcasp1_hwmod, AM43XX_CM_PER_MCASP1_CLKCTRL_OFFSET);
 977         CLKCTRL(am33xx_spi0_hwmod, AM43XX_CM_PER_SPI0_CLKCTRL_OFFSET);
 978         CLKCTRL(am33xx_spi1_hwmod, AM43XX_CM_PER_SPI1_CLKCTRL_OFFSET);
 979         CLKCTRL(am33xx_spinlock_hwmod, AM43XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET);
 980         CLKCTRL(am33xx_timer2_hwmod, AM43XX_CM_PER_TIMER2_CLKCTRL_OFFSET);
 981         CLKCTRL(am33xx_timer3_hwmod, AM43XX_CM_PER_TIMER3_CLKCTRL_OFFSET);
 982         CLKCTRL(am33xx_timer4_hwmod, AM43XX_CM_PER_TIMER4_CLKCTRL_OFFSET);
 983         CLKCTRL(am33xx_timer5_hwmod, AM43XX_CM_PER_TIMER5_CLKCTRL_OFFSET);
 984         CLKCTRL(am33xx_timer6_hwmod, AM43XX_CM_PER_TIMER6_CLKCTRL_OFFSET);
 985         CLKCTRL(am33xx_timer7_hwmod, AM43XX_CM_PER_TIMER7_CLKCTRL_OFFSET);
 986         CLKCTRL(am33xx_smartreflex0_hwmod,
 987                 AM43XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET);
 988         CLKCTRL(am33xx_smartreflex1_hwmod,
 989                 AM43XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET);
 990         CLKCTRL(am33xx_timer1_hwmod, AM43XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET);
 991         CLKCTRL(am33xx_wd_timer1_hwmod, AM43XX_CM_WKUP_WDT1_CLKCTRL_OFFSET);
 992         CLKCTRL(am33xx_rtc_hwmod, AM43XX_CM_RTC_RTC_CLKCTRL_OFFSET);
 993         CLKCTRL(am33xx_gpmc_hwmod, AM43XX_CM_PER_GPMC_CLKCTRL_OFFSET);
 994         CLKCTRL(am33xx_l4_ls_hwmod, AM43XX_CM_PER_L4LS_CLKCTRL_OFFSET);
 995         CLKCTRL(am33xx_l4_wkup_hwmod, AM43XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET);
 996         CLKCTRL(am33xx_l3_main_hwmod, AM43XX_CM_PER_L3_CLKCTRL_OFFSET);
 997         CLKCTRL(am33xx_tpcc_hwmod, AM43XX_CM_PER_TPCC_CLKCTRL_OFFSET);
 998         CLKCTRL(am33xx_tptc0_hwmod, AM43XX_CM_PER_TPTC0_CLKCTRL_OFFSET);
 999         CLKCTRL(am33xx_tptc1_hwmod, AM43XX_CM_PER_TPTC1_CLKCTRL_OFFSET);
1000         CLKCTRL(am33xx_tptc2_hwmod, AM43XX_CM_PER_TPTC2_CLKCTRL_OFFSET);
1001         CLKCTRL(am33xx_gfx_hwmod, AM43XX_CM_GFX_GFX_CLKCTRL_OFFSET);
1002         CLKCTRL(am33xx_pruss_hwmod, AM43XX_CM_PER_PRUSS_CLKCTRL_OFFSET);
1003         CLKCTRL(am33xx_mpu_hwmod , AM43XX_CM_MPU_MPU_CLKCTRL_OFFSET);
1004         CLKCTRL(am33xx_l3_instr_hwmod , AM43XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET);
1005         CLKCTRL(am33xx_ocmcram_hwmod , AM43XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET);
1006         CLKCTRL(am33xx_sha0_hwmod , AM43XX_CM_PER_SHA0_CLKCTRL_OFFSET);
1007         CLKCTRL(am33xx_aes0_hwmod , AM43XX_CM_PER_AES0_CLKCTRL_OFFSET);
1008         CLKCTRL(am33xx_rng_hwmod, AM43XX_CM_PER_RNG_CLKCTRL_OFFSET);
1009 }
1010
1011 static void omap_hwmod_am43xx_rst(void)
1012 {
1013         RSTCTRL(am33xx_pruss_hwmod, AM43XX_RM_PER_RSTCTRL_OFFSET);
1014         RSTCTRL(am33xx_gfx_hwmod, AM43XX_RM_GFX_RSTCTRL_OFFSET);
1015         RSTST(am33xx_pruss_hwmod, AM43XX_RM_PER_RSTST_OFFSET);
1016         RSTST(am33xx_gfx_hwmod, AM43XX_RM_GFX_RSTST_OFFSET);
1017 }
1018
1019 void omap_hwmod_am43xx_reg(void)
1020 {
1021         omap_hwmod_am43xx_clkctrl();
1022         omap_hwmod_am43xx_rst();
1023 }