arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c

   1 /*
   2  *
   3  * Copyright (C) 2013 Texas Instruments Incorporated
   4  *
   5  * Hwmod common for AM335x and AM43x
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation version 2.
  10  *
  11  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  12  * kind, whether express or implied; without even the implied warranty
  13  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <linux/types.h>
  18
  19 #include "omap_hwmod.h"
  20 #include "cm33xx.h"
  21 #include "prm33xx.h"
  22 #include "omap_hwmod_33xx_43xx_common_data.h"
  23 #include "prcm43xx.h"
  24 #include "common.h"
  25
  26 #define CLKCTRL(oh, clkctrl) ((oh).prcm.omap4.clkctrl_offs = (clkctrl))
  27 #define RSTCTRL(oh, rstctrl) ((oh).prcm.omap4.rstctrl_offs = (rstctrl))
  28 #define RSTST(oh, rstst) ((oh).prcm.omap4.rstst_offs = (rstst))
  29 #define PRCM_FLAGS(oh, flag) ((oh).prcm.omap4.flags = (flag))
  30
  31 /*
  32  * 'l3' class
  33  * instance(s): l3_main, l3_s, l3_instr
  34  */
  35 static struct omap_hwmod_class am33xx_l3_hwmod_class = {
  36         .name           = "l3",
  37 };
  38
  39 struct omap_hwmod am33xx_l3_main_hwmod = {
  40         .name           = "l3_main",
  41         .class          = &am33xx_l3_hwmod_class,
  42         .clkdm_name     = "l3_clkdm",
  43         .flags          = HWMOD_INIT_NO_IDLE,
  44         .main_clk       = "l3_gclk",
  45         .prcm           = {
  46                 .omap4  = {
  47                         .modulemode     = MODULEMODE_SWCTRL,
  48                 },
  49         },
  50 };
  51
  52 /* l3_s */
  53 struct omap_hwmod am33xx_l3_s_hwmod = {
  54         .name           = "l3_s",
  55         .class          = &am33xx_l3_hwmod_class,
  56         .clkdm_name     = "l3s_clkdm",
  57 };
  58
  59 /* l3_instr */
  60 struct omap_hwmod am33xx_l3_instr_hwmod = {
  61         .name           = "l3_instr",
  62         .class          = &am33xx_l3_hwmod_class,
  63         .clkdm_name     = "l3_clkdm",
  64         .flags          = HWMOD_INIT_NO_IDLE,
  65         .main_clk       = "l3_gclk",
  66         .prcm           = {
  67                 .omap4  = {
  68                         .modulemode     = MODULEMODE_SWCTRL,
  69                 },
  70         },
  71 };
  72
  73 /*
  74  * 'l4' class
  75  * instance(s): l4_ls, l4_hs, l4_wkup, l4_fw
  76  */
  77 struct omap_hwmod_class am33xx_l4_hwmod_class = {
  78         .name           = "l4",
  79 };
  80
  81 /* l4_ls */
  82 struct omap_hwmod am33xx_l4_ls_hwmod = {
  83         .name           = "l4_ls",
  84         .class          = &am33xx_l4_hwmod_class,
  85         .clkdm_name     = "l4ls_clkdm",
  86         .flags          = HWMOD_INIT_NO_IDLE,
  87         .main_clk       = "l4ls_gclk",
  88         .prcm           = {
  89                 .omap4  = {
  90                         .modulemode     = MODULEMODE_SWCTRL,
  91                 },
  92         },
  93 };
  94
  95 /* l4_wkup */
  96 struct omap_hwmod am33xx_l4_wkup_hwmod = {
  97         .name           = "l4_wkup",
  98         .class          = &am33xx_l4_hwmod_class,
  99         .clkdm_name     = "l4_wkup_clkdm",
 100         .flags          = HWMOD_INIT_NO_IDLE,
 101         .prcm           = {
 102                 .omap4  = {
 103                         .modulemode     = MODULEMODE_SWCTRL,
 104                 },
 105         },
 106 };
 107
 108 /*
 109  * 'mpu' class
 110  */
 111 static struct omap_hwmod_class am33xx_mpu_hwmod_class = {
 112         .name   = "mpu",
 113 };
 114
 115 struct omap_hwmod am33xx_mpu_hwmod = {
 116         .name           = "mpu",
 117         .class          = &am33xx_mpu_hwmod_class,
 118         .clkdm_name     = "mpu_clkdm",
 119         .flags          = HWMOD_INIT_NO_IDLE,
 120         .main_clk       = "dpll_mpu_m2_ck",
 121         .prcm           = {
 122                 .omap4  = {
 123                         .modulemode     = MODULEMODE_SWCTRL,
 124                 },
 125         },
 126 };
 127
 128 /*
 129  * 'wakeup m3' class
 130  * Wakeup controller sub-system under wakeup domain
 131  */
 132 struct omap_hwmod_class am33xx_wkup_m3_hwmod_class = {
 133         .name           = "wkup_m3",
 134 };
 135
 136 /*
 137  * 'pru-icss' class
 138  * Programmable Real-Time Unit and Industrial Communication Subsystem
 139  */
 140 static struct omap_hwmod_class am33xx_pruss_hwmod_class = {
 141         .name   = "pruss",
 142 };
 143
 144 static struct omap_hwmod_rst_info am33xx_pruss_resets[] = {
 145         { .name = "pruss", .rst_shift = 1 },
 146 };
 147
 148 /* pru-icss */
 149 /* Pseudo hwmod for reset control purpose only */
 150 struct omap_hwmod am33xx_pruss_hwmod = {
 151         .name           = "pruss",
 152         .class          = &am33xx_pruss_hwmod_class,
 153         .clkdm_name     = "pruss_ocp_clkdm",
 154         .main_clk       = "pruss_ocp_gclk",
 155         .prcm           = {
 156                 .omap4  = {
 157                         .modulemode     = MODULEMODE_SWCTRL,
 158                 },
 159         },
 160         .rst_lines      = am33xx_pruss_resets,
 161         .rst_lines_cnt  = ARRAY_SIZE(am33xx_pruss_resets),
 162 };
 163
 164 /* gfx */
 165 /* Pseudo hwmod for reset control purpose only */
 166 static struct omap_hwmod_class am33xx_gfx_hwmod_class = {
 167         .name   = "gfx",
 168 };
 169
 170 static struct omap_hwmod_rst_info am33xx_gfx_resets[] = {
 171         { .name = "gfx", .rst_shift = 0, .st_shift = 0},
 172 };
 173
 174 struct omap_hwmod am33xx_gfx_hwmod = {
 175         .name           = "gfx",
 176         .class          = &am33xx_gfx_hwmod_class,
 177         .clkdm_name     = "gfx_l3_clkdm",
 178         .main_clk       = "gfx_fck_div_ck",
 179         .prcm           = {
 180                 .omap4  = {
 181                         .modulemode     = MODULEMODE_SWCTRL,
 182                 },
 183         },
 184         .rst_lines      = am33xx_gfx_resets,
 185         .rst_lines_cnt  = ARRAY_SIZE(am33xx_gfx_resets),
 186 };
 187
 188 /*
 189  * 'prcm' class
 190  * power and reset manager (whole prcm infrastructure)
 191  */
 192 static struct omap_hwmod_class am33xx_prcm_hwmod_class = {
 193         .name   = "prcm",
 194 };
 195
 196 /* prcm */
 197 struct omap_hwmod am33xx_prcm_hwmod = {
 198         .name           = "prcm",
 199         .class          = &am33xx_prcm_hwmod_class,
 200         .clkdm_name     = "l4_wkup_clkdm",
 201 };
 202
 203 /*
 204  * 'emif' class
 205  * instance(s): emif
 206  */
 207 static struct omap_hwmod_class_sysconfig am33xx_emif_sysc = {
 208         .rev_offs       = 0x0000,
 209 };
 210
 211 struct omap_hwmod_class am33xx_emif_hwmod_class = {
 212         .name           = "emif",
 213         .sysc           = &am33xx_emif_sysc,
 214 };
 215
 216 /*
 217  * 'aes0' class
 218  */
 219 static struct omap_hwmod_class_sysconfig am33xx_aes0_sysc = {
 220         .rev_offs       = 0x80,
 221         .sysc_offs      = 0x84,
 222         .syss_offs      = 0x88,
 223         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 224 };
 225
 226 static struct omap_hwmod_class am33xx_aes0_hwmod_class = {
 227         .name           = "aes0",
 228         .sysc           = &am33xx_aes0_sysc,
 229 };
 230
 231 struct omap_hwmod am33xx_aes0_hwmod = {
 232         .name           = "aes",
 233         .class          = &am33xx_aes0_hwmod_class,
 234         .clkdm_name     = "l3_clkdm",
 235         .main_clk       = "aes0_fck",
 236         .prcm           = {
 237                 .omap4  = {
 238                         .modulemode     = MODULEMODE_SWCTRL,
 239                 },
 240         },
 241 };
 242
 243 /* sha0 HIB2 (the 'P' (public) device) */
 244 static struct omap_hwmod_class_sysconfig am33xx_sha0_sysc = {
 245         .rev_offs       = 0x100,
 246         .sysc_offs      = 0x110,
 247         .syss_offs      = 0x114,
 248         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 249 };
 250
 251 static struct omap_hwmod_class am33xx_sha0_hwmod_class = {
 252         .name           = "sha0",
 253         .sysc           = &am33xx_sha0_sysc,
 254 };
 255
 256 struct omap_hwmod am33xx_sha0_hwmod = {
 257         .name           = "sham",
 258         .class          = &am33xx_sha0_hwmod_class,
 259         .clkdm_name     = "l3_clkdm",
 260         .main_clk       = "l3_gclk",
 261         .prcm           = {
 262                 .omap4  = {
 263                         .modulemode     = MODULEMODE_SWCTRL,
 264                 },
 265         },
 266 };
 267
 268 /* ocmcram */
 269 static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = {
 270         .name = "ocmcram",
 271 };
 272
 273 struct omap_hwmod am33xx_ocmcram_hwmod = {
 274         .name           = "ocmcram",
 275         .class          = &am33xx_ocmcram_hwmod_class,
 276         .clkdm_name     = "l3_clkdm",
 277         .flags          = HWMOD_INIT_NO_IDLE,
 278         .main_clk       = "l3_gclk",
 279         .prcm           = {
 280                 .omap4  = {
 281                         .modulemode     = MODULEMODE_SWCTRL,
 282                 },
 283         },
 284 };
 285
 286 /* 'smartreflex' class */
 287 static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = {
 288         .name           = "smartreflex",
 289 };
 290
 291 /* smartreflex0 */
 292 struct omap_hwmod am33xx_smartreflex0_hwmod = {
 293         .name           = "smartreflex0",
 294         .class          = &am33xx_smartreflex_hwmod_class,
 295         .clkdm_name     = "l4_wkup_clkdm",
 296         .main_clk       = "smartreflex0_fck",
 297         .prcm           = {
 298                 .omap4  = {
 299                         .modulemode     = MODULEMODE_SWCTRL,
 300                 },
 301         },
 302 };
 303
 304 /* smartreflex1 */
 305 struct omap_hwmod am33xx_smartreflex1_hwmod = {
 306         .name           = "smartreflex1",
 307         .class          = &am33xx_smartreflex_hwmod_class,
 308         .clkdm_name     = "l4_wkup_clkdm",
 309         .main_clk       = "smartreflex1_fck",
 310         .prcm           = {
 311                 .omap4  = {
 312                         .modulemode     = MODULEMODE_SWCTRL,
 313                 },
 314         },
 315 };
 316
 317 /*
 318  * 'control' module class
 319  */
 320 struct omap_hwmod_class am33xx_control_hwmod_class = {
 321         .name           = "control",
 322 };
 323
 324 /*
 325  * dcan class
 326  */
 327 static struct omap_hwmod_class am33xx_dcan_hwmod_class = {
 328         .name = "d_can",
 329 };
 330
 331 /* dcan0 */
 332 struct omap_hwmod am33xx_dcan0_hwmod = {
 333         .name           = "d_can0",
 334         .class          = &am33xx_dcan_hwmod_class,
 335         .clkdm_name     = "l4ls_clkdm",
 336         .main_clk       = "dcan0_fck",
 337         .prcm           = {
 338                 .omap4  = {
 339                         .modulemode     = MODULEMODE_SWCTRL,
 340                 },
 341         },
 342 };
 343
 344 /* dcan1 */
 345 struct omap_hwmod am33xx_dcan1_hwmod = {
 346         .name           = "d_can1",
 347         .class          = &am33xx_dcan_hwmod_class,
 348         .clkdm_name     = "l4ls_clkdm",
 349         .main_clk       = "dcan1_fck",
 350         .prcm           = {
 351                 .omap4  = {
 352                         .modulemode     = MODULEMODE_SWCTRL,
 353                 },
 354         },
 355 };
 356
 357 /* elm */
 358 static struct omap_hwmod_class_sysconfig am33xx_elm_sysc = {
 359         .rev_offs       = 0x0000,
 360         .sysc_offs      = 0x0010,
 361         .syss_offs      = 0x0014,
 362         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
 363                         SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
 364                         SYSS_HAS_RESET_STATUS),
 365         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 366         .sysc_fields    = &omap_hwmod_sysc_type1,
 367 };
 368
 369 static struct omap_hwmod_class am33xx_elm_hwmod_class = {
 370         .name           = "elm",
 371         .sysc           = &am33xx_elm_sysc,
 372 };
 373
 374 struct omap_hwmod am33xx_elm_hwmod = {
 375         .name           = "elm",
 376         .class          = &am33xx_elm_hwmod_class,
 377         .clkdm_name     = "l4ls_clkdm",
 378         .main_clk       = "l4ls_gclk",
 379         .prcm           = {
 380                 .omap4  = {
 381                         .modulemode     = MODULEMODE_SWCTRL,
 382                 },
 383         },
 384 };
 385
 386 /* pwmss  */
 387 static struct omap_hwmod_class_sysconfig am33xx_epwmss_sysc = {
 388         .rev_offs       = 0x0,
 389         .sysc_offs      = 0x4,
 390         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
 391         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 392                         SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
 393                         MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
 394         .sysc_fields    = &omap_hwmod_sysc_type2,
 395 };
 396
 397 struct omap_hwmod_class am33xx_epwmss_hwmod_class = {
 398         .name           = "epwmss",
 399         .sysc           = &am33xx_epwmss_sysc,
 400 };
 401
 402 /* epwmss0 */
 403 struct omap_hwmod am33xx_epwmss0_hwmod = {
 404         .name           = "epwmss0",
 405         .class          = &am33xx_epwmss_hwmod_class,
 406         .clkdm_name     = "l4ls_clkdm",
 407         .main_clk       = "l4ls_gclk",
 408         .prcm           = {
 409                 .omap4  = {
 410                         .modulemode     = MODULEMODE_SWCTRL,
 411                 },
 412         },
 413 };
 414
 415 /* epwmss1 */
 416 struct omap_hwmod am33xx_epwmss1_hwmod = {
 417         .name           = "epwmss1",
 418         .class          = &am33xx_epwmss_hwmod_class,
 419         .clkdm_name     = "l4ls_clkdm",
 420         .main_clk       = "l4ls_gclk",
 421         .prcm           = {
 422                 .omap4  = {
 423                         .modulemode     = MODULEMODE_SWCTRL,
 424                 },
 425         },
 426 };
 427
 428 /* epwmss2 */
 429 struct omap_hwmod am33xx_epwmss2_hwmod = {
 430         .name           = "epwmss2",
 431         .class          = &am33xx_epwmss_hwmod_class,
 432         .clkdm_name     = "l4ls_clkdm",
 433         .main_clk       = "l4ls_gclk",
 434         .prcm           = {
 435                 .omap4  = {
 436                         .modulemode     = MODULEMODE_SWCTRL,
 437                 },
 438         },
 439 };
 440
 441 /* gpmc */
 442 static struct omap_hwmod_class_sysconfig gpmc_sysc = {
 443         .rev_offs       = 0x0,
 444         .sysc_offs      = 0x10,
 445         .syss_offs      = 0x14,
 446         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
 447                         SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 448         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 449         .sysc_fields    = &omap_hwmod_sysc_type1,
 450 };
 451
 452 static struct omap_hwmod_class am33xx_gpmc_hwmod_class = {
 453         .name           = "gpmc",
 454         .sysc           = &gpmc_sysc,
 455 };
 456
 457 struct omap_hwmod am33xx_gpmc_hwmod = {
 458         .name           = "gpmc",
 459         .class          = &am33xx_gpmc_hwmod_class,
 460         .clkdm_name     = "l3s_clkdm",
 461         /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
 462         .flags          = DEBUG_OMAP_GPMC_HWMOD_FLAGS,
 463         .main_clk       = "l3s_gclk",
 464         .prcm           = {
 465                 .omap4  = {
 466                         .modulemode     = MODULEMODE_SWCTRL,
 467                 },
 468         },
 469 };
 470
 471
 472 /*
 473  * 'rtc' class
 474  * rtc subsystem
 475  */
 476 static struct omap_hwmod_class_sysconfig am33xx_rtc_sysc = {
 477         .rev_offs       = 0x0074,
 478         .sysc_offs      = 0x0078,
 479         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 480         .idlemodes      = (SIDLE_FORCE | SIDLE_NO |
 481                           SIDLE_SMART | SIDLE_SMART_WKUP),
 482         .sysc_fields    = &omap_hwmod_sysc_type3,
 483 };
 484
 485 static struct omap_hwmod_class am33xx_rtc_hwmod_class = {
 486         .name           = "rtc",
 487         .sysc           = &am33xx_rtc_sysc,
 488         .unlock         = &omap_hwmod_rtc_unlock,
 489         .lock           = &omap_hwmod_rtc_lock,
 490 };
 491
 492 struct omap_hwmod am33xx_rtc_hwmod = {
 493         .name           = "rtc",
 494         .class          = &am33xx_rtc_hwmod_class,
 495         .clkdm_name     = "l4_rtc_clkdm",
 496         .main_clk       = "clk_32768_ck",
 497         .prcm           = {
 498                 .omap4  = {
 499                         .modulemode     = MODULEMODE_SWCTRL,
 500                 },
 501         },
 502 };
 503
 504 /* 'spi' class */
 505 static struct omap_hwmod_class_sysconfig am33xx_mcspi_sysc = {
 506         .rev_offs       = 0x0000,
 507         .sysc_offs      = 0x0110,
 508         .syss_offs      = 0x0114,
 509         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
 510                           SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
 511                           SYSS_HAS_RESET_STATUS),
 512         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 513         .sysc_fields    = &omap_hwmod_sysc_type1,
 514 };
 515
 516 struct omap_hwmod_class am33xx_spi_hwmod_class = {
 517         .name           = "mcspi",
 518         .sysc           = &am33xx_mcspi_sysc,
 519 };
 520
 521 /* spi0 */
 522 struct omap_hwmod am33xx_spi0_hwmod = {
 523         .name           = "spi0",
 524         .class          = &am33xx_spi_hwmod_class,
 525         .clkdm_name     = "l4ls_clkdm",
 526         .main_clk       = "dpll_per_m2_div4_ck",
 527         .prcm           = {
 528                 .omap4  = {
 529                         .modulemode     = MODULEMODE_SWCTRL,
 530                 },
 531         },
 532 };
 533
 534 /* spi1 */
 535 struct omap_hwmod am33xx_spi1_hwmod = {
 536         .name           = "spi1",
 537         .class          = &am33xx_spi_hwmod_class,
 538         .clkdm_name     = "l4ls_clkdm",
 539         .main_clk       = "dpll_per_m2_div4_ck",
 540         .prcm           = {
 541                 .omap4  = {
 542                         .modulemode     = MODULEMODE_SWCTRL,
 543                 },
 544         },
 545 };
 546
 547 /*
 548  * 'spinlock' class
 549  * spinlock provides hardware assistance for synchronizing the
 550  * processes running on multiple processors
 551  */
 552
 553 static struct omap_hwmod_class_sysconfig am33xx_spinlock_sysc = {
 554         .rev_offs       = 0x0000,
 555         .sysc_offs      = 0x0010,
 556         .syss_offs      = 0x0014,
 557         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 558                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 559                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 560         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 561         .sysc_fields    = &omap_hwmod_sysc_type1,
 562 };
 563
 564 static struct omap_hwmod_class am33xx_spinlock_hwmod_class = {
 565         .name           = "spinlock",
 566         .sysc           = &am33xx_spinlock_sysc,
 567 };
 568
 569 struct omap_hwmod am33xx_spinlock_hwmod = {
 570         .name           = "spinlock",
 571         .class          = &am33xx_spinlock_hwmod_class,
 572         .clkdm_name     = "l4ls_clkdm",
 573         .main_clk       = "l4ls_gclk",
 574         .prcm           = {
 575                 .omap4  = {
 576                         .modulemode     = MODULEMODE_SWCTRL,
 577                 },
 578         },
 579 };
 580
 581 /* 'timer 2-7' class */
 582 static struct omap_hwmod_class_sysconfig am33xx_timer_sysc = {
 583         .rev_offs       = 0x0000,
 584         .sysc_offs      = 0x0010,
 585         .syss_offs      = 0x0014,
 586         .sysc_flags     = SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 587                           SYSC_HAS_RESET_STATUS,
 588         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 589                           SIDLE_SMART_WKUP),
 590         .sysc_fields    = &omap_hwmod_sysc_type2,
 591 };
 592
 593 struct omap_hwmod_class am33xx_timer_hwmod_class = {
 594         .name           = "timer",
 595         .sysc           = &am33xx_timer_sysc,
 596 };
 597
 598 /* timer1 1ms */
 599 static struct omap_hwmod_class_sysconfig am33xx_timer1ms_sysc = {
 600         .rev_offs       = 0x0000,
 601         .sysc_offs      = 0x0010,
 602         .syss_offs      = 0x0014,
 603         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
 604                         SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
 605                         SYSS_HAS_RESET_STATUS),
 606         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 607         .sysc_fields    = &omap_hwmod_sysc_type1,
 608 };
 609
 610 static struct omap_hwmod_class am33xx_timer1ms_hwmod_class = {
 611         .name           = "timer",
 612         .sysc           = &am33xx_timer1ms_sysc,
 613 };
 614
 615 struct omap_hwmod am33xx_timer1_hwmod = {
 616         .name           = "timer1",
 617         .class          = &am33xx_timer1ms_hwmod_class,
 618         .clkdm_name     = "l4_wkup_clkdm",
 619         .main_clk       = "timer1_fck",
 620         .prcm           = {
 621                 .omap4  = {
 622                         .modulemode     = MODULEMODE_SWCTRL,
 623                 },
 624         },
 625 };
 626
 627 struct omap_hwmod am33xx_timer2_hwmod = {
 628         .name           = "timer2",
 629         .class          = &am33xx_timer_hwmod_class,
 630         .clkdm_name     = "l4ls_clkdm",
 631         .main_clk       = "timer2_fck",
 632         .prcm           = {
 633                 .omap4  = {
 634                         .modulemode     = MODULEMODE_SWCTRL,
 635                 },
 636         },
 637 };
 638
 639 struct omap_hwmod am33xx_timer3_hwmod = {
 640         .name           = "timer3",
 641         .class          = &am33xx_timer_hwmod_class,
 642         .clkdm_name     = "l4ls_clkdm",
 643         .main_clk       = "timer3_fck",
 644         .prcm           = {
 645                 .omap4  = {
 646                         .modulemode     = MODULEMODE_SWCTRL,
 647                 },
 648         },
 649 };
 650
 651 struct omap_hwmod am33xx_timer4_hwmod = {
 652         .name           = "timer4",
 653         .class          = &am33xx_timer_hwmod_class,
 654         .clkdm_name     = "l4ls_clkdm",
 655         .main_clk       = "timer4_fck",
 656         .prcm           = {
 657                 .omap4  = {
 658                         .modulemode     = MODULEMODE_SWCTRL,
 659                 },
 660         },
 661 };
 662
 663 struct omap_hwmod am33xx_timer5_hwmod = {
 664         .name           = "timer5",
 665         .class          = &am33xx_timer_hwmod_class,
 666         .clkdm_name     = "l4ls_clkdm",
 667         .main_clk       = "timer5_fck",
 668         .prcm           = {
 669                 .omap4  = {
 670                         .modulemode     = MODULEMODE_SWCTRL,
 671                 },
 672         },
 673 };
 674
 675 struct omap_hwmod am33xx_timer6_hwmod = {
 676         .name           = "timer6",
 677         .class          = &am33xx_timer_hwmod_class,
 678         .clkdm_name     = "l4ls_clkdm",
 679         .main_clk       = "timer6_fck",
 680         .prcm           = {
 681                 .omap4  = {
 682                         .modulemode     = MODULEMODE_SWCTRL,
 683                 },
 684         },
 685 };
 686
 687 struct omap_hwmod am33xx_timer7_hwmod = {
 688         .name           = "timer7",
 689         .class          = &am33xx_timer_hwmod_class,
 690         .clkdm_name     = "l4ls_clkdm",
 691         .main_clk       = "timer7_fck",
 692         .prcm           = {
 693                 .omap4  = {
 694                         .modulemode     = MODULEMODE_SWCTRL,
 695                 },
 696         },
 697 };
 698
 699 /* tpcc */
 700 static struct omap_hwmod_class am33xx_tpcc_hwmod_class = {
 701         .name           = "tpcc",
 702 };
 703
 704 struct omap_hwmod am33xx_tpcc_hwmod = {
 705         .name           = "tpcc",
 706         .class          = &am33xx_tpcc_hwmod_class,
 707         .clkdm_name     = "l3_clkdm",
 708         .main_clk       = "l3_gclk",
 709         .prcm           = {
 710                 .omap4  = {
 711                         .modulemode     = MODULEMODE_SWCTRL,
 712                 },
 713         },
 714 };
 715
 716 static struct omap_hwmod_class_sysconfig am33xx_tptc_sysc = {
 717         .rev_offs       = 0x0,
 718         .sysc_offs      = 0x10,
 719         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 720                           SYSC_HAS_MIDLEMODE),
 721         .idlemodes      = (SIDLE_FORCE | SIDLE_SMART | MSTANDBY_FORCE),
 722         .sysc_fields    = &omap_hwmod_sysc_type2,
 723 };
 724
 725 /* 'tptc' class */
 726 static struct omap_hwmod_class am33xx_tptc_hwmod_class = {
 727         .name           = "tptc",
 728         .sysc           = &am33xx_tptc_sysc,
 729 };
 730
 731 /* tptc0 */
 732 struct omap_hwmod am33xx_tptc0_hwmod = {
 733         .name           = "tptc0",
 734         .class          = &am33xx_tptc_hwmod_class,
 735         .clkdm_name     = "l3_clkdm",
 736         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
 737         .main_clk       = "l3_gclk",
 738         .prcm           = {
 739                 .omap4  = {
 740                         .modulemode     = MODULEMODE_SWCTRL,
 741                 },
 742         },
 743 };
 744
 745 /* tptc1 */
 746 struct omap_hwmod am33xx_tptc1_hwmod = {
 747         .name           = "tptc1",
 748         .class          = &am33xx_tptc_hwmod_class,
 749         .clkdm_name     = "l3_clkdm",
 750         .flags          = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
 751         .main_clk       = "l3_gclk",
 752         .prcm           = {
 753                 .omap4  = {
 754                         .modulemode     = MODULEMODE_SWCTRL,
 755                 },
 756         },
 757 };
 758
 759 /* tptc2 */
 760 struct omap_hwmod am33xx_tptc2_hwmod = {
 761         .name           = "tptc2",
 762         .class          = &am33xx_tptc_hwmod_class,
 763         .clkdm_name     = "l3_clkdm",
 764         .flags          = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
 765         .main_clk       = "l3_gclk",
 766         .prcm           = {
 767                 .omap4  = {
 768                         .modulemode     = MODULEMODE_SWCTRL,
 769                 },
 770         },
 771 };
 772
 773 static void omap_hwmod_am33xx_clkctrl(void)
 774 {
 775         CLKCTRL(am33xx_dcan0_hwmod, AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET);
 776         CLKCTRL(am33xx_dcan1_hwmod, AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET);
 777         CLKCTRL(am33xx_elm_hwmod, AM33XX_CM_PER_ELM_CLKCTRL_OFFSET);
 778         CLKCTRL(am33xx_epwmss0_hwmod, AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET);
 779         CLKCTRL(am33xx_epwmss1_hwmod, AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET);
 780         CLKCTRL(am33xx_epwmss2_hwmod, AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET);
 781         CLKCTRL(am33xx_spi0_hwmod, AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET);
 782         CLKCTRL(am33xx_spi1_hwmod, AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET);
 783         CLKCTRL(am33xx_spinlock_hwmod, AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET);
 784         CLKCTRL(am33xx_timer2_hwmod, AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET);
 785         CLKCTRL(am33xx_timer3_hwmod, AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET);
 786         CLKCTRL(am33xx_timer4_hwmod, AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET);
 787         CLKCTRL(am33xx_timer5_hwmod, AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET);
 788         CLKCTRL(am33xx_timer6_hwmod, AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET);
 789         CLKCTRL(am33xx_timer7_hwmod, AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET);
 790         CLKCTRL(am33xx_smartreflex0_hwmod,
 791                 AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET);
 792         CLKCTRL(am33xx_smartreflex1_hwmod,
 793                 AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET);
 794         CLKCTRL(am33xx_timer1_hwmod, AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET);
 795         CLKCTRL(am33xx_rtc_hwmod, AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET);
 796         PRCM_FLAGS(am33xx_rtc_hwmod, HWMOD_OMAP4_ZERO_CLKCTRL_OFFSET);
 797         CLKCTRL(am33xx_gpmc_hwmod, AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET);
 798         CLKCTRL(am33xx_l4_ls_hwmod, AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET);
 799         CLKCTRL(am33xx_l4_wkup_hwmod, AM33XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET);
 800         CLKCTRL(am33xx_l3_main_hwmod, AM33XX_CM_PER_L3_CLKCTRL_OFFSET);
 801         CLKCTRL(am33xx_tpcc_hwmod, AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET);
 802         CLKCTRL(am33xx_tptc0_hwmod, AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET);
 803         CLKCTRL(am33xx_tptc1_hwmod, AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET);
 804         CLKCTRL(am33xx_tptc2_hwmod, AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET);
 805         CLKCTRL(am33xx_gfx_hwmod, AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET);
 806         CLKCTRL(am33xx_pruss_hwmod, AM33XX_CM_PER_PRUSS_CLKCTRL_OFFSET);
 807         CLKCTRL(am33xx_mpu_hwmod , AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET);
 808         CLKCTRL(am33xx_l3_instr_hwmod , AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET);
 809         CLKCTRL(am33xx_ocmcram_hwmod , AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET);
 810         CLKCTRL(am33xx_sha0_hwmod , AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET);
 811         CLKCTRL(am33xx_aes0_hwmod , AM33XX_CM_PER_AES0_CLKCTRL_OFFSET);
 812 }
 813
 814 static void omap_hwmod_am33xx_rst(void)
 815 {
 816         RSTCTRL(am33xx_pruss_hwmod, AM33XX_RM_PER_RSTCTRL_OFFSET);
 817         RSTCTRL(am33xx_gfx_hwmod, AM33XX_RM_GFX_RSTCTRL_OFFSET);
 818         RSTST(am33xx_gfx_hwmod, AM33XX_RM_GFX_RSTST_OFFSET);
 819 }
 820
 821 void omap_hwmod_am33xx_reg(void)
 822 {
 823         omap_hwmod_am33xx_clkctrl();
 824         omap_hwmod_am33xx_rst();
 825 }
 826
 827 static void omap_hwmod_am43xx_clkctrl(void)
 828 {
 829         CLKCTRL(am33xx_dcan0_hwmod, AM43XX_CM_PER_DCAN0_CLKCTRL_OFFSET);
 830         CLKCTRL(am33xx_dcan1_hwmod, AM43XX_CM_PER_DCAN1_CLKCTRL_OFFSET);
 831         CLKCTRL(am33xx_elm_hwmod, AM43XX_CM_PER_ELM_CLKCTRL_OFFSET);
 832         CLKCTRL(am33xx_epwmss0_hwmod, AM43XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET);
 833         CLKCTRL(am33xx_epwmss1_hwmod, AM43XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET);
 834         CLKCTRL(am33xx_epwmss2_hwmod, AM43XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET);
 835         CLKCTRL(am33xx_spi0_hwmod, AM43XX_CM_PER_SPI0_CLKCTRL_OFFSET);
 836         CLKCTRL(am33xx_spi1_hwmod, AM43XX_CM_PER_SPI1_CLKCTRL_OFFSET);
 837         CLKCTRL(am33xx_spinlock_hwmod, AM43XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET);
 838         CLKCTRL(am33xx_timer2_hwmod, AM43XX_CM_PER_TIMER2_CLKCTRL_OFFSET);
 839         CLKCTRL(am33xx_timer3_hwmod, AM43XX_CM_PER_TIMER3_CLKCTRL_OFFSET);
 840         CLKCTRL(am33xx_timer4_hwmod, AM43XX_CM_PER_TIMER4_CLKCTRL_OFFSET);
 841         CLKCTRL(am33xx_timer5_hwmod, AM43XX_CM_PER_TIMER5_CLKCTRL_OFFSET);
 842         CLKCTRL(am33xx_timer6_hwmod, AM43XX_CM_PER_TIMER6_CLKCTRL_OFFSET);
 843         CLKCTRL(am33xx_timer7_hwmod, AM43XX_CM_PER_TIMER7_CLKCTRL_OFFSET);
 844         CLKCTRL(am33xx_smartreflex0_hwmod,
 845                 AM43XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET);
 846         CLKCTRL(am33xx_smartreflex1_hwmod,
 847                 AM43XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET);
 848         CLKCTRL(am33xx_timer1_hwmod, AM43XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET);
 849         CLKCTRL(am33xx_rtc_hwmod, AM43XX_CM_RTC_RTC_CLKCTRL_OFFSET);
 850         CLKCTRL(am33xx_gpmc_hwmod, AM43XX_CM_PER_GPMC_CLKCTRL_OFFSET);
 851         CLKCTRL(am33xx_l4_ls_hwmod, AM43XX_CM_PER_L4LS_CLKCTRL_OFFSET);
 852         CLKCTRL(am33xx_l4_wkup_hwmod, AM43XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET);
 853         CLKCTRL(am33xx_l3_main_hwmod, AM43XX_CM_PER_L3_CLKCTRL_OFFSET);
 854         CLKCTRL(am33xx_tpcc_hwmod, AM43XX_CM_PER_TPCC_CLKCTRL_OFFSET);
 855         CLKCTRL(am33xx_tptc0_hwmod, AM43XX_CM_PER_TPTC0_CLKCTRL_OFFSET);
 856         CLKCTRL(am33xx_tptc1_hwmod, AM43XX_CM_PER_TPTC1_CLKCTRL_OFFSET);
 857         CLKCTRL(am33xx_tptc2_hwmod, AM43XX_CM_PER_TPTC2_CLKCTRL_OFFSET);
 858         CLKCTRL(am33xx_gfx_hwmod, AM43XX_CM_GFX_GFX_CLKCTRL_OFFSET);
 859         CLKCTRL(am33xx_pruss_hwmod, AM43XX_CM_PER_PRUSS_CLKCTRL_OFFSET);
 860         CLKCTRL(am33xx_mpu_hwmod , AM43XX_CM_MPU_MPU_CLKCTRL_OFFSET);
 861         CLKCTRL(am33xx_l3_instr_hwmod , AM43XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET);
 862         CLKCTRL(am33xx_ocmcram_hwmod , AM43XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET);
 863         CLKCTRL(am33xx_sha0_hwmod , AM43XX_CM_PER_SHA0_CLKCTRL_OFFSET);
 864         CLKCTRL(am33xx_aes0_hwmod , AM43XX_CM_PER_AES0_CLKCTRL_OFFSET);
 865 }
 866
 867 static void omap_hwmod_am43xx_rst(void)
 868 {
 869         RSTCTRL(am33xx_pruss_hwmod, AM43XX_RM_PER_RSTCTRL_OFFSET);
 870         RSTCTRL(am33xx_gfx_hwmod, AM43XX_RM_GFX_RSTCTRL_OFFSET);
 871         RSTST(am33xx_pruss_hwmod, AM43XX_RM_PER_RSTST_OFFSET);
 872         RSTST(am33xx_gfx_hwmod, AM43XX_RM_GFX_RSTST_OFFSET);
 873 }
 874
 875 void omap_hwmod_am43xx_reg(void)
 876 {
 877         omap_hwmod_am43xx_clkctrl();
 878         omap_hwmod_am43xx_rst();
 879 }