arch/arm/mach-omap2/omap_hwmod_33xx_data.c

   1 /*
   2  * omap_hwmod_33xx_data.c: Hardware modules present on the AM33XX chips
   3  *
   4  * Copyright (C) {2012} Texas Instruments Incorporated - http://www.ti.com/
   5  *
   6  * This file is automatically generated from the AM33XX hardware databases.
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation version 2.
  10  *
  11  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  12  * kind, whether express or implied; without even the implied warranty
  13  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include "omap_hwmod.h"
  18 #include "omap_hwmod_common_data.h"
  19
  20 #include "control.h"
  21 #include "cm33xx.h"
  22 #include "prm33xx.h"
  23 #include "prm-regbits-33xx.h"
  24 #include "omap_hwmod_33xx_43xx_common_data.h"
  25
  26 /*
  27  * IP blocks
  28  */
  29
  30 /* emif */
  31 static struct omap_hwmod am33xx_emif_hwmod = {
  32         .name           = "emif",
  33         .class          = &am33xx_emif_hwmod_class,
  34         .clkdm_name     = "l3_clkdm",
  35         .flags          = HWMOD_INIT_NO_IDLE,
  36         .main_clk       = "dpll_ddr_m2_div2_ck",
  37         .prcm           = {
  38                 .omap4  = {
  39                         .clkctrl_offs   = AM33XX_CM_PER_EMIF_CLKCTRL_OFFSET,
  40                         .modulemode     = MODULEMODE_SWCTRL,
  41                 },
  42         },
  43 };
  44
  45 /* l4_hs */
  46 static struct omap_hwmod am33xx_l4_hs_hwmod = {
  47         .name           = "l4_hs",
  48         .class          = &am33xx_l4_hwmod_class,
  49         .clkdm_name     = "l4hs_clkdm",
  50         .flags          = HWMOD_INIT_NO_IDLE,
  51         .main_clk       = "l4hs_gclk",
  52         .prcm           = {
  53                 .omap4  = {
  54                         .clkctrl_offs   = AM33XX_CM_PER_L4HS_CLKCTRL_OFFSET,
  55                         .modulemode     = MODULEMODE_SWCTRL,
  56                 },
  57         },
  58 };
  59
  60 static struct omap_hwmod_rst_info am33xx_wkup_m3_resets[] = {
  61         { .name = "wkup_m3", .rst_shift = 3, .st_shift = 5 },
  62 };
  63
  64 /* wkup_m3  */
  65 static struct omap_hwmod am33xx_wkup_m3_hwmod = {
  66         .name           = "wkup_m3",
  67         .class          = &am33xx_wkup_m3_hwmod_class,
  68         .clkdm_name     = "l4_wkup_aon_clkdm",
  69         /* Keep hardreset asserted */
  70         .flags          = HWMOD_INIT_NO_RESET | HWMOD_NO_IDLEST,
  71         .main_clk       = "dpll_core_m4_div2_ck",
  72         .prcm           = {
  73                 .omap4  = {
  74                         .clkctrl_offs   = AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET,
  75                         .rstctrl_offs   = AM33XX_RM_WKUP_RSTCTRL_OFFSET,
  76                         .rstst_offs     = AM33XX_RM_WKUP_RSTST_OFFSET,
  77                         .modulemode     = MODULEMODE_SWCTRL,
  78                 },
  79         },
  80         .rst_lines      = am33xx_wkup_m3_resets,
  81         .rst_lines_cnt  = ARRAY_SIZE(am33xx_wkup_m3_resets),
  82 };
  83
  84 /*
  85  * 'adc/tsc' class
  86  * TouchScreen Controller (Anolog-To-Digital Converter)
  87  */
  88 static struct omap_hwmod_class_sysconfig am33xx_adc_tsc_sysc = {
  89         .rev_offs       = 0x00,
  90         .sysc_offs      = 0x10,
  91         .sysc_flags     = SYSC_HAS_SIDLEMODE,
  92         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
  93                         SIDLE_SMART_WKUP),
  94         .sysc_fields    = &omap_hwmod_sysc_type2,
  95 };
  96
  97 static struct omap_hwmod_class am33xx_adc_tsc_hwmod_class = {
  98         .name           = "adc_tsc",
  99         .sysc           = &am33xx_adc_tsc_sysc,
 100 };
 101
 102 static struct omap_hwmod am33xx_adc_tsc_hwmod = {
 103         .name           = "adc_tsc",
 104         .class          = &am33xx_adc_tsc_hwmod_class,
 105         .clkdm_name     = "l4_wkup_clkdm",
 106         .main_clk       = "adc_tsc_fck",
 107         .prcm           = {
 108                 .omap4  = {
 109                         .clkctrl_offs   = AM33XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET,
 110                         .modulemode     = MODULEMODE_SWCTRL,
 111                 },
 112         },
 113 };
 114
 115 /*
 116  * Modules omap_hwmod structures
 117  *
 118  * The following IPs are excluded for the moment because:
 119  * - They do not need an explicit SW control using omap_hwmod API.
 120  * - They still need to be validated with the driver
 121  *   properly adapted to omap_hwmod / omap_device
 122  *
 123  *    - cEFUSE (doesn't fall under any ocp_if)
 124  *    - clkdiv32k
 125  *    - ocp watch point
 126  */
 127 #if 0
 128 /*
 129  * 'cefuse' class
 130  */
 131 static struct omap_hwmod_class am33xx_cefuse_hwmod_class = {
 132         .name           = "cefuse",
 133 };
 134
 135 static struct omap_hwmod am33xx_cefuse_hwmod = {
 136         .name           = "cefuse",
 137         .class          = &am33xx_cefuse_hwmod_class,
 138         .clkdm_name     = "l4_cefuse_clkdm",
 139         .main_clk       = "cefuse_fck",
 140         .prcm           = {
 141                 .omap4  = {
 142                         .clkctrl_offs   = AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET,
 143                         .modulemode     = MODULEMODE_SWCTRL,
 144                 },
 145         },
 146 };
 147
 148 /*
 149  * 'clkdiv32k' class
 150  */
 151 static struct omap_hwmod_class am33xx_clkdiv32k_hwmod_class = {
 152         .name           = "clkdiv32k",
 153 };
 154
 155 static struct omap_hwmod am33xx_clkdiv32k_hwmod = {
 156         .name           = "clkdiv32k",
 157         .class          = &am33xx_clkdiv32k_hwmod_class,
 158         .clkdm_name     = "clk_24mhz_clkdm",
 159         .main_clk       = "clkdiv32k_ick",
 160         .prcm           = {
 161                 .omap4  = {
 162                         .clkctrl_offs   = AM33XX_CM_PER_CLKDIV32K_CLKCTRL_OFFSET,
 163                         .modulemode     = MODULEMODE_SWCTRL,
 164                 },
 165         },
 166 };
 167
 168 /* ocpwp */
 169 static struct omap_hwmod_class am33xx_ocpwp_hwmod_class = {
 170         .name           = "ocpwp",
 171 };
 172
 173 static struct omap_hwmod am33xx_ocpwp_hwmod = {
 174         .name           = "ocpwp",
 175         .class          = &am33xx_ocpwp_hwmod_class,
 176         .clkdm_name     = "l4ls_clkdm",
 177         .main_clk       = "l4ls_gclk",
 178         .prcm           = {
 179                 .omap4  = {
 180                         .clkctrl_offs   = AM33XX_CM_PER_OCPWP_CLKCTRL_OFFSET,
 181                         .modulemode     = MODULEMODE_SWCTRL,
 182                 },
 183         },
 184 };
 185 #endif
 186
 187 /*
 188  * 'debugss' class
 189  * debug sub system
 190  */
 191 static struct omap_hwmod_opt_clk debugss_opt_clks[] = {
 192         { .role = "dbg_sysclk", .clk = "dbg_sysclk_ck" },
 193         { .role = "dbg_clka", .clk = "dbg_clka_ck" },
 194 };
 195
 196 static struct omap_hwmod_class am33xx_debugss_hwmod_class = {
 197         .name           = "debugss",
 198 };
 199
 200 static struct omap_hwmod am33xx_debugss_hwmod = {
 201         .name           = "debugss",
 202         .class          = &am33xx_debugss_hwmod_class,
 203         .clkdm_name     = "l3_aon_clkdm",
 204         .main_clk       = "trace_clk_div_ck",
 205         .prcm           = {
 206                 .omap4  = {
 207                         .clkctrl_offs   = AM33XX_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET,
 208                         .modulemode     = MODULEMODE_SWCTRL,
 209                 },
 210         },
 211         .opt_clks       = debugss_opt_clks,
 212         .opt_clks_cnt   = ARRAY_SIZE(debugss_opt_clks),
 213 };
 214
 215 static struct omap_hwmod am33xx_control_hwmod = {
 216         .name           = "control",
 217         .class          = &am33xx_control_hwmod_class,
 218         .clkdm_name     = "l4_wkup_clkdm",
 219         .flags          = HWMOD_INIT_NO_IDLE,
 220         .main_clk       = "dpll_core_m4_div2_ck",
 221         .prcm           = {
 222                 .omap4  = {
 223                         .clkctrl_offs   = AM33XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET,
 224                         .modulemode     = MODULEMODE_SWCTRL,
 225                 },
 226         },
 227 };
 228
 229 /* lcdc */
 230 static struct omap_hwmod_class_sysconfig lcdc_sysc = {
 231         .rev_offs       = 0x0,
 232         .sysc_offs      = 0x54,
 233         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
 234         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 235         .sysc_fields    = &omap_hwmod_sysc_type2,
 236 };
 237
 238 static struct omap_hwmod_class am33xx_lcdc_hwmod_class = {
 239         .name           = "lcdc",
 240         .sysc           = &lcdc_sysc,
 241 };
 242
 243 static struct omap_hwmod am33xx_lcdc_hwmod = {
 244         .name           = "lcdc",
 245         .class          = &am33xx_lcdc_hwmod_class,
 246         .clkdm_name     = "lcdc_clkdm",
 247         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
 248         .main_clk       = "lcd_gclk",
 249         .prcm           = {
 250                 .omap4  = {
 251                         .clkctrl_offs   = AM33XX_CM_PER_LCDC_CLKCTRL_OFFSET,
 252                         .modulemode     = MODULEMODE_SWCTRL,
 253                 },
 254         },
 255 };
 256
 257 /*
 258  * 'usb_otg' class
 259  * high-speed on-the-go universal serial bus (usb_otg) controller
 260  */
 261 static struct omap_hwmod_class_sysconfig am33xx_usbhsotg_sysc = {
 262         .rev_offs       = 0x0,
 263         .sysc_offs      = 0x10,
 264         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
 265         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 266                           MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 267         .sysc_fields    = &omap_hwmod_sysc_type2,
 268 };
 269
 270 static struct omap_hwmod_class am33xx_usbotg_class = {
 271         .name           = "usbotg",
 272         .sysc           = &am33xx_usbhsotg_sysc,
 273 };
 274
 275 static struct omap_hwmod am33xx_usbss_hwmod = {
 276         .name           = "usb_otg_hs",
 277         .class          = &am33xx_usbotg_class,
 278         .clkdm_name     = "l3s_clkdm",
 279         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
 280         .main_clk       = "usbotg_fck",
 281         .prcm           = {
 282                 .omap4  = {
 283                         .clkctrl_offs   = AM33XX_CM_PER_USB0_CLKCTRL_OFFSET,
 284                         .modulemode     = MODULEMODE_SWCTRL,
 285                 },
 286         },
 287 };
 288
 289
 290 /*
 291  * Interfaces
 292  */
 293
 294 /* l3 main -> emif */
 295 static struct omap_hwmod_ocp_if am33xx_l3_main__emif = {
 296         .master         = &am33xx_l3_main_hwmod,
 297         .slave          = &am33xx_emif_hwmod,
 298         .clk            = "dpll_core_m4_ck",
 299         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 300 };
 301
 302 /* l3 main -> l4 hs */
 303 static struct omap_hwmod_ocp_if am33xx_l3_main__l4_hs = {
 304         .master         = &am33xx_l3_main_hwmod,
 305         .slave          = &am33xx_l4_hs_hwmod,
 306         .clk            = "l3s_gclk",
 307         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 308 };
 309
 310 /* wkup m3 -> l4 wkup */
 311 static struct omap_hwmod_ocp_if am33xx_wkup_m3__l4_wkup = {
 312         .master         = &am33xx_wkup_m3_hwmod,
 313         .slave          = &am33xx_l4_wkup_hwmod,
 314         .clk            = "dpll_core_m4_div2_ck",
 315         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 316 };
 317
 318 /* l4 wkup -> wkup m3 */
 319 static struct omap_hwmod_ocp_if am33xx_l4_wkup__wkup_m3 = {
 320         .master         = &am33xx_l4_wkup_hwmod,
 321         .slave          = &am33xx_wkup_m3_hwmod,
 322         .clk            = "dpll_core_m4_div2_ck",
 323         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 324 };
 325
 326 /* l4 hs -> pru-icss */
 327 static struct omap_hwmod_ocp_if am33xx_l4_hs__pruss = {
 328         .master         = &am33xx_l4_hs_hwmod,
 329         .slave          = &am33xx_pruss_hwmod,
 330         .clk            = "dpll_core_m4_ck",
 331         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 332 };
 333
 334 /* l3_main -> debugss */
 335 static struct omap_hwmod_ocp_if am33xx_l3_main__debugss = {
 336         .master         = &am33xx_l3_main_hwmod,
 337         .slave          = &am33xx_debugss_hwmod,
 338         .clk            = "dpll_core_m4_ck",
 339         .user           = OCP_USER_MPU,
 340 };
 341
 342 /* l4 wkup -> smartreflex0 */
 343 static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex0 = {
 344         .master         = &am33xx_l4_wkup_hwmod,
 345         .slave          = &am33xx_smartreflex0_hwmod,
 346         .clk            = "dpll_core_m4_div2_ck",
 347         .user           = OCP_USER_MPU,
 348 };
 349
 350 /* l4 wkup -> smartreflex1 */
 351 static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex1 = {
 352         .master         = &am33xx_l4_wkup_hwmod,
 353         .slave          = &am33xx_smartreflex1_hwmod,
 354         .clk            = "dpll_core_m4_div2_ck",
 355         .user           = OCP_USER_MPU,
 356 };
 357
 358 /* l4 wkup -> control */
 359 static struct omap_hwmod_ocp_if am33xx_l4_wkup__control = {
 360         .master         = &am33xx_l4_wkup_hwmod,
 361         .slave          = &am33xx_control_hwmod,
 362         .clk            = "dpll_core_m4_div2_ck",
 363         .user           = OCP_USER_MPU,
 364 };
 365
 366 /* L4 WKUP -> ADC_TSC */
 367 static struct omap_hwmod_ocp_if am33xx_l4_wkup__adc_tsc = {
 368         .master         = &am33xx_l4_wkup_hwmod,
 369         .slave          = &am33xx_adc_tsc_hwmod,
 370         .clk            = "dpll_core_m4_div2_ck",
 371         .user           = OCP_USER_MPU,
 372 };
 373
 374 static struct omap_hwmod_ocp_if am33xx_l3_main__lcdc = {
 375         .master         = &am33xx_l3_main_hwmod,
 376         .slave          = &am33xx_lcdc_hwmod,
 377         .clk            = "dpll_core_m4_ck",
 378         .user           = OCP_USER_MPU,
 379 };
 380
 381 /* l4 wkup -> timer1 */
 382 static struct omap_hwmod_ocp_if am33xx_l4_wkup__timer1 = {
 383         .master         = &am33xx_l4_wkup_hwmod,
 384         .slave          = &am33xx_timer1_hwmod,
 385         .clk            = "dpll_core_m4_div2_ck",
 386         .user           = OCP_USER_MPU,
 387 };
 388
 389 /* usbss */
 390 /* l3 s -> USBSS interface */
 391 static struct omap_hwmod_ocp_if am33xx_l3_s__usbss = {
 392         .master         = &am33xx_l3_s_hwmod,
 393         .slave          = &am33xx_usbss_hwmod,
 394         .clk            = "l3s_gclk",
 395         .user           = OCP_USER_MPU,
 396         .flags          = OCPIF_SWSUP_IDLE,
 397 };
 398
 399 static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
 400         &am33xx_l3_main__emif,
 401         &am33xx_mpu__l3_main,
 402         &am33xx_mpu__prcm,
 403         &am33xx_l3_s__l4_ls,
 404         &am33xx_l3_s__l4_wkup,
 405         &am33xx_l3_main__l4_hs,
 406         &am33xx_l3_main__l3_s,
 407         &am33xx_l3_main__l3_instr,
 408         &am33xx_l3_main__gfx,
 409         &am33xx_l3_s__l3_main,
 410         &am33xx_pruss__l3_main,
 411         &am33xx_wkup_m3__l4_wkup,
 412         &am33xx_gfx__l3_main,
 413         &am33xx_l3_main__debugss,
 414         &am33xx_l4_wkup__wkup_m3,
 415         &am33xx_l4_wkup__control,
 416         &am33xx_l4_wkup__smartreflex0,
 417         &am33xx_l4_wkup__smartreflex1,
 418         &am33xx_l4_wkup__timer1,
 419         &am33xx_l4_wkup__rtc,
 420         &am33xx_l4_wkup__adc_tsc,
 421         &am33xx_l4_hs__pruss,
 422         &am33xx_l4_per__dcan0,
 423         &am33xx_l4_per__dcan1,
 424         &am33xx_l4_ls__timer2,
 425         &am33xx_l4_ls__timer3,
 426         &am33xx_l4_ls__timer4,
 427         &am33xx_l4_ls__timer5,
 428         &am33xx_l4_ls__timer6,
 429         &am33xx_l4_ls__timer7,
 430         &am33xx_l3_main__tpcc,
 431         &am33xx_l4_ls__spinlock,
 432         &am33xx_l4_ls__elm,
 433         &am33xx_l4_ls__epwmss0,
 434         &am33xx_l4_ls__epwmss1,
 435         &am33xx_l4_ls__epwmss2,
 436         &am33xx_l3_s__gpmc,
 437         &am33xx_l3_main__lcdc,
 438         &am33xx_l4_ls__mcspi0,
 439         &am33xx_l4_ls__mcspi1,
 440         &am33xx_l3_main__tptc0,
 441         &am33xx_l3_main__tptc1,
 442         &am33xx_l3_main__tptc2,
 443         &am33xx_l3_main__ocmc,
 444         &am33xx_l3_s__usbss,
 445         &am33xx_l3_main__sha0,
 446         &am33xx_l3_main__aes0,
 447         NULL,
 448 };
 449
 450 int __init am33xx_hwmod_init(void)
 451 {
 452         omap_hwmod_am33xx_reg();
 453         omap_hwmod_init();
 454         return omap_hwmod_register_links(am33xx_hwmod_ocp_ifs);
 455 }