arch/arm/mach-omap2/omap_hwmod_43xx_data.c

   1 /*
   2  * Copyright (C) 2013 Texas Instruments Incorporated
   3  *
   4  * Hwmod present only in AM43x and those that differ other than register
   5  * offsets as compared to AM335x.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation version 2.
  10  *
  11  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  12  * kind, whether express or implied; without even the implied warranty
  13  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include "omap_hwmod.h"
  18 #include "omap_hwmod_33xx_43xx_common_data.h"
  19 #include "prcm43xx.h"
  20 #include "omap_hwmod_common_data.h"
  21
  22 /* IP blocks */
  23 static struct omap_hwmod am43xx_emif_hwmod = {
  24         .name           = "emif",
  25         .class          = &am33xx_emif_hwmod_class,
  26         .clkdm_name     = "emif_clkdm",
  27         .flags          = HWMOD_INIT_NO_IDLE,
  28         .main_clk       = "dpll_ddr_m2_ck",
  29         .prcm           = {
  30                 .omap4  = {
  31                         .clkctrl_offs   = AM43XX_CM_PER_EMIF_CLKCTRL_OFFSET,
  32                         .modulemode     = MODULEMODE_SWCTRL,
  33                 },
  34         },
  35 };
  36
  37 static struct omap_hwmod am43xx_l4_hs_hwmod = {
  38         .name           = "l4_hs",
  39         .class          = &am33xx_l4_hwmod_class,
  40         .clkdm_name     = "l3_clkdm",
  41         .flags          = HWMOD_INIT_NO_IDLE,
  42         .main_clk       = "l4hs_gclk",
  43         .prcm           = {
  44                 .omap4  = {
  45                         .clkctrl_offs   = AM43XX_CM_PER_L4HS_CLKCTRL_OFFSET,
  46                         .modulemode     = MODULEMODE_SWCTRL,
  47                 },
  48         },
  49 };
  50
  51 static struct omap_hwmod_rst_info am33xx_wkup_m3_resets[] = {
  52         { .name = "wkup_m3", .rst_shift = 3, .st_shift = 5 },
  53 };
  54
  55 static struct omap_hwmod am43xx_wkup_m3_hwmod = {
  56         .name           = "wkup_m3",
  57         .class          = &am33xx_wkup_m3_hwmod_class,
  58         .clkdm_name     = "l4_wkup_aon_clkdm",
  59         /* Keep hardreset asserted */
  60         .flags          = HWMOD_INIT_NO_RESET | HWMOD_NO_IDLEST,
  61         .main_clk       = "sys_clkin_ck",
  62         .prcm           = {
  63                 .omap4  = {
  64                         .clkctrl_offs   = AM43XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET,
  65                         .rstctrl_offs   = AM43XX_RM_WKUP_RSTCTRL_OFFSET,
  66                         .rstst_offs     = AM43XX_RM_WKUP_RSTST_OFFSET,
  67                         .modulemode     = MODULEMODE_SWCTRL,
  68                 },
  69         },
  70         .rst_lines      = am33xx_wkup_m3_resets,
  71         .rst_lines_cnt  = ARRAY_SIZE(am33xx_wkup_m3_resets),
  72 };
  73
  74 static struct omap_hwmod am43xx_control_hwmod = {
  75         .name           = "control",
  76         .class          = &am33xx_control_hwmod_class,
  77         .clkdm_name     = "l4_wkup_clkdm",
  78         .flags          = HWMOD_INIT_NO_IDLE,
  79         .main_clk       = "sys_clkin_ck",
  80         .prcm           = {
  81                 .omap4  = {
  82                         .clkctrl_offs   = AM43XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET,
  83                         .modulemode     = MODULEMODE_SWCTRL,
  84                 },
  85         },
  86 };
  87
  88 static struct omap_hwmod_class_sysconfig am43xx_synctimer_sysc = {
  89         .rev_offs       = 0x0,
  90         .sysc_offs      = 0x4,
  91         .sysc_flags     = SYSC_HAS_SIDLEMODE,
  92         .idlemodes      = (SIDLE_FORCE | SIDLE_NO),
  93         .sysc_fields    = &omap_hwmod_sysc_type1,
  94 };
  95
  96 static struct omap_hwmod_class am43xx_synctimer_hwmod_class = {
  97         .name   = "synctimer",
  98         .sysc   = &am43xx_synctimer_sysc,
  99 };
 100
 101 static struct omap_hwmod am43xx_synctimer_hwmod = {
 102         .name           = "counter_32k",
 103         .class          = &am43xx_synctimer_hwmod_class,
 104         .clkdm_name     = "l4_wkup_aon_clkdm",
 105         .flags          = HWMOD_SWSUP_SIDLE,
 106         .main_clk       = "synctimer_32kclk",
 107         .prcm = {
 108                 .omap4 = {
 109                         .clkctrl_offs = AM43XX_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
 110                         .modulemode   = MODULEMODE_SWCTRL,
 111                 },
 112         },
 113 };
 114
 115 static struct omap_hwmod am43xx_timer8_hwmod = {
 116         .name           = "timer8",
 117         .class          = &am33xx_timer_hwmod_class,
 118         .clkdm_name     = "l4ls_clkdm",
 119         .main_clk       = "timer8_fck",
 120         .prcm           = {
 121                 .omap4  = {
 122                         .clkctrl_offs   = AM43XX_CM_PER_TIMER8_CLKCTRL_OFFSET,
 123                         .modulemode     = MODULEMODE_SWCTRL,
 124                 },
 125         },
 126 };
 127
 128 static struct omap_hwmod am43xx_timer9_hwmod = {
 129         .name           = "timer9",
 130         .class          = &am33xx_timer_hwmod_class,
 131         .clkdm_name     = "l4ls_clkdm",
 132         .main_clk       = "timer9_fck",
 133         .prcm           = {
 134                 .omap4  = {
 135                         .clkctrl_offs   = AM43XX_CM_PER_TIMER9_CLKCTRL_OFFSET,
 136                         .modulemode     = MODULEMODE_SWCTRL,
 137                 },
 138         },
 139 };
 140
 141 static struct omap_hwmod am43xx_timer10_hwmod = {
 142         .name           = "timer10",
 143         .class          = &am33xx_timer_hwmod_class,
 144         .clkdm_name     = "l4ls_clkdm",
 145         .main_clk       = "timer10_fck",
 146         .prcm           = {
 147                 .omap4  = {
 148                         .clkctrl_offs   = AM43XX_CM_PER_TIMER10_CLKCTRL_OFFSET,
 149                         .modulemode     = MODULEMODE_SWCTRL,
 150                 },
 151         },
 152 };
 153
 154 static struct omap_hwmod am43xx_timer11_hwmod = {
 155         .name           = "timer11",
 156         .class          = &am33xx_timer_hwmod_class,
 157         .clkdm_name     = "l4ls_clkdm",
 158         .main_clk       = "timer11_fck",
 159         .prcm           = {
 160                 .omap4  = {
 161                         .clkctrl_offs   = AM43XX_CM_PER_TIMER11_CLKCTRL_OFFSET,
 162                         .modulemode     = MODULEMODE_SWCTRL,
 163                 },
 164         },
 165 };
 166
 167 static struct omap_hwmod am43xx_epwmss3_hwmod = {
 168         .name           = "epwmss3",
 169         .class          = &am33xx_epwmss_hwmod_class,
 170         .clkdm_name     = "l4ls_clkdm",
 171         .main_clk       = "l4ls_gclk",
 172         .prcm           = {
 173                 .omap4  = {
 174                         .clkctrl_offs = AM43XX_CM_PER_EPWMSS3_CLKCTRL_OFFSET,
 175                         .modulemode   = MODULEMODE_SWCTRL,
 176                 },
 177         },
 178 };
 179
 180 static struct omap_hwmod am43xx_epwmss4_hwmod = {
 181         .name           = "epwmss4",
 182         .class          = &am33xx_epwmss_hwmod_class,
 183         .clkdm_name     = "l4ls_clkdm",
 184         .main_clk       = "l4ls_gclk",
 185         .prcm           = {
 186                 .omap4  = {
 187                         .clkctrl_offs = AM43XX_CM_PER_EPWMSS4_CLKCTRL_OFFSET,
 188                         .modulemode   = MODULEMODE_SWCTRL,
 189                 },
 190         },
 191 };
 192
 193 static struct omap_hwmod am43xx_epwmss5_hwmod = {
 194         .name           = "epwmss5",
 195         .class          = &am33xx_epwmss_hwmod_class,
 196         .clkdm_name     = "l4ls_clkdm",
 197         .main_clk       = "l4ls_gclk",
 198         .prcm           = {
 199                 .omap4  = {
 200                         .clkctrl_offs = AM43XX_CM_PER_EPWMSS5_CLKCTRL_OFFSET,
 201                         .modulemode   = MODULEMODE_SWCTRL,
 202                 },
 203         },
 204 };
 205
 206 static struct omap_hwmod am43xx_spi2_hwmod = {
 207         .name           = "spi2",
 208         .class          = &am33xx_spi_hwmod_class,
 209         .clkdm_name     = "l4ls_clkdm",
 210         .main_clk       = "dpll_per_m2_div4_ck",
 211         .prcm           = {
 212                 .omap4  = {
 213                         .clkctrl_offs = AM43XX_CM_PER_SPI2_CLKCTRL_OFFSET,
 214                         .modulemode   = MODULEMODE_SWCTRL,
 215                 },
 216         },
 217 };
 218
 219 static struct omap_hwmod am43xx_spi3_hwmod = {
 220         .name           = "spi3",
 221         .class          = &am33xx_spi_hwmod_class,
 222         .clkdm_name     = "l4ls_clkdm",
 223         .main_clk       = "dpll_per_m2_div4_ck",
 224         .prcm           = {
 225                 .omap4  = {
 226                         .clkctrl_offs = AM43XX_CM_PER_SPI3_CLKCTRL_OFFSET,
 227                         .modulemode   = MODULEMODE_SWCTRL,
 228                 },
 229         },
 230 };
 231
 232 static struct omap_hwmod am43xx_spi4_hwmod = {
 233         .name           = "spi4",
 234         .class          = &am33xx_spi_hwmod_class,
 235         .clkdm_name     = "l4ls_clkdm",
 236         .main_clk       = "dpll_per_m2_div4_ck",
 237         .prcm           = {
 238                 .omap4  = {
 239                         .clkctrl_offs = AM43XX_CM_PER_SPI4_CLKCTRL_OFFSET,
 240                         .modulemode   = MODULEMODE_SWCTRL,
 241                 },
 242         },
 243 };
 244
 245 static struct omap_hwmod_class am43xx_ocp2scp_hwmod_class = {
 246         .name   = "ocp2scp",
 247 };
 248
 249 static struct omap_hwmod am43xx_ocp2scp0_hwmod = {
 250         .name           = "ocp2scp0",
 251         .class          = &am43xx_ocp2scp_hwmod_class,
 252         .clkdm_name     = "l4ls_clkdm",
 253         .main_clk       = "l4ls_gclk",
 254         .prcm = {
 255                 .omap4 = {
 256                         .clkctrl_offs = AM43XX_CM_PER_USBPHYOCP2SCP0_CLKCTRL_OFFSET,
 257                         .modulemode   = MODULEMODE_SWCTRL,
 258                 },
 259         },
 260 };
 261
 262 static struct omap_hwmod am43xx_ocp2scp1_hwmod = {
 263         .name           = "ocp2scp1",
 264         .class          = &am43xx_ocp2scp_hwmod_class,
 265         .clkdm_name     = "l4ls_clkdm",
 266         .main_clk       = "l4ls_gclk",
 267         .prcm = {
 268                 .omap4 = {
 269                         .clkctrl_offs   = AM43XX_CM_PER_USBPHYOCP2SCP1_CLKCTRL_OFFSET,
 270                         .modulemode     = MODULEMODE_SWCTRL,
 271                 },
 272         },
 273 };
 274
 275 static struct omap_hwmod_class_sysconfig am43xx_usb_otg_ss_sysc = {
 276         .rev_offs       = 0x0000,
 277         .sysc_offs      = 0x0010,
 278         .sysc_flags     = (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE |
 279                                 SYSC_HAS_SIDLEMODE),
 280         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 281                                 SIDLE_SMART_WKUP | MSTANDBY_FORCE |
 282                                 MSTANDBY_NO | MSTANDBY_SMART |
 283                                 MSTANDBY_SMART_WKUP),
 284         .sysc_fields    = &omap_hwmod_sysc_type2,
 285 };
 286
 287 static struct omap_hwmod_class am43xx_usb_otg_ss_hwmod_class = {
 288         .name   = "usb_otg_ss",
 289         .sysc   = &am43xx_usb_otg_ss_sysc,
 290 };
 291
 292 static struct omap_hwmod am43xx_usb_otg_ss0_hwmod = {
 293         .name           = "usb_otg_ss0",
 294         .class          = &am43xx_usb_otg_ss_hwmod_class,
 295         .clkdm_name     = "l3s_clkdm",
 296         .main_clk       = "l3s_gclk",
 297         .prcm = {
 298                 .omap4 = {
 299                         .clkctrl_offs   = AM43XX_CM_PER_USB_OTG_SS0_CLKCTRL_OFFSET,
 300                         .modulemode     = MODULEMODE_SWCTRL,
 301                 },
 302         },
 303 };
 304
 305 static struct omap_hwmod am43xx_usb_otg_ss1_hwmod = {
 306         .name           = "usb_otg_ss1",
 307         .class          = &am43xx_usb_otg_ss_hwmod_class,
 308         .clkdm_name     = "l3s_clkdm",
 309         .main_clk       = "l3s_gclk",
 310         .prcm = {
 311                 .omap4 = {
 312                         .clkctrl_offs   = AM43XX_CM_PER_USB_OTG_SS1_CLKCTRL_OFFSET,
 313                         .modulemode     = MODULEMODE_SWCTRL,
 314                 },
 315         },
 316 };
 317
 318 static struct omap_hwmod_class_sysconfig am43xx_qspi_sysc = {
 319         .rev_offs       = 0,
 320         .sysc_offs      = 0x0010,
 321         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 322         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 323                                 SIDLE_SMART_WKUP),
 324         .sysc_fields    = &omap_hwmod_sysc_type2,
 325 };
 326
 327 static struct omap_hwmod_class am43xx_qspi_hwmod_class = {
 328         .name   = "qspi",
 329         .sysc   = &am43xx_qspi_sysc,
 330 };
 331
 332 static struct omap_hwmod am43xx_qspi_hwmod = {
 333         .name           = "qspi",
 334         .class          = &am43xx_qspi_hwmod_class,
 335         .clkdm_name     = "l3s_clkdm",
 336         .main_clk       = "l3s_gclk",
 337         .prcm = {
 338                 .omap4 = {
 339                         .clkctrl_offs = AM43XX_CM_PER_QSPI_CLKCTRL_OFFSET,
 340                         .modulemode   = MODULEMODE_SWCTRL,
 341                 },
 342         },
 343 };
 344
 345 /*
 346  * 'adc/tsc' class
 347  * TouchScreen Controller (Analog-To-Digital Converter)
 348  */
 349 static struct omap_hwmod_class_sysconfig am43xx_adc_tsc_sysc = {
 350         .rev_offs       = 0x00,
 351         .sysc_offs      = 0x10,
 352         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 353         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 354                           SIDLE_SMART_WKUP),
 355         .sysc_fields    = &omap_hwmod_sysc_type2,
 356 };
 357
 358 static struct omap_hwmod_class am43xx_adc_tsc_hwmod_class = {
 359         .name           = "adc_tsc",
 360         .sysc           = &am43xx_adc_tsc_sysc,
 361 };
 362
 363 static struct omap_hwmod am43xx_adc_tsc_hwmod = {
 364         .name           = "adc_tsc",
 365         .class          = &am43xx_adc_tsc_hwmod_class,
 366         .clkdm_name     = "l3s_tsc_clkdm",
 367         .main_clk       = "adc_tsc_fck",
 368         .prcm           = {
 369                 .omap4  = {
 370                         .clkctrl_offs   = AM43XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET,
 371                         .modulemode     = MODULEMODE_SWCTRL,
 372                 },
 373         },
 374 };
 375
 376 static struct omap_hwmod_class_sysconfig am43xx_des_sysc = {
 377         .rev_offs       = 0x30,
 378         .sysc_offs      = 0x34,
 379         .syss_offs      = 0x38,
 380         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 381 };
 382
 383 static struct omap_hwmod_class am43xx_des_hwmod_class = {
 384         .name           = "des",
 385         .sysc           = &am43xx_des_sysc,
 386 };
 387
 388 static struct omap_hwmod am43xx_des_hwmod = {
 389         .name           = "des",
 390         .class          = &am43xx_des_hwmod_class,
 391         .clkdm_name     = "l3_clkdm",
 392         .main_clk       = "l3_gclk",
 393         .prcm           = {
 394                 .omap4  = {
 395                         .clkctrl_offs   = AM43XX_CM_PER_DES_CLKCTRL_OFFSET,
 396                         .modulemode     = MODULEMODE_SWCTRL,
 397                 },
 398         },
 399 };
 400
 401 /* dss */
 402
 403 static struct omap_hwmod am43xx_dss_core_hwmod = {
 404         .name           = "dss_core",
 405         .class          = &omap2_dss_hwmod_class,
 406         .clkdm_name     = "dss_clkdm",
 407         .main_clk       = "disp_clk",
 408         .prcm = {
 409                 .omap4 = {
 410                         .clkctrl_offs = AM43XX_CM_PER_DSS_CLKCTRL_OFFSET,
 411                         .modulemode   = MODULEMODE_SWCTRL,
 412                 },
 413         },
 414 };
 415
 416 /* dispc */
 417
 418 static struct omap_dss_dispc_dev_attr am43xx_dss_dispc_dev_attr = {
 419         .manager_count          = 1,
 420         .has_framedonetv_irq    = 0
 421 };
 422
 423 static struct omap_hwmod_class_sysconfig am43xx_dispc_sysc = {
 424         .rev_offs       = 0x0000,
 425         .sysc_offs      = 0x0010,
 426         .syss_offs      = 0x0014,
 427         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
 428                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 429                            SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_MIDLEMODE),
 430         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 431                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 432         .sysc_fields    = &omap_hwmod_sysc_type1,
 433 };
 434
 435 static struct omap_hwmod_class am43xx_dispc_hwmod_class = {
 436         .name   = "dispc",
 437         .sysc   = &am43xx_dispc_sysc,
 438 };
 439
 440 static struct omap_hwmod am43xx_dss_dispc_hwmod = {
 441         .name           = "dss_dispc",
 442         .class          = &am43xx_dispc_hwmod_class,
 443         .clkdm_name     = "dss_clkdm",
 444         .main_clk       = "disp_clk",
 445         .prcm = {
 446                 .omap4 = {
 447                         .clkctrl_offs = AM43XX_CM_PER_DSS_CLKCTRL_OFFSET,
 448                 },
 449         },
 450         .dev_attr       = &am43xx_dss_dispc_dev_attr,
 451         .parent_hwmod   = &am43xx_dss_core_hwmod,
 452 };
 453
 454 /* rfbi */
 455
 456 static struct omap_hwmod am43xx_dss_rfbi_hwmod = {
 457         .name           = "dss_rfbi",
 458         .class          = &omap2_rfbi_hwmod_class,
 459         .clkdm_name     = "dss_clkdm",
 460         .main_clk       = "disp_clk",
 461         .prcm = {
 462                 .omap4 = {
 463                         .clkctrl_offs = AM43XX_CM_PER_DSS_CLKCTRL_OFFSET,
 464                 },
 465         },
 466         .parent_hwmod   = &am43xx_dss_core_hwmod,
 467 };
 468
 469
 470 static struct omap_hwmod_class_sysconfig am43xx_vpfe_sysc = {
 471         .rev_offs       = 0x0,
 472         .sysc_offs      = 0x104,
 473         .sysc_flags     = SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE,
 474         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 475                                 MSTANDBY_FORCE | MSTANDBY_SMART | MSTANDBY_NO),
 476         .sysc_fields    = &omap_hwmod_sysc_type2,
 477 };
 478
 479 static struct omap_hwmod_class am43xx_vpfe_hwmod_class = {
 480         .name           = "vpfe",
 481         .sysc           = &am43xx_vpfe_sysc,
 482 };
 483
 484 static struct omap_hwmod am43xx_vpfe0_hwmod = {
 485         .name           = "vpfe0",
 486         .class          = &am43xx_vpfe_hwmod_class,
 487         .clkdm_name     = "l3s_clkdm",
 488         .prcm           = {
 489                 .omap4  = {
 490                         .modulemode     = MODULEMODE_SWCTRL,
 491                         .clkctrl_offs   = AM43XX_CM_PER_VPFE0_CLKCTRL_OFFSET,
 492                 },
 493         },
 494 };
 495
 496 static struct omap_hwmod am43xx_vpfe1_hwmod = {
 497         .name           = "vpfe1",
 498         .class          = &am43xx_vpfe_hwmod_class,
 499         .clkdm_name     = "l3s_clkdm",
 500         .prcm           = {
 501                 .omap4  = {
 502                         .modulemode     = MODULEMODE_SWCTRL,
 503                         .clkctrl_offs   = AM43XX_CM_PER_VPFE1_CLKCTRL_OFFSET,
 504                 },
 505         },
 506 };
 507
 508 /* Interfaces */
 509 static struct omap_hwmod_ocp_if am43xx_l3_main__emif = {
 510         .master         = &am33xx_l3_main_hwmod,
 511         .slave          = &am43xx_emif_hwmod,
 512         .clk            = "dpll_core_m4_ck",
 513         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 514 };
 515
 516 static struct omap_hwmod_ocp_if am43xx_l3_main__l4_hs = {
 517         .master         = &am33xx_l3_main_hwmod,
 518         .slave          = &am43xx_l4_hs_hwmod,
 519         .clk            = "l3s_gclk",
 520         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 521 };
 522
 523 static struct omap_hwmod_ocp_if am43xx_wkup_m3__l4_wkup = {
 524         .master         = &am43xx_wkup_m3_hwmod,
 525         .slave          = &am33xx_l4_wkup_hwmod,
 526         .clk            = "sys_clkin_ck",
 527         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 528 };
 529
 530 static struct omap_hwmod_ocp_if am43xx_l4_wkup__wkup_m3 = {
 531         .master         = &am33xx_l4_wkup_hwmod,
 532         .slave          = &am43xx_wkup_m3_hwmod,
 533         .clk            = "sys_clkin_ck",
 534         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 535 };
 536
 537 static struct omap_hwmod_ocp_if am43xx_l3_main__pruss = {
 538         .master         = &am33xx_l3_main_hwmod,
 539         .slave          = &am33xx_pruss_hwmod,
 540         .clk            = "dpll_core_m4_ck",
 541         .user           = OCP_USER_MPU,
 542 };
 543
 544 static struct omap_hwmod_ocp_if am43xx_l4_wkup__smartreflex0 = {
 545         .master         = &am33xx_l4_wkup_hwmod,
 546         .slave          = &am33xx_smartreflex0_hwmod,
 547         .clk            = "sys_clkin_ck",
 548         .user           = OCP_USER_MPU,
 549 };
 550
 551 static struct omap_hwmod_ocp_if am43xx_l4_wkup__smartreflex1 = {
 552         .master         = &am33xx_l4_wkup_hwmod,
 553         .slave          = &am33xx_smartreflex1_hwmod,
 554         .clk            = "sys_clkin_ck",
 555         .user           = OCP_USER_MPU,
 556 };
 557
 558 static struct omap_hwmod_ocp_if am43xx_l4_wkup__control = {
 559         .master         = &am33xx_l4_wkup_hwmod,
 560         .slave          = &am43xx_control_hwmod,
 561         .clk            = "sys_clkin_ck",
 562         .user           = OCP_USER_MPU,
 563 };
 564
 565 static struct omap_hwmod_ocp_if am43xx_l4_wkup__adc_tsc = {
 566         .master         = &am33xx_l4_wkup_hwmod,
 567         .slave          = &am43xx_adc_tsc_hwmod,
 568         .clk            = "dpll_core_m4_div2_ck",
 569         .user           = OCP_USER_MPU,
 570 };
 571
 572 static struct omap_hwmod_ocp_if am43xx_l4_wkup__timer1 = {
 573         .master         = &am33xx_l4_wkup_hwmod,
 574         .slave          = &am33xx_timer1_hwmod,
 575         .clk            = "sys_clkin_ck",
 576         .user           = OCP_USER_MPU,
 577 };
 578
 579 static struct omap_hwmod_ocp_if am33xx_l4_wkup__synctimer = {
 580         .master         = &am33xx_l4_wkup_hwmod,
 581         .slave          = &am43xx_synctimer_hwmod,
 582         .clk            = "sys_clkin_ck",
 583         .user           = OCP_USER_MPU,
 584 };
 585
 586 static struct omap_hwmod_ocp_if am43xx_l4_ls__timer8 = {
 587         .master         = &am33xx_l4_ls_hwmod,
 588         .slave          = &am43xx_timer8_hwmod,
 589         .clk            = "l4ls_gclk",
 590         .user           = OCP_USER_MPU,
 591 };
 592
 593 static struct omap_hwmod_ocp_if am43xx_l4_ls__timer9 = {
 594         .master         = &am33xx_l4_ls_hwmod,
 595         .slave          = &am43xx_timer9_hwmod,
 596         .clk            = "l4ls_gclk",
 597         .user           = OCP_USER_MPU,
 598 };
 599
 600 static struct omap_hwmod_ocp_if am43xx_l4_ls__timer10 = {
 601         .master         = &am33xx_l4_ls_hwmod,
 602         .slave          = &am43xx_timer10_hwmod,
 603         .clk            = "l4ls_gclk",
 604         .user           = OCP_USER_MPU,
 605 };
 606
 607 static struct omap_hwmod_ocp_if am43xx_l4_ls__timer11 = {
 608         .master         = &am33xx_l4_ls_hwmod,
 609         .slave          = &am43xx_timer11_hwmod,
 610         .clk            = "l4ls_gclk",
 611         .user           = OCP_USER_MPU,
 612 };
 613
 614 static struct omap_hwmod_ocp_if am43xx_l4_ls__epwmss3 = {
 615         .master         = &am33xx_l4_ls_hwmod,
 616         .slave          = &am43xx_epwmss3_hwmod,
 617         .clk            = "l4ls_gclk",
 618         .user           = OCP_USER_MPU,
 619 };
 620
 621 static struct omap_hwmod_ocp_if am43xx_l4_ls__epwmss4 = {
 622         .master         = &am33xx_l4_ls_hwmod,
 623         .slave          = &am43xx_epwmss4_hwmod,
 624         .clk            = "l4ls_gclk",
 625         .user           = OCP_USER_MPU,
 626 };
 627
 628 static struct omap_hwmod_ocp_if am43xx_l4_ls__epwmss5 = {
 629         .master         = &am33xx_l4_ls_hwmod,
 630         .slave          = &am43xx_epwmss5_hwmod,
 631         .clk            = "l4ls_gclk",
 632         .user           = OCP_USER_MPU,
 633 };
 634
 635 static struct omap_hwmod_ocp_if am43xx_l4_ls__mcspi2 = {
 636         .master         = &am33xx_l4_ls_hwmod,
 637         .slave          = &am43xx_spi2_hwmod,
 638         .clk            = "l4ls_gclk",
 639         .user           = OCP_USER_MPU,
 640 };
 641
 642 static struct omap_hwmod_ocp_if am43xx_l4_ls__mcspi3 = {
 643         .master         = &am33xx_l4_ls_hwmod,
 644         .slave          = &am43xx_spi3_hwmod,
 645         .clk            = "l4ls_gclk",
 646         .user           = OCP_USER_MPU,
 647 };
 648
 649 static struct omap_hwmod_ocp_if am43xx_l4_ls__mcspi4 = {
 650         .master         = &am33xx_l4_ls_hwmod,
 651         .slave          = &am43xx_spi4_hwmod,
 652         .clk            = "l4ls_gclk",
 653         .user           = OCP_USER_MPU,
 654 };
 655
 656 static struct omap_hwmod_ocp_if am43xx_l4_ls__ocp2scp0 = {
 657         .master         = &am33xx_l4_ls_hwmod,
 658         .slave          = &am43xx_ocp2scp0_hwmod,
 659         .clk            = "l4ls_gclk",
 660         .user           = OCP_USER_MPU,
 661 };
 662
 663 static struct omap_hwmod_ocp_if am43xx_l4_ls__ocp2scp1 = {
 664         .master         = &am33xx_l4_ls_hwmod,
 665         .slave          = &am43xx_ocp2scp1_hwmod,
 666         .clk            = "l4ls_gclk",
 667         .user           = OCP_USER_MPU,
 668 };
 669
 670 static struct omap_hwmod_ocp_if am43xx_l3_s__usbotgss0 = {
 671         .master         = &am33xx_l3_s_hwmod,
 672         .slave          = &am43xx_usb_otg_ss0_hwmod,
 673         .clk            = "l3s_gclk",
 674         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 675 };
 676
 677 static struct omap_hwmod_ocp_if am43xx_l3_s__usbotgss1 = {
 678         .master         = &am33xx_l3_s_hwmod,
 679         .slave          = &am43xx_usb_otg_ss1_hwmod,
 680         .clk            = "l3s_gclk",
 681         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 682 };
 683
 684 static struct omap_hwmod_ocp_if am43xx_l3_s__qspi = {
 685         .master         = &am33xx_l3_s_hwmod,
 686         .slave          = &am43xx_qspi_hwmod,
 687         .clk            = "l3s_gclk",
 688         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 689 };
 690
 691 static struct omap_hwmod_ocp_if am43xx_dss__l3_main = {
 692         .master         = &am43xx_dss_core_hwmod,
 693         .slave          = &am33xx_l3_main_hwmod,
 694         .clk            = "l3_gclk",
 695         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 696 };
 697
 698 static struct omap_hwmod_ocp_if am43xx_l4_ls__dss = {
 699         .master         = &am33xx_l4_ls_hwmod,
 700         .slave          = &am43xx_dss_core_hwmod,
 701         .clk            = "l4ls_gclk",
 702         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 703 };
 704
 705 static struct omap_hwmod_ocp_if am43xx_l4_ls__dss_dispc = {
 706         .master         = &am33xx_l4_ls_hwmod,
 707         .slave          = &am43xx_dss_dispc_hwmod,
 708         .clk            = "l4ls_gclk",
 709         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 710 };
 711
 712 static struct omap_hwmod_ocp_if am43xx_l4_ls__dss_rfbi = {
 713         .master         = &am33xx_l4_ls_hwmod,
 714         .slave          = &am43xx_dss_rfbi_hwmod,
 715         .clk            = "l4ls_gclk",
 716         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 717 };
 718
 719 static struct omap_hwmod_ocp_if am43xx_l3__vpfe0 = {
 720         .master         = &am43xx_vpfe0_hwmod,
 721         .slave          = &am33xx_l3_main_hwmod,
 722         .clk            = "l3_gclk",
 723         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 724 };
 725
 726 static struct omap_hwmod_ocp_if am43xx_l3__vpfe1 = {
 727         .master         = &am43xx_vpfe1_hwmod,
 728         .slave          = &am33xx_l3_main_hwmod,
 729         .clk            = "l3_gclk",
 730         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 731 };
 732
 733 static struct omap_hwmod_ocp_if am43xx_l4_ls__vpfe0 = {
 734         .master         = &am33xx_l4_ls_hwmod,
 735         .slave          = &am43xx_vpfe0_hwmod,
 736         .clk            = "l4ls_gclk",
 737         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 738 };
 739
 740 static struct omap_hwmod_ocp_if am43xx_l4_ls__vpfe1 = {
 741         .master         = &am33xx_l4_ls_hwmod,
 742         .slave          = &am43xx_vpfe1_hwmod,
 743         .clk            = "l4ls_gclk",
 744         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 745 };
 746
 747 static struct omap_hwmod_ocp_if am43xx_l3_main__des = {
 748         .master         = &am33xx_l3_main_hwmod,
 749         .slave          = &am43xx_des_hwmod,
 750         .clk            = "l3_gclk",
 751         .user           = OCP_USER_MPU,
 752 };
 753
 754 static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = {
 755         &am33xx_l4_wkup__synctimer,
 756         &am43xx_l4_ls__timer8,
 757         &am43xx_l4_ls__timer9,
 758         &am43xx_l4_ls__timer10,
 759         &am43xx_l4_ls__timer11,
 760         &am43xx_l4_ls__epwmss3,
 761         &am43xx_l4_ls__epwmss4,
 762         &am43xx_l4_ls__epwmss5,
 763         &am43xx_l4_ls__mcspi2,
 764         &am43xx_l4_ls__mcspi3,
 765         &am43xx_l4_ls__mcspi4,
 766         &am43xx_l3_main__pruss,
 767         &am33xx_mpu__l3_main,
 768         &am33xx_mpu__prcm,
 769         &am33xx_l3_s__l4_ls,
 770         &am33xx_l3_s__l4_wkup,
 771         &am43xx_l3_main__l4_hs,
 772         &am33xx_l3_main__l3_s,
 773         &am33xx_l3_main__l3_instr,
 774         &am33xx_l3_main__gfx,
 775         &am33xx_l3_s__l3_main,
 776         &am43xx_l3_main__emif,
 777         &am33xx_pruss__l3_main,
 778         &am43xx_wkup_m3__l4_wkup,
 779         &am33xx_gfx__l3_main,
 780         &am43xx_l4_wkup__wkup_m3,
 781         &am43xx_l4_wkup__control,
 782         &am43xx_l4_wkup__smartreflex0,
 783         &am43xx_l4_wkup__smartreflex1,
 784         &am43xx_l4_wkup__timer1,
 785         &am43xx_l4_wkup__adc_tsc,
 786         &am43xx_l3_s__qspi,
 787         &am33xx_l4_per__dcan0,
 788         &am33xx_l4_per__dcan1,
 789         &am33xx_l4_ls__timer2,
 790         &am33xx_l4_ls__timer3,
 791         &am33xx_l4_ls__timer4,
 792         &am33xx_l4_ls__timer5,
 793         &am33xx_l4_ls__timer6,
 794         &am33xx_l4_ls__timer7,
 795         &am33xx_l3_main__tpcc,
 796         &am33xx_l4_ls__spinlock,
 797         &am33xx_l4_ls__elm,
 798         &am33xx_l4_ls__epwmss0,
 799         &am33xx_l4_ls__epwmss1,
 800         &am33xx_l4_ls__epwmss2,
 801         &am33xx_l3_s__gpmc,
 802         &am33xx_l4_ls__mcspi0,
 803         &am33xx_l4_ls__mcspi1,
 804         &am33xx_l3_main__tptc0,
 805         &am33xx_l3_main__tptc1,
 806         &am33xx_l3_main__tptc2,
 807         &am33xx_l3_main__ocmc,
 808         &am33xx_l3_main__sha0,
 809         &am33xx_l3_main__aes0,
 810         &am43xx_l3_main__des,
 811         &am43xx_l4_ls__ocp2scp0,
 812         &am43xx_l4_ls__ocp2scp1,
 813         &am43xx_l3_s__usbotgss0,
 814         &am43xx_l3_s__usbotgss1,
 815         &am43xx_dss__l3_main,
 816         &am43xx_l4_ls__dss,
 817         &am43xx_l4_ls__dss_dispc,
 818         &am43xx_l4_ls__dss_rfbi,
 819         &am43xx_l3__vpfe0,
 820         &am43xx_l3__vpfe1,
 821         &am43xx_l4_ls__vpfe0,
 822         &am43xx_l4_ls__vpfe1,
 823         NULL,
 824 };
 825
 826 static struct omap_hwmod_ocp_if *am43xx_rtc_hwmod_ocp_ifs[] __initdata = {
 827         &am33xx_l4_wkup__rtc,
 828         NULL,
 829 };
 830
 831 int __init am43xx_hwmod_init(void)
 832 {
 833         int ret;
 834
 835         omap_hwmod_am43xx_reg();
 836         omap_hwmod_init();
 837         ret = omap_hwmod_register_links(am43xx_hwmod_ocp_ifs);
 838
 839         if (!ret && of_machine_is_compatible("ti,am4372"))
 840                 ret = omap_hwmod_register_links(am43xx_rtc_hwmod_ocp_ifs);
 841
 842         return ret;
 843 }