arch/arm/mach-omap2/omap_hwmod_44xx_data.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Hardware modules present on the OMAP44xx chips
   4  *
   5  * Copyright (C) 2009-2012 Texas Instruments, Inc.
   6  * Copyright (C) 2009-2010 Nokia Corporation
   7  *
   8  * Paul Walmsley
   9  * Benoit Cousson
  10  *
  11  * This file is automatically generated from the OMAP hardware databases.
  12  * We respectfully ask that any modifications to this file be coordinated
  13  * with the public linux-omap@vger.kernel.org mailing list and the
  14  * authors above to ensure that the autogeneration scripts are kept
  15  * up-to-date with the file contents.
  16  * Note that this file is currently not in sync with autogeneration scripts.
  17  * The above note to be removed, once it is synced up.
  18  */
  19
  20 #include <linux/io.h>
  21 #include <linux/power/smartreflex.h>
  22
  23 #include <linux/omap-dma.h>
  24
  25 #include "omap_hwmod.h"
  26 #include "omap_hwmod_common_data.h"
  27 #include "cm1_44xx.h"
  28 #include "cm2_44xx.h"
  29 #include "prm44xx.h"
  30 #include "prm-regbits-44xx.h"
  31
  32 /* Base offset for all OMAP4 interrupts external to MPUSS */
  33 #define OMAP44XX_IRQ_GIC_START  32
  34
  35 /* Base offset for all OMAP4 dma requests */
  36 #define OMAP44XX_DMA_REQ_START  1
  37
  38 /*
  39  * IP blocks
  40  */
  41
  42 /*
  43  * 'dmm' class
  44  * instance(s): dmm
  45  */
  46 static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
  47         .name   = "dmm",
  48 };
  49
  50 /* dmm */
  51 static struct omap_hwmod omap44xx_dmm_hwmod = {
  52         .name           = "dmm",
  53         .class          = &omap44xx_dmm_hwmod_class,
  54         .clkdm_name     = "l3_emif_clkdm",
  55         .prcm = {
  56                 .omap4 = {
  57                         .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET,
  58                         .context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET,
  59                 },
  60         },
  61 };
  62
  63 /*
  64  * 'l3' class
  65  * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
  66  */
  67 static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
  68         .name   = "l3",
  69 };
  70
  71 /* l3_instr */
  72 static struct omap_hwmod omap44xx_l3_instr_hwmod = {
  73         .name           = "l3_instr",
  74         .class          = &omap44xx_l3_hwmod_class,
  75         .clkdm_name     = "l3_instr_clkdm",
  76         .prcm = {
  77                 .omap4 = {
  78                         .clkctrl_offs = OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
  79                         .context_offs = OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
  80                         .modulemode   = MODULEMODE_HWCTRL,
  81                 },
  82         },
  83 };
  84
  85 /* l3_main_1 */
  86 static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
  87         .name           = "l3_main_1",
  88         .class          = &omap44xx_l3_hwmod_class,
  89         .clkdm_name     = "l3_1_clkdm",
  90         .prcm = {
  91                 .omap4 = {
  92                         .clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET,
  93                         .context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET,
  94                 },
  95         },
  96 };
  97
  98 /* l3_main_2 */
  99 static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
 100         .name           = "l3_main_2",
 101         .class          = &omap44xx_l3_hwmod_class,
 102         .clkdm_name     = "l3_2_clkdm",
 103         .prcm = {
 104                 .omap4 = {
 105                         .clkctrl_offs = OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET,
 106                         .context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET,
 107                 },
 108         },
 109 };
 110
 111 /* l3_main_3 */
 112 static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
 113         .name           = "l3_main_3",
 114         .class          = &omap44xx_l3_hwmod_class,
 115         .clkdm_name     = "l3_instr_clkdm",
 116         .prcm = {
 117                 .omap4 = {
 118                         .clkctrl_offs = OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET,
 119                         .context_offs = OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET,
 120                         .modulemode   = MODULEMODE_HWCTRL,
 121                 },
 122         },
 123 };
 124
 125 /*
 126  * 'l4' class
 127  * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
 128  */
 129 static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
 130         .name   = "l4",
 131 };
 132
 133 /* l4_abe */
 134 static struct omap_hwmod omap44xx_l4_abe_hwmod = {
 135         .name           = "l4_abe",
 136         .class          = &omap44xx_l4_hwmod_class,
 137         .clkdm_name     = "abe_clkdm",
 138         .prcm = {
 139                 .omap4 = {
 140                         .clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET,
 141                         .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
 142                         .lostcontext_mask = OMAP4430_LOSTMEM_AESSMEM_MASK,
 143                         .flags        = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 144                 },
 145         },
 146 };
 147
 148 /* l4_cfg */
 149 static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
 150         .name           = "l4_cfg",
 151         .class          = &omap44xx_l4_hwmod_class,
 152         .clkdm_name     = "l4_cfg_clkdm",
 153         .prcm = {
 154                 .omap4 = {
 155                         .clkctrl_offs = OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
 156                         .context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
 157                 },
 158         },
 159 };
 160
 161 /* l4_per */
 162 static struct omap_hwmod omap44xx_l4_per_hwmod = {
 163         .name           = "l4_per",
 164         .class          = &omap44xx_l4_hwmod_class,
 165         .clkdm_name     = "l4_per_clkdm",
 166         .prcm = {
 167                 .omap4 = {
 168                         .clkctrl_offs = OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET,
 169                         .context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET,
 170                 },
 171         },
 172 };
 173
 174 /* l4_wkup */
 175 static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
 176         .name           = "l4_wkup",
 177         .class          = &omap44xx_l4_hwmod_class,
 178         .clkdm_name     = "l4_wkup_clkdm",
 179         .prcm = {
 180                 .omap4 = {
 181                         .clkctrl_offs = OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
 182                         .context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET,
 183                 },
 184         },
 185 };
 186
 187 /*
 188  * 'mpu_bus' class
 189  * instance(s): mpu_private
 190  */
 191 static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
 192         .name   = "mpu_bus",
 193 };
 194
 195 /* mpu_private */
 196 static struct omap_hwmod omap44xx_mpu_private_hwmod = {
 197         .name           = "mpu_private",
 198         .class          = &omap44xx_mpu_bus_hwmod_class,
 199         .clkdm_name     = "mpuss_clkdm",
 200         .prcm = {
 201                 .omap4 = {
 202                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 203                 },
 204         },
 205 };
 206
 207 /*
 208  * 'ocp_wp_noc' class
 209  * instance(s): ocp_wp_noc
 210  */
 211 static struct omap_hwmod_class omap44xx_ocp_wp_noc_hwmod_class = {
 212         .name   = "ocp_wp_noc",
 213 };
 214
 215 /* ocp_wp_noc */
 216 static struct omap_hwmod omap44xx_ocp_wp_noc_hwmod = {
 217         .name           = "ocp_wp_noc",
 218         .class          = &omap44xx_ocp_wp_noc_hwmod_class,
 219         .clkdm_name     = "l3_instr_clkdm",
 220         .prcm = {
 221                 .omap4 = {
 222                         .clkctrl_offs = OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET,
 223                         .context_offs = OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET,
 224                         .modulemode   = MODULEMODE_HWCTRL,
 225                 },
 226         },
 227 };
 228
 229 /*
 230  * Modules omap_hwmod structures
 231  *
 232  * The following IPs are excluded for the moment because:
 233  * - They do not need an explicit SW control using omap_hwmod API.
 234  * - They still need to be validated with the driver
 235  *   properly adapted to omap_hwmod / omap_device
 236  *
 237  * usim
 238  */
 239
 240 /*
 241  * 'aess' class
 242  * audio engine sub system
 243  */
 244
 245 static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = {
 246         .rev_offs       = 0x0000,
 247         .sysc_offs      = 0x0010,
 248         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
 249         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 250                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART |
 251                            MSTANDBY_SMART_WKUP),
 252         .sysc_fields    = &omap_hwmod_sysc_type2,
 253 };
 254
 255 static struct omap_hwmod_class omap44xx_aess_hwmod_class = {
 256         .name   = "aess",
 257         .sysc   = &omap44xx_aess_sysc,
 258         .enable_preprogram = omap_hwmod_aess_preprogram,
 259 };
 260
 261 /* aess */
 262 static struct omap_hwmod omap44xx_aess_hwmod = {
 263         .name           = "aess",
 264         .class          = &omap44xx_aess_hwmod_class,
 265         .clkdm_name     = "abe_clkdm",
 266         .main_clk       = "aess_fclk",
 267         .prcm = {
 268                 .omap4 = {
 269                         .clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET,
 270                         .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
 271                         .lostcontext_mask = OMAP4430_LOSTCONTEXT_DFF_MASK,
 272                         .modulemode   = MODULEMODE_SWCTRL,
 273                 },
 274         },
 275 };
 276
 277 /*
 278  * 'counter' class
 279  * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
 280  */
 281
 282 static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = {
 283         .rev_offs       = 0x0000,
 284         .sysc_offs      = 0x0004,
 285         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 286         .idlemodes      = (SIDLE_FORCE | SIDLE_NO),
 287         .sysc_fields    = &omap_hwmod_sysc_type1,
 288 };
 289
 290 static struct omap_hwmod_class omap44xx_counter_hwmod_class = {
 291         .name   = "counter",
 292         .sysc   = &omap44xx_counter_sysc,
 293 };
 294
 295 /* counter_32k */
 296 static struct omap_hwmod omap44xx_counter_32k_hwmod = {
 297         .name           = "counter_32k",
 298         .class          = &omap44xx_counter_hwmod_class,
 299         .clkdm_name     = "l4_wkup_clkdm",
 300         .flags          = HWMOD_SWSUP_SIDLE,
 301         .main_clk       = "sys_32k_ck",
 302         .prcm = {
 303                 .omap4 = {
 304                         .clkctrl_offs = OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
 305                         .context_offs = OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET,
 306                 },
 307         },
 308 };
 309
 310 /*
 311  * 'ctrl_module' class
 312  * attila core control module + core pad control module + wkup pad control
 313  * module + attila wkup control module
 314  */
 315
 316 static struct omap_hwmod_class_sysconfig omap44xx_ctrl_module_sysc = {
 317         .rev_offs       = 0x0000,
 318         .sysc_offs      = 0x0010,
 319         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 320         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 321                            SIDLE_SMART_WKUP),
 322         .sysc_fields    = &omap_hwmod_sysc_type2,
 323 };
 324
 325 static struct omap_hwmod_class omap44xx_ctrl_module_hwmod_class = {
 326         .name   = "ctrl_module",
 327         .sysc   = &omap44xx_ctrl_module_sysc,
 328 };
 329
 330 /* ctrl_module_core */
 331 static struct omap_hwmod omap44xx_ctrl_module_core_hwmod = {
 332         .name           = "ctrl_module_core",
 333         .class          = &omap44xx_ctrl_module_hwmod_class,
 334         .clkdm_name     = "l4_cfg_clkdm",
 335         .prcm = {
 336                 .omap4 = {
 337                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 338                 },
 339         },
 340 };
 341
 342 /* ctrl_module_pad_core */
 343 static struct omap_hwmod omap44xx_ctrl_module_pad_core_hwmod = {
 344         .name           = "ctrl_module_pad_core",
 345         .class          = &omap44xx_ctrl_module_hwmod_class,
 346         .clkdm_name     = "l4_cfg_clkdm",
 347         .prcm = {
 348                 .omap4 = {
 349                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 350                 },
 351         },
 352 };
 353
 354 /* ctrl_module_wkup */
 355 static struct omap_hwmod omap44xx_ctrl_module_wkup_hwmod = {
 356         .name           = "ctrl_module_wkup",
 357         .class          = &omap44xx_ctrl_module_hwmod_class,
 358         .clkdm_name     = "l4_wkup_clkdm",
 359         .prcm = {
 360                 .omap4 = {
 361                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 362                 },
 363         },
 364 };
 365
 366 /* ctrl_module_pad_wkup */
 367 static struct omap_hwmod omap44xx_ctrl_module_pad_wkup_hwmod = {
 368         .name           = "ctrl_module_pad_wkup",
 369         .class          = &omap44xx_ctrl_module_hwmod_class,
 370         .clkdm_name     = "l4_wkup_clkdm",
 371         .prcm = {
 372                 .omap4 = {
 373                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 374                 },
 375         },
 376 };
 377
 378 /*
 379  * 'debugss' class
 380  * debug and emulation sub system
 381  */
 382
 383 static struct omap_hwmod_class omap44xx_debugss_hwmod_class = {
 384         .name   = "debugss",
 385 };
 386
 387 /* debugss */
 388 static struct omap_hwmod omap44xx_debugss_hwmod = {
 389         .name           = "debugss",
 390         .class          = &omap44xx_debugss_hwmod_class,
 391         .clkdm_name     = "emu_sys_clkdm",
 392         .main_clk       = "trace_clk_div_ck",
 393         .prcm = {
 394                 .omap4 = {
 395                         .clkctrl_offs = OMAP4_CM_EMU_DEBUGSS_CLKCTRL_OFFSET,
 396                         .context_offs = OMAP4_RM_EMU_DEBUGSS_CONTEXT_OFFSET,
 397                 },
 398         },
 399 };
 400
 401 /*
 402  * 'dma' class
 403  * dma controller for data exchange between memory to memory (i.e. internal or
 404  * external memory) and gp peripherals to memory or memory to gp peripherals
 405  */
 406
 407 static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = {
 408         .rev_offs       = 0x0000,
 409         .sysc_offs      = 0x002c,
 410         .syss_offs      = 0x0028,
 411         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 412                            SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
 413                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 414                            SYSS_HAS_RESET_STATUS),
 415         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 416                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 417         .sysc_fields    = &omap_hwmod_sysc_type1,
 418 };
 419
 420 static struct omap_hwmod_class omap44xx_dma_hwmod_class = {
 421         .name   = "dma",
 422         .sysc   = &omap44xx_dma_sysc,
 423 };
 424
 425 /* dma dev_attr */
 426 static struct omap_dma_dev_attr dma_dev_attr = {
 427         .dev_caps       = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
 428                           IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
 429         .lch_count      = 32,
 430 };
 431
 432 /* dma_system */
 433 static struct omap_hwmod omap44xx_dma_system_hwmod = {
 434         .name           = "dma_system",
 435         .class          = &omap44xx_dma_hwmod_class,
 436         .clkdm_name     = "l3_dma_clkdm",
 437         .main_clk       = "l3_div_ck",
 438         .prcm = {
 439                 .omap4 = {
 440                         .clkctrl_offs = OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET,
 441                         .context_offs = OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET,
 442                 },
 443         },
 444         .dev_attr       = &dma_dev_attr,
 445 };
 446
 447 /*
 448  * 'dmic' class
 449  * digital microphone controller
 450  */
 451
 452 static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = {
 453         .rev_offs       = 0x0000,
 454         .sysc_offs      = 0x0010,
 455         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
 456                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
 457         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 458                            SIDLE_SMART_WKUP),
 459         .sysc_fields    = &omap_hwmod_sysc_type2,
 460 };
 461
 462 static struct omap_hwmod_class omap44xx_dmic_hwmod_class = {
 463         .name   = "dmic",
 464         .sysc   = &omap44xx_dmic_sysc,
 465 };
 466
 467 /* dmic */
 468 static struct omap_hwmod omap44xx_dmic_hwmod = {
 469         .name           = "dmic",
 470         .class          = &omap44xx_dmic_hwmod_class,
 471         .clkdm_name     = "abe_clkdm",
 472         .main_clk       = "func_dmic_abe_gfclk",
 473         .prcm = {
 474                 .omap4 = {
 475                         .clkctrl_offs = OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET,
 476                         .context_offs = OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET,
 477                         .modulemode   = MODULEMODE_SWCTRL,
 478                 },
 479         },
 480 };
 481
 482 /*
 483  * 'dsp' class
 484  * dsp sub-system
 485  */
 486
 487 static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
 488         .name   = "dsp",
 489 };
 490
 491 /* dsp */
 492 static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
 493         { .name = "dsp", .rst_shift = 0 },
 494 };
 495
 496 static struct omap_hwmod omap44xx_dsp_hwmod = {
 497         .name           = "dsp",
 498         .class          = &omap44xx_dsp_hwmod_class,
 499         .clkdm_name     = "tesla_clkdm",
 500         .rst_lines      = omap44xx_dsp_resets,
 501         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_dsp_resets),
 502         .main_clk       = "dpll_iva_m4x2_ck",
 503         .prcm = {
 504                 .omap4 = {
 505                         .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
 506                         .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
 507                         .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
 508                         .modulemode   = MODULEMODE_HWCTRL,
 509                 },
 510         },
 511 };
 512
 513 /*
 514  * 'dss' class
 515  * display sub-system
 516  */
 517
 518 static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = {
 519         .rev_offs       = 0x0000,
 520         .syss_offs      = 0x0014,
 521         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 522 };
 523
 524 static struct omap_hwmod_class omap44xx_dss_hwmod_class = {
 525         .name   = "dss",
 526         .sysc   = &omap44xx_dss_sysc,
 527         .reset  = omap_dss_reset,
 528 };
 529
 530 /* dss */
 531 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
 532         { .role = "sys_clk", .clk = "dss_sys_clk" },
 533         { .role = "tv_clk", .clk = "dss_tv_clk" },
 534         { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
 535 };
 536
 537 static struct omap_hwmod omap44xx_dss_hwmod = {
 538         .name           = "dss_core",
 539         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 540         .class          = &omap44xx_dss_hwmod_class,
 541         .clkdm_name     = "l3_dss_clkdm",
 542         .main_clk       = "dss_dss_clk",
 543         .prcm = {
 544                 .omap4 = {
 545                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 546                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 547                         .modulemode   = MODULEMODE_SWCTRL,
 548                 },
 549         },
 550         .opt_clks       = dss_opt_clks,
 551         .opt_clks_cnt   = ARRAY_SIZE(dss_opt_clks),
 552 };
 553
 554 /*
 555  * 'dispc' class
 556  * display controller
 557  */
 558
 559 static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = {
 560         .rev_offs       = 0x0000,
 561         .sysc_offs      = 0x0010,
 562         .syss_offs      = 0x0014,
 563         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 564                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
 565                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 566                            SYSS_HAS_RESET_STATUS),
 567         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 568                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 569         .sysc_fields    = &omap_hwmod_sysc_type1,
 570 };
 571
 572 static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
 573         .name   = "dispc",
 574         .sysc   = &omap44xx_dispc_sysc,
 575 };
 576
 577 /* dss_dispc */
 578 static struct omap_dss_dispc_dev_attr omap44xx_dss_dispc_dev_attr = {
 579         .manager_count          = 3,
 580         .has_framedonetv_irq    = 1
 581 };
 582
 583 static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
 584         .name           = "dss_dispc",
 585         .class          = &omap44xx_dispc_hwmod_class,
 586         .clkdm_name     = "l3_dss_clkdm",
 587         .main_clk       = "dss_dss_clk",
 588         .prcm = {
 589                 .omap4 = {
 590                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 591                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 592                 },
 593         },
 594         .dev_attr       = &omap44xx_dss_dispc_dev_attr,
 595         .parent_hwmod   = &omap44xx_dss_hwmod,
 596 };
 597
 598 /*
 599  * 'dsi' class
 600  * display serial interface controller
 601  */
 602
 603 static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = {
 604         .rev_offs       = 0x0000,
 605         .sysc_offs      = 0x0010,
 606         .syss_offs      = 0x0014,
 607         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 608                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 609                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 610         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 611         .sysc_fields    = &omap_hwmod_sysc_type1,
 612 };
 613
 614 static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
 615         .name   = "dsi",
 616         .sysc   = &omap44xx_dsi_sysc,
 617 };
 618
 619 /* dss_dsi1 */
 620 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
 621         { .role = "sys_clk", .clk = "dss_sys_clk" },
 622 };
 623
 624 static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
 625         .name           = "dss_dsi1",
 626         .class          = &omap44xx_dsi_hwmod_class,
 627         .clkdm_name     = "l3_dss_clkdm",
 628         .main_clk       = "dss_dss_clk",
 629         .prcm = {
 630                 .omap4 = {
 631                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 632                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 633                 },
 634         },
 635         .opt_clks       = dss_dsi1_opt_clks,
 636         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi1_opt_clks),
 637         .parent_hwmod   = &omap44xx_dss_hwmod,
 638 };
 639
 640 /* dss_dsi2 */
 641 static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = {
 642         { .role = "sys_clk", .clk = "dss_sys_clk" },
 643 };
 644
 645 static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
 646         .name           = "dss_dsi2",
 647         .class          = &omap44xx_dsi_hwmod_class,
 648         .clkdm_name     = "l3_dss_clkdm",
 649         .main_clk       = "dss_dss_clk",
 650         .prcm = {
 651                 .omap4 = {
 652                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 653                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 654                 },
 655         },
 656         .opt_clks       = dss_dsi2_opt_clks,
 657         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi2_opt_clks),
 658         .parent_hwmod   = &omap44xx_dss_hwmod,
 659 };
 660
 661 /*
 662  * 'hdmi' class
 663  * hdmi controller
 664  */
 665
 666 static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = {
 667         .rev_offs       = 0x0000,
 668         .sysc_offs      = 0x0010,
 669         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
 670                            SYSC_HAS_SOFTRESET),
 671         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 672                            SIDLE_SMART_WKUP),
 673         .sysc_fields    = &omap_hwmod_sysc_type2,
 674 };
 675
 676 static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
 677         .name   = "hdmi",
 678         .sysc   = &omap44xx_hdmi_sysc,
 679 };
 680
 681 /* dss_hdmi */
 682 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
 683         { .role = "sys_clk", .clk = "dss_sys_clk" },
 684         { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
 685 };
 686
 687 static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
 688         .name           = "dss_hdmi",
 689         .class          = &omap44xx_hdmi_hwmod_class,
 690         .clkdm_name     = "l3_dss_clkdm",
 691         /*
 692          * HDMI audio requires to use no-idle mode. Hence,
 693          * set idle mode by software.
 694          */
 695         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_OPT_CLKS_NEEDED,
 696         .main_clk       = "dss_48mhz_clk",
 697         .prcm = {
 698                 .omap4 = {
 699                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 700                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 701                 },
 702         },
 703         .opt_clks       = dss_hdmi_opt_clks,
 704         .opt_clks_cnt   = ARRAY_SIZE(dss_hdmi_opt_clks),
 705         .parent_hwmod   = &omap44xx_dss_hwmod,
 706 };
 707
 708 /*
 709  * 'rfbi' class
 710  * remote frame buffer interface
 711  */
 712
 713 static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = {
 714         .rev_offs       = 0x0000,
 715         .sysc_offs      = 0x0010,
 716         .syss_offs      = 0x0014,
 717         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
 718                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 719         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 720         .sysc_fields    = &omap_hwmod_sysc_type1,
 721 };
 722
 723 static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
 724         .name   = "rfbi",
 725         .sysc   = &omap44xx_rfbi_sysc,
 726 };
 727
 728 /* dss_rfbi */
 729 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
 730         { .role = "ick", .clk = "l3_div_ck" },
 731 };
 732
 733 static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
 734         .name           = "dss_rfbi",
 735         .class          = &omap44xx_rfbi_hwmod_class,
 736         .clkdm_name     = "l3_dss_clkdm",
 737         .main_clk       = "dss_dss_clk",
 738         .prcm = {
 739                 .omap4 = {
 740                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 741                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 742                 },
 743         },
 744         .opt_clks       = dss_rfbi_opt_clks,
 745         .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
 746         .parent_hwmod   = &omap44xx_dss_hwmod,
 747 };
 748
 749 /*
 750  * 'venc' class
 751  * video encoder
 752  */
 753
 754 static struct omap_hwmod_class omap44xx_venc_hwmod_class = {
 755         .name   = "venc",
 756 };
 757
 758 /* dss_venc */
 759 static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = {
 760         { .role = "tv_clk", .clk = "dss_tv_clk" },
 761 };
 762
 763 static struct omap_hwmod omap44xx_dss_venc_hwmod = {
 764         .name           = "dss_venc",
 765         .class          = &omap44xx_venc_hwmod_class,
 766         .clkdm_name     = "l3_dss_clkdm",
 767         .main_clk       = "dss_tv_clk",
 768         .flags          = HWMOD_OPT_CLKS_NEEDED,
 769         .prcm = {
 770                 .omap4 = {
 771                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 772                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 773                 },
 774         },
 775         .parent_hwmod   = &omap44xx_dss_hwmod,
 776         .opt_clks       = dss_venc_opt_clks,
 777         .opt_clks_cnt   = ARRAY_SIZE(dss_venc_opt_clks),
 778 };
 779
 780 /* sha0 HIB2 (the 'P' (public) device) */
 781 static struct omap_hwmod_class_sysconfig omap44xx_sha0_sysc = {
 782         .rev_offs       = 0x100,
 783         .sysc_offs      = 0x110,
 784         .syss_offs      = 0x114,
 785         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 786 };
 787
 788 static struct omap_hwmod_class omap44xx_sha0_hwmod_class = {
 789         .name           = "sham",
 790         .sysc           = &omap44xx_sha0_sysc,
 791 };
 792
 793 static struct omap_hwmod omap44xx_sha0_hwmod = {
 794         .name           = "sham",
 795         .class          = &omap44xx_sha0_hwmod_class,
 796         .clkdm_name     = "l4_secure_clkdm",
 797         .main_clk       = "l3_div_ck",
 798         .prcm           = {
 799                 .omap4 = {
 800                         .clkctrl_offs = OMAP4_CM_L4SEC_SHA2MD51_CLKCTRL_OFFSET,
 801                         .context_offs = OMAP4_RM_L4SEC_SHA2MD51_CONTEXT_OFFSET,
 802                         .modulemode   = MODULEMODE_SWCTRL,
 803                 },
 804         },
 805 };
 806
 807 /*
 808  * 'elm' class
 809  * bch error location module
 810  */
 811
 812 static struct omap_hwmod_class_sysconfig omap44xx_elm_sysc = {
 813         .rev_offs       = 0x0000,
 814         .sysc_offs      = 0x0010,
 815         .syss_offs      = 0x0014,
 816         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 817                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 818                            SYSS_HAS_RESET_STATUS),
 819         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 820         .sysc_fields    = &omap_hwmod_sysc_type1,
 821 };
 822
 823 static struct omap_hwmod_class omap44xx_elm_hwmod_class = {
 824         .name   = "elm",
 825         .sysc   = &omap44xx_elm_sysc,
 826 };
 827
 828 /* elm */
 829 static struct omap_hwmod omap44xx_elm_hwmod = {
 830         .name           = "elm",
 831         .class          = &omap44xx_elm_hwmod_class,
 832         .clkdm_name     = "l4_per_clkdm",
 833         .prcm = {
 834                 .omap4 = {
 835                         .clkctrl_offs = OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET,
 836                         .context_offs = OMAP4_RM_L4PER_ELM_CONTEXT_OFFSET,
 837                 },
 838         },
 839 };
 840
 841 /*
 842  * 'emif' class
 843  * external memory interface no1
 844  */
 845
 846 static struct omap_hwmod_class_sysconfig omap44xx_emif_sysc = {
 847         .rev_offs       = 0x0000,
 848 };
 849
 850 static struct omap_hwmod_class omap44xx_emif_hwmod_class = {
 851         .name   = "emif",
 852         .sysc   = &omap44xx_emif_sysc,
 853 };
 854
 855 /* emif1 */
 856 static struct omap_hwmod omap44xx_emif1_hwmod = {
 857         .name           = "emif1",
 858         .class          = &omap44xx_emif_hwmod_class,
 859         .clkdm_name     = "l3_emif_clkdm",
 860         .flags          = HWMOD_INIT_NO_IDLE,
 861         .main_clk       = "ddrphy_ck",
 862         .prcm = {
 863                 .omap4 = {
 864                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET,
 865                         .context_offs = OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET,
 866                         .modulemode   = MODULEMODE_HWCTRL,
 867                 },
 868         },
 869 };
 870
 871 /* emif2 */
 872 static struct omap_hwmod omap44xx_emif2_hwmod = {
 873         .name           = "emif2",
 874         .class          = &omap44xx_emif_hwmod_class,
 875         .clkdm_name     = "l3_emif_clkdm",
 876         .flags          = HWMOD_INIT_NO_IDLE,
 877         .main_clk       = "ddrphy_ck",
 878         .prcm = {
 879                 .omap4 = {
 880                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET,
 881                         .context_offs = OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET,
 882                         .modulemode   = MODULEMODE_HWCTRL,
 883                 },
 884         },
 885 };
 886
 887 /*
 888     Crypto modules AES0/1 belong to:
 889         PD_L4_PER power domain
 890         CD_L4_SEC clock domain
 891         On the L3, the AES modules are mapped to
 892         L3_CLK2: Peripherals and multimedia sub clock domain
 893 */
 894 static struct omap_hwmod_class_sysconfig omap44xx_aes_sysc = {
 895         .rev_offs       = 0x80,
 896         .sysc_offs      = 0x84,
 897         .syss_offs      = 0x88,
 898         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 899 };
 900
 901 static struct omap_hwmod_class omap44xx_aes_hwmod_class = {
 902         .name           = "aes",
 903         .sysc           = &omap44xx_aes_sysc,
 904 };
 905
 906 static struct omap_hwmod omap44xx_aes1_hwmod = {
 907         .name           = "aes1",
 908         .class          = &omap44xx_aes_hwmod_class,
 909         .clkdm_name     = "l4_secure_clkdm",
 910         .main_clk       = "l3_div_ck",
 911         .prcm           = {
 912                 .omap4  = {
 913                         .context_offs   = OMAP4_RM_L4SEC_AES1_CONTEXT_OFFSET,
 914                         .clkctrl_offs   = OMAP4_CM_L4SEC_AES1_CLKCTRL_OFFSET,
 915                         .modulemode     = MODULEMODE_SWCTRL,
 916                 },
 917         },
 918 };
 919
 920 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__aes1 = {
 921         .master         = &omap44xx_l4_per_hwmod,
 922         .slave          = &omap44xx_aes1_hwmod,
 923         .clk            = "l3_div_ck",
 924         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 925 };
 926
 927 static struct omap_hwmod omap44xx_aes2_hwmod = {
 928         .name           = "aes2",
 929         .class          = &omap44xx_aes_hwmod_class,
 930         .clkdm_name     = "l4_secure_clkdm",
 931         .main_clk       = "l3_div_ck",
 932         .prcm           = {
 933                 .omap4  = {
 934                         .context_offs   = OMAP4_RM_L4SEC_AES2_CONTEXT_OFFSET,
 935                         .clkctrl_offs   = OMAP4_CM_L4SEC_AES2_CLKCTRL_OFFSET,
 936                         .modulemode     = MODULEMODE_SWCTRL,
 937                 },
 938         },
 939 };
 940
 941 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__aes2 = {
 942         .master         = &omap44xx_l4_per_hwmod,
 943         .slave          = &omap44xx_aes2_hwmod,
 944         .clk            = "l3_div_ck",
 945         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 946 };
 947
 948 /*
 949  * 'des' class for DES3DES module
 950  */
 951 static struct omap_hwmod_class_sysconfig omap44xx_des_sysc = {
 952         .rev_offs       = 0x30,
 953         .sysc_offs      = 0x34,
 954         .syss_offs      = 0x38,
 955         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 956 };
 957
 958 static struct omap_hwmod_class omap44xx_des_hwmod_class = {
 959         .name           = "des",
 960         .sysc           = &omap44xx_des_sysc,
 961 };
 962
 963 static struct omap_hwmod omap44xx_des_hwmod = {
 964         .name           = "des",
 965         .class          = &omap44xx_des_hwmod_class,
 966         .clkdm_name     = "l4_secure_clkdm",
 967         .main_clk       = "l3_div_ck",
 968         .prcm           = {
 969                 .omap4  = {
 970                         .context_offs   = OMAP4_RM_L4SEC_DES3DES_CONTEXT_OFFSET,
 971                         .clkctrl_offs   = OMAP4_CM_L4SEC_DES3DES_CLKCTRL_OFFSET,
 972                         .modulemode     = MODULEMODE_SWCTRL,
 973                 },
 974         },
 975 };
 976
 977 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__des = {
 978         .master         = &omap44xx_l3_main_2_hwmod,
 979         .slave          = &omap44xx_des_hwmod,
 980         .clk            = "l3_div_ck",
 981         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 982 };
 983
 984 /*
 985  * 'fdif' class
 986  * face detection hw accelerator module
 987  */
 988
 989 static struct omap_hwmod_class_sysconfig omap44xx_fdif_sysc = {
 990         .rev_offs       = 0x0000,
 991         .sysc_offs      = 0x0010,
 992         /*
 993          * FDIF needs 100 OCP clk cycles delay after a softreset before
 994          * accessing sysconfig again.
 995          * The lowest frequency at the moment for L3 bus is 100 MHz, so
 996          * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
 997          *
 998          * TODO: Indicate errata when available.
 999          */
1000         .srst_udelay    = 2,
1001         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1002                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1003         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1004                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1005         .sysc_fields    = &omap_hwmod_sysc_type2,
1006 };
1007
1008 static struct omap_hwmod_class omap44xx_fdif_hwmod_class = {
1009         .name   = "fdif",
1010         .sysc   = &omap44xx_fdif_sysc,
1011 };
1012
1013 /* fdif */
1014 static struct omap_hwmod omap44xx_fdif_hwmod = {
1015         .name           = "fdif",
1016         .class          = &omap44xx_fdif_hwmod_class,
1017         .clkdm_name     = "iss_clkdm",
1018         .main_clk       = "fdif_fck",
1019         .prcm = {
1020                 .omap4 = {
1021                         .clkctrl_offs = OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET,
1022                         .context_offs = OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET,
1023                         .modulemode   = MODULEMODE_SWCTRL,
1024                 },
1025         },
1026 };
1027
1028 /*
1029  * 'gpmc' class
1030  * general purpose memory controller
1031  */
1032
1033 static struct omap_hwmod_class_sysconfig omap44xx_gpmc_sysc = {
1034         .rev_offs       = 0x0000,
1035         .sysc_offs      = 0x0010,
1036         .syss_offs      = 0x0014,
1037         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1038                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1039         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1040         .sysc_fields    = &omap_hwmod_sysc_type1,
1041 };
1042
1043 static struct omap_hwmod_class omap44xx_gpmc_hwmod_class = {
1044         .name   = "gpmc",
1045         .sysc   = &omap44xx_gpmc_sysc,
1046 };
1047
1048 /* gpmc */
1049 static struct omap_hwmod omap44xx_gpmc_hwmod = {
1050         .name           = "gpmc",
1051         .class          = &omap44xx_gpmc_hwmod_class,
1052         .clkdm_name     = "l3_2_clkdm",
1053         /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
1054         .flags          = DEBUG_OMAP_GPMC_HWMOD_FLAGS,
1055         .prcm = {
1056                 .omap4 = {
1057                         .clkctrl_offs = OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET,
1058                         .context_offs = OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET,
1059                         .modulemode   = MODULEMODE_HWCTRL,
1060                 },
1061         },
1062 };
1063
1064
1065 /*
1066  * 'hsi' class
1067  * mipi high-speed synchronous serial interface (multichannel and full-duplex
1068  * serial if)
1069  */
1070
1071 static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = {
1072         .rev_offs       = 0x0000,
1073         .sysc_offs      = 0x0010,
1074         .syss_offs      = 0x0014,
1075         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE |
1076                            SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
1077                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1078         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1079                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1080                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1081         .sysc_fields    = &omap_hwmod_sysc_type1,
1082 };
1083
1084 static struct omap_hwmod_class omap44xx_hsi_hwmod_class = {
1085         .name   = "hsi",
1086         .sysc   = &omap44xx_hsi_sysc,
1087 };
1088
1089 /* hsi */
1090 static struct omap_hwmod omap44xx_hsi_hwmod = {
1091         .name           = "hsi",
1092         .class          = &omap44xx_hsi_hwmod_class,
1093         .clkdm_name     = "l3_init_clkdm",
1094         .main_clk       = "hsi_fck",
1095         .prcm = {
1096                 .omap4 = {
1097                         .clkctrl_offs = OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET,
1098                         .context_offs = OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET,
1099                         .modulemode   = MODULEMODE_HWCTRL,
1100                 },
1101         },
1102 };
1103
1104 /*
1105  * 'ipu' class
1106  * imaging processor unit
1107  */
1108
1109 static struct omap_hwmod_class omap44xx_ipu_hwmod_class = {
1110         .name   = "ipu",
1111 };
1112
1113 /* ipu */
1114 static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
1115         { .name = "cpu0", .rst_shift = 0 },
1116         { .name = "cpu1", .rst_shift = 1 },
1117 };
1118
1119 static struct omap_hwmod omap44xx_ipu_hwmod = {
1120         .name           = "ipu",
1121         .class          = &omap44xx_ipu_hwmod_class,
1122         .clkdm_name     = "ducati_clkdm",
1123         .rst_lines      = omap44xx_ipu_resets,
1124         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_ipu_resets),
1125         .main_clk       = "ducati_clk_mux_ck",
1126         .prcm = {
1127                 .omap4 = {
1128                         .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
1129                         .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
1130                         .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
1131                         .modulemode   = MODULEMODE_HWCTRL,
1132                 },
1133         },
1134 };
1135
1136 /*
1137  * 'iss' class
1138  * external images sensor pixel data processor
1139  */
1140
1141 static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = {
1142         .rev_offs       = 0x0000,
1143         .sysc_offs      = 0x0010,
1144         /*
1145          * ISS needs 100 OCP clk cycles delay after a softreset before
1146          * accessing sysconfig again.
1147          * The lowest frequency at the moment for L3 bus is 100 MHz, so
1148          * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
1149          *
1150          * TODO: Indicate errata when available.
1151          */
1152         .srst_udelay    = 2,
1153         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1154                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1155         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1156                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1157                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1158         .sysc_fields    = &omap_hwmod_sysc_type2,
1159 };
1160
1161 static struct omap_hwmod_class omap44xx_iss_hwmod_class = {
1162         .name   = "iss",
1163         .sysc   = &omap44xx_iss_sysc,
1164 };
1165
1166 /* iss */
1167 static struct omap_hwmod_opt_clk iss_opt_clks[] = {
1168         { .role = "ctrlclk", .clk = "iss_ctrlclk" },
1169 };
1170
1171 static struct omap_hwmod omap44xx_iss_hwmod = {
1172         .name           = "iss",
1173         .class          = &omap44xx_iss_hwmod_class,
1174         .clkdm_name     = "iss_clkdm",
1175         .main_clk       = "ducati_clk_mux_ck",
1176         .prcm = {
1177                 .omap4 = {
1178                         .clkctrl_offs = OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET,
1179                         .context_offs = OMAP4_RM_CAM_ISS_CONTEXT_OFFSET,
1180                         .modulemode   = MODULEMODE_SWCTRL,
1181                 },
1182         },
1183         .opt_clks       = iss_opt_clks,
1184         .opt_clks_cnt   = ARRAY_SIZE(iss_opt_clks),
1185 };
1186
1187 /*
1188  * 'iva' class
1189  * multi-standard video encoder/decoder hardware accelerator
1190  */
1191
1192 static struct omap_hwmod_class omap44xx_iva_hwmod_class = {
1193         .name   = "iva",
1194 };
1195
1196 /* iva */
1197 static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
1198         { .name = "seq0", .rst_shift = 0 },
1199         { .name = "seq1", .rst_shift = 1 },
1200         { .name = "logic", .rst_shift = 2 },
1201 };
1202
1203 static struct omap_hwmod omap44xx_iva_hwmod = {
1204         .name           = "iva",
1205         .class          = &omap44xx_iva_hwmod_class,
1206         .clkdm_name     = "ivahd_clkdm",
1207         .rst_lines      = omap44xx_iva_resets,
1208         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_resets),
1209         .main_clk       = "dpll_iva_m5x2_ck",
1210         .prcm = {
1211                 .omap4 = {
1212                         .clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET,
1213                         .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
1214                         .context_offs = OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET,
1215                         .modulemode   = MODULEMODE_HWCTRL,
1216                 },
1217         },
1218 };
1219
1220 /*
1221  * 'kbd' class
1222  * keyboard controller
1223  */
1224
1225 static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = {
1226         .rev_offs       = 0x0000,
1227         .sysc_offs      = 0x0010,
1228         .syss_offs      = 0x0014,
1229         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1230                            SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
1231                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1232                            SYSS_HAS_RESET_STATUS),
1233         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1234         .sysc_fields    = &omap_hwmod_sysc_type1,
1235 };
1236
1237 static struct omap_hwmod_class omap44xx_kbd_hwmod_class = {
1238         .name   = "kbd",
1239         .sysc   = &omap44xx_kbd_sysc,
1240 };
1241
1242 /* kbd */
1243 static struct omap_hwmod omap44xx_kbd_hwmod = {
1244         .name           = "kbd",
1245         .class          = &omap44xx_kbd_hwmod_class,
1246         .clkdm_name     = "l4_wkup_clkdm",
1247         .main_clk       = "sys_32k_ck",
1248         .prcm = {
1249                 .omap4 = {
1250                         .clkctrl_offs = OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET,
1251                         .context_offs = OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET,
1252                         .modulemode   = MODULEMODE_SWCTRL,
1253                 },
1254         },
1255 };
1256
1257
1258 /*
1259  * 'mcpdm' class
1260  * multi channel pdm controller (proprietary interface with phoenix power
1261  * ic)
1262  */
1263
1264 static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc = {
1265         .rev_offs       = 0x0000,
1266         .sysc_offs      = 0x0010,
1267         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1268                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1269         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1270                            SIDLE_SMART_WKUP),
1271         .sysc_fields    = &omap_hwmod_sysc_type2,
1272 };
1273
1274 static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = {
1275         .name   = "mcpdm",
1276         .sysc   = &omap44xx_mcpdm_sysc,
1277 };
1278
1279 /* mcpdm */
1280 static struct omap_hwmod omap44xx_mcpdm_hwmod = {
1281         .name           = "mcpdm",
1282         .class          = &omap44xx_mcpdm_hwmod_class,
1283         .clkdm_name     = "abe_clkdm",
1284         /*
1285          * It's suspected that the McPDM requires an off-chip main
1286          * functional clock, controlled via I2C.  This IP block is
1287          * currently reset very early during boot, before I2C is
1288          * available, so it doesn't seem that we have any choice in
1289          * the kernel other than to avoid resetting it.
1290          *
1291          * Also, McPDM needs to be configured to NO_IDLE mode when it
1292          * is in used otherwise vital clocks will be gated which
1293          * results 'slow motion' audio playback.
1294          */
1295         .flags          = HWMOD_EXT_OPT_MAIN_CLK | HWMOD_SWSUP_SIDLE,
1296         .main_clk       = "pad_clks_ck",
1297         .prcm = {
1298                 .omap4 = {
1299                         .clkctrl_offs = OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET,
1300                         .context_offs = OMAP4_RM_ABE_PDM_CONTEXT_OFFSET,
1301                         .modulemode   = MODULEMODE_SWCTRL,
1302                 },
1303         },
1304 };
1305
1306 /*
1307  * 'mmu' class
1308  * The memory management unit performs virtual to physical address translation
1309  * for its requestors.
1310  */
1311
1312 static struct omap_hwmod_class_sysconfig mmu_sysc = {
1313         .rev_offs       = 0x000,
1314         .sysc_offs      = 0x010,
1315         .syss_offs      = 0x014,
1316         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1317                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1318         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1319         .sysc_fields    = &omap_hwmod_sysc_type1,
1320 };
1321
1322 static struct omap_hwmod_class omap44xx_mmu_hwmod_class = {
1323         .name = "mmu",
1324         .sysc = &mmu_sysc,
1325 };
1326
1327 /* mmu ipu */
1328
1329 static struct omap_hwmod omap44xx_mmu_ipu_hwmod;
1330 static struct omap_hwmod_rst_info omap44xx_mmu_ipu_resets[] = {
1331         { .name = "mmu_cache", .rst_shift = 2 },
1332 };
1333
1334 /* l3_main_2 -> mmu_ipu */
1335 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__mmu_ipu = {
1336         .master         = &omap44xx_l3_main_2_hwmod,
1337         .slave          = &omap44xx_mmu_ipu_hwmod,
1338         .clk            = "l3_div_ck",
1339         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1340 };
1341
1342 static struct omap_hwmod omap44xx_mmu_ipu_hwmod = {
1343         .name           = "mmu_ipu",
1344         .class          = &omap44xx_mmu_hwmod_class,
1345         .clkdm_name     = "ducati_clkdm",
1346         .rst_lines      = omap44xx_mmu_ipu_resets,
1347         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_mmu_ipu_resets),
1348         .main_clk       = "ducati_clk_mux_ck",
1349         .prcm = {
1350                 .omap4 = {
1351                         .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
1352                         .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
1353                         .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
1354                         .modulemode   = MODULEMODE_HWCTRL,
1355                 },
1356         },
1357 };
1358
1359 /* mmu dsp */
1360
1361 static struct omap_hwmod omap44xx_mmu_dsp_hwmod;
1362 static struct omap_hwmod_rst_info omap44xx_mmu_dsp_resets[] = {
1363         { .name = "mmu_cache", .rst_shift = 1 },
1364 };
1365
1366 /* l4_cfg -> dsp */
1367 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mmu_dsp = {
1368         .master         = &omap44xx_l4_cfg_hwmod,
1369         .slave          = &omap44xx_mmu_dsp_hwmod,
1370         .clk            = "l4_div_ck",
1371         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1372 };
1373
1374 static struct omap_hwmod omap44xx_mmu_dsp_hwmod = {
1375         .name           = "mmu_dsp",
1376         .class          = &omap44xx_mmu_hwmod_class,
1377         .clkdm_name     = "tesla_clkdm",
1378         .rst_lines      = omap44xx_mmu_dsp_resets,
1379         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_mmu_dsp_resets),
1380         .main_clk       = "dpll_iva_m4x2_ck",
1381         .prcm = {
1382                 .omap4 = {
1383                         .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
1384                         .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
1385                         .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
1386                         .modulemode   = MODULEMODE_HWCTRL,
1387                 },
1388         },
1389 };
1390
1391 /*
1392  * 'mpu' class
1393  * mpu sub-system
1394  */
1395
1396 static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
1397         .name   = "mpu",
1398 };
1399
1400 /* mpu */
1401 static struct omap_hwmod omap44xx_mpu_hwmod = {
1402         .name           = "mpu",
1403         .class          = &omap44xx_mpu_hwmod_class,
1404         .clkdm_name     = "mpuss_clkdm",
1405         .flags          = HWMOD_INIT_NO_IDLE,
1406         .main_clk       = "dpll_mpu_m2_ck",
1407         .prcm = {
1408                 .omap4 = {
1409                         .clkctrl_offs = OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET,
1410                         .context_offs = OMAP4_RM_MPU_MPU_CONTEXT_OFFSET,
1411                 },
1412         },
1413 };
1414
1415 /*
1416  * 'ocmc_ram' class
1417  * top-level core on-chip ram
1418  */
1419
1420 static struct omap_hwmod_class omap44xx_ocmc_ram_hwmod_class = {
1421         .name   = "ocmc_ram",
1422 };
1423
1424 /* ocmc_ram */
1425 static struct omap_hwmod omap44xx_ocmc_ram_hwmod = {
1426         .name           = "ocmc_ram",
1427         .class          = &omap44xx_ocmc_ram_hwmod_class,
1428         .clkdm_name     = "l3_2_clkdm",
1429         .prcm = {
1430                 .omap4 = {
1431                         .clkctrl_offs = OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET,
1432                         .context_offs = OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET,
1433                 },
1434         },
1435 };
1436
1437 /*
1438  * 'ocp2scp' class
1439  * bridge to transform ocp interface protocol to scp (serial control port)
1440  * protocol
1441  */
1442
1443 static struct omap_hwmod_class_sysconfig omap44xx_ocp2scp_sysc = {
1444         .rev_offs       = 0x0000,
1445         .sysc_offs      = 0x0010,
1446         .syss_offs      = 0x0014,
1447         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1448                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1449         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1450         .sysc_fields    = &omap_hwmod_sysc_type1,
1451 };
1452
1453 static struct omap_hwmod_class omap44xx_ocp2scp_hwmod_class = {
1454         .name   = "ocp2scp",
1455         .sysc   = &omap44xx_ocp2scp_sysc,
1456 };
1457
1458 /* ocp2scp_usb_phy */
1459 static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = {
1460         .name           = "ocp2scp_usb_phy",
1461         .class          = &omap44xx_ocp2scp_hwmod_class,
1462         .clkdm_name     = "l3_init_clkdm",
1463         /*
1464          * ocp2scp_usb_phy_phy_48m is provided by the OMAP4 PRCM IP
1465          * block as an "optional clock," and normally should never be
1466          * specified as the main_clk for an OMAP IP block.  However it
1467          * turns out that this clock is actually the main clock for
1468          * the ocp2scp_usb_phy IP block:
1469          * http://lists.infradead.org/pipermail/linux-arm-kernel/2012-September/119943.html
1470          * So listing ocp2scp_usb_phy_phy_48m as a main_clk here seems
1471          * to be the best workaround.
1472          */
1473         .main_clk       = "ocp2scp_usb_phy_phy_48m",
1474         .prcm = {
1475                 .omap4 = {
1476                         .clkctrl_offs = OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET,
1477                         .context_offs = OMAP4_RM_L3INIT_USBPHYOCP2SCP_CONTEXT_OFFSET,
1478                         .modulemode   = MODULEMODE_HWCTRL,
1479                 },
1480         },
1481 };
1482
1483 /*
1484  * 'prcm' class
1485  * power and reset manager (part of the prcm infrastructure) + clock manager 2
1486  * + clock manager 1 (in always on power domain) + local prm in mpu
1487  */
1488
1489 static struct omap_hwmod_class omap44xx_prcm_hwmod_class = {
1490         .name   = "prcm",
1491 };
1492
1493 /* prcm_mpu */
1494 static struct omap_hwmod omap44xx_prcm_mpu_hwmod = {
1495         .name           = "prcm_mpu",
1496         .class          = &omap44xx_prcm_hwmod_class,
1497         .clkdm_name     = "l4_wkup_clkdm",
1498         .flags          = HWMOD_NO_IDLEST,
1499         .prcm = {
1500                 .omap4 = {
1501                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
1502                 },
1503         },
1504 };
1505
1506 /* cm_core_aon */
1507 static struct omap_hwmod omap44xx_cm_core_aon_hwmod = {
1508         .name           = "cm_core_aon",
1509         .class          = &omap44xx_prcm_hwmod_class,
1510         .flags          = HWMOD_NO_IDLEST,
1511         .prcm = {
1512                 .omap4 = {
1513                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
1514                 },
1515         },
1516 };
1517
1518 /* cm_core */
1519 static struct omap_hwmod omap44xx_cm_core_hwmod = {
1520         .name           = "cm_core",
1521         .class          = &omap44xx_prcm_hwmod_class,
1522         .flags          = HWMOD_NO_IDLEST,
1523         .prcm = {
1524                 .omap4 = {
1525                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
1526                 },
1527         },
1528 };
1529
1530 /* prm */
1531 static struct omap_hwmod_rst_info omap44xx_prm_resets[] = {
1532         { .name = "rst_global_warm_sw", .rst_shift = 0 },
1533         { .name = "rst_global_cold_sw", .rst_shift = 1 },
1534 };
1535
1536 static struct omap_hwmod omap44xx_prm_hwmod = {
1537         .name           = "prm",
1538         .class          = &omap44xx_prcm_hwmod_class,
1539         .rst_lines      = omap44xx_prm_resets,
1540         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_prm_resets),
1541 };
1542
1543 /*
1544  * 'scrm' class
1545  * system clock and reset manager
1546  */
1547
1548 static struct omap_hwmod_class omap44xx_scrm_hwmod_class = {
1549         .name   = "scrm",
1550 };
1551
1552 /* scrm */
1553 static struct omap_hwmod omap44xx_scrm_hwmod = {
1554         .name           = "scrm",
1555         .class          = &omap44xx_scrm_hwmod_class,
1556         .clkdm_name     = "l4_wkup_clkdm",
1557         .prcm = {
1558                 .omap4 = {
1559                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
1560                 },
1561         },
1562 };
1563
1564 /*
1565  * 'sl2if' class
1566  * shared level 2 memory interface
1567  */
1568
1569 static struct omap_hwmod_class omap44xx_sl2if_hwmod_class = {
1570         .name   = "sl2if",
1571 };
1572
1573 /* sl2if */
1574 static struct omap_hwmod omap44xx_sl2if_hwmod = {
1575         .name           = "sl2if",
1576         .class          = &omap44xx_sl2if_hwmod_class,
1577         .clkdm_name     = "ivahd_clkdm",
1578         .prcm = {
1579                 .omap4 = {
1580                         .clkctrl_offs = OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET,
1581                         .context_offs = OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET,
1582                         .modulemode   = MODULEMODE_HWCTRL,
1583                 },
1584         },
1585 };
1586
1587 /*
1588  * 'slimbus' class
1589  * bidirectional, multi-drop, multi-channel two-line serial interface between
1590  * the device and external components
1591  */
1592
1593 static struct omap_hwmod_class_sysconfig omap44xx_slimbus_sysc = {
1594         .rev_offs       = 0x0000,
1595         .sysc_offs      = 0x0010,
1596         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1597                            SYSC_HAS_SOFTRESET),
1598         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1599                            SIDLE_SMART_WKUP),
1600         .sysc_fields    = &omap_hwmod_sysc_type2,
1601 };
1602
1603 static struct omap_hwmod_class omap44xx_slimbus_hwmod_class = {
1604         .name   = "slimbus",
1605         .sysc   = &omap44xx_slimbus_sysc,
1606 };
1607
1608 /* slimbus1 */
1609 static struct omap_hwmod_opt_clk slimbus1_opt_clks[] = {
1610         { .role = "fclk_1", .clk = "slimbus1_fclk_1" },
1611         { .role = "fclk_0", .clk = "slimbus1_fclk_0" },
1612         { .role = "fclk_2", .clk = "slimbus1_fclk_2" },
1613         { .role = "slimbus_clk", .clk = "slimbus1_slimbus_clk" },
1614 };
1615
1616 static struct omap_hwmod omap44xx_slimbus1_hwmod = {
1617         .name           = "slimbus1",
1618         .class          = &omap44xx_slimbus_hwmod_class,
1619         .clkdm_name     = "abe_clkdm",
1620         .prcm = {
1621                 .omap4 = {
1622                         .clkctrl_offs = OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET,
1623                         .context_offs = OMAP4_RM_ABE_SLIMBUS_CONTEXT_OFFSET,
1624                         .modulemode   = MODULEMODE_SWCTRL,
1625                 },
1626         },
1627         .opt_clks       = slimbus1_opt_clks,
1628         .opt_clks_cnt   = ARRAY_SIZE(slimbus1_opt_clks),
1629 };
1630
1631 /* slimbus2 */
1632 static struct omap_hwmod_opt_clk slimbus2_opt_clks[] = {
1633         { .role = "fclk_1", .clk = "slimbus2_fclk_1" },
1634         { .role = "fclk_0", .clk = "slimbus2_fclk_0" },
1635         { .role = "slimbus_clk", .clk = "slimbus2_slimbus_clk" },
1636 };
1637
1638 static struct omap_hwmod omap44xx_slimbus2_hwmod = {
1639         .name           = "slimbus2",
1640         .class          = &omap44xx_slimbus_hwmod_class,
1641         .clkdm_name     = "l4_per_clkdm",
1642         .prcm = {
1643                 .omap4 = {
1644                         .clkctrl_offs = OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET,
1645                         .context_offs = OMAP4_RM_L4PER_SLIMBUS2_CONTEXT_OFFSET,
1646                         .modulemode   = MODULEMODE_SWCTRL,
1647                 },
1648         },
1649         .opt_clks       = slimbus2_opt_clks,
1650         .opt_clks_cnt   = ARRAY_SIZE(slimbus2_opt_clks),
1651 };
1652
1653 /*
1654  * 'smartreflex' class
1655  * smartreflex module (monitor silicon performance and outputs a measure of
1656  * performance error)
1657  */
1658
1659 /* The IP is not compliant to type1 / type2 scheme */
1660 static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
1661         .rev_offs       = -ENODEV,
1662         .sysc_offs      = 0x0038,
1663         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
1664         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1665                            SIDLE_SMART_WKUP),
1666         .sysc_fields    = &omap36xx_sr_sysc_fields,
1667 };
1668
1669 static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
1670         .name   = "smartreflex",
1671         .sysc   = &omap44xx_smartreflex_sysc,
1672 };
1673
1674 /* smartreflex_core */
1675 static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
1676         .sensor_voltdm_name   = "core",
1677 };
1678
1679 static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
1680         .name           = "smartreflex_core",
1681         .class          = &omap44xx_smartreflex_hwmod_class,
1682         .clkdm_name     = "l4_ao_clkdm",
1683
1684         .main_clk       = "smartreflex_core_fck",
1685         .prcm = {
1686                 .omap4 = {
1687                         .clkctrl_offs = OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET,
1688                         .context_offs = OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET,
1689                         .modulemode   = MODULEMODE_SWCTRL,
1690                 },
1691         },
1692         .dev_attr       = &smartreflex_core_dev_attr,
1693 };
1694
1695 /* smartreflex_iva */
1696 static struct omap_smartreflex_dev_attr smartreflex_iva_dev_attr = {
1697         .sensor_voltdm_name     = "iva",
1698 };
1699
1700 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
1701         .name           = "smartreflex_iva",
1702         .class          = &omap44xx_smartreflex_hwmod_class,
1703         .clkdm_name     = "l4_ao_clkdm",
1704         .main_clk       = "smartreflex_iva_fck",
1705         .prcm = {
1706                 .omap4 = {
1707                         .clkctrl_offs = OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET,
1708                         .context_offs = OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET,
1709                         .modulemode   = MODULEMODE_SWCTRL,
1710                 },
1711         },
1712         .dev_attr       = &smartreflex_iva_dev_attr,
1713 };
1714
1715 /* smartreflex_mpu */
1716 static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
1717         .sensor_voltdm_name     = "mpu",
1718 };
1719
1720 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
1721         .name           = "smartreflex_mpu",
1722         .class          = &omap44xx_smartreflex_hwmod_class,
1723         .clkdm_name     = "l4_ao_clkdm",
1724         .main_clk       = "smartreflex_mpu_fck",
1725         .prcm = {
1726                 .omap4 = {
1727                         .clkctrl_offs = OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET,
1728                         .context_offs = OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET,
1729                         .modulemode   = MODULEMODE_SWCTRL,
1730                 },
1731         },
1732         .dev_attr       = &smartreflex_mpu_dev_attr,
1733 };
1734
1735 /*
1736  * 'spinlock' class
1737  * spinlock provides hardware assistance for synchronizing the processes
1738  * running on multiple processors
1739  */
1740
1741 static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = {
1742         .rev_offs       = 0x0000,
1743         .sysc_offs      = 0x0010,
1744         .syss_offs      = 0x0014,
1745         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1746                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1747                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1748         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1749         .sysc_fields    = &omap_hwmod_sysc_type1,
1750 };
1751
1752 static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = {
1753         .name   = "spinlock",
1754         .sysc   = &omap44xx_spinlock_sysc,
1755 };
1756
1757 /* spinlock */
1758 static struct omap_hwmod omap44xx_spinlock_hwmod = {
1759         .name           = "spinlock",
1760         .class          = &omap44xx_spinlock_hwmod_class,
1761         .clkdm_name     = "l4_cfg_clkdm",
1762         .prcm = {
1763                 .omap4 = {
1764                         .clkctrl_offs = OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET,
1765                         .context_offs = OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET,
1766                 },
1767         },
1768 };
1769
1770 /*
1771  * 'timer' class
1772  * general purpose timer module with accurate 1ms tick
1773  * This class contains several variants: ['timer_1ms', 'timer']
1774  */
1775
1776 static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = {
1777         .rev_offs       = 0x0000,
1778         .sysc_offs      = 0x0010,
1779         .syss_offs      = 0x0014,
1780         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1781                            SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
1782                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1783                            SYSS_HAS_RESET_STATUS),
1784         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1785         .sysc_fields    = &omap_hwmod_sysc_type1,
1786 };
1787
1788 static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = {
1789         .name   = "timer",
1790         .sysc   = &omap44xx_timer_1ms_sysc,
1791 };
1792
1793 static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = {
1794         .rev_offs       = 0x0000,
1795         .sysc_offs      = 0x0010,
1796         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1797                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1798         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1799                            SIDLE_SMART_WKUP),
1800         .sysc_fields    = &omap_hwmod_sysc_type2,
1801 };
1802
1803 static struct omap_hwmod_class omap44xx_timer_hwmod_class = {
1804         .name   = "timer",
1805         .sysc   = &omap44xx_timer_sysc,
1806 };
1807
1808 /* timer1 */
1809 static struct omap_hwmod omap44xx_timer1_hwmod = {
1810         .name           = "timer1",
1811         .class          = &omap44xx_timer_1ms_hwmod_class,
1812         .clkdm_name     = "l4_wkup_clkdm",
1813         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
1814         .main_clk       = "dmt1_clk_mux",
1815         .prcm = {
1816                 .omap4 = {
1817                         .clkctrl_offs = OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
1818                         .context_offs = OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET,
1819                         .modulemode   = MODULEMODE_SWCTRL,
1820                 },
1821         },
1822 };
1823
1824 /* timer2 */
1825 static struct omap_hwmod omap44xx_timer2_hwmod = {
1826         .name           = "timer2",
1827         .class          = &omap44xx_timer_1ms_hwmod_class,
1828         .clkdm_name     = "l4_per_clkdm",
1829         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
1830         .main_clk       = "cm2_dm2_mux",
1831         .prcm = {
1832                 .omap4 = {
1833                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET,
1834                         .context_offs = OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET,
1835                         .modulemode   = MODULEMODE_SWCTRL,
1836                 },
1837         },
1838 };
1839
1840 /* timer3 */
1841 static struct omap_hwmod omap44xx_timer3_hwmod = {
1842         .name           = "timer3",
1843         .class          = &omap44xx_timer_hwmod_class,
1844         .clkdm_name     = "l4_per_clkdm",
1845         .main_clk       = "cm2_dm3_mux",
1846         .prcm = {
1847                 .omap4 = {
1848                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET,
1849                         .context_offs = OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET,
1850                         .modulemode   = MODULEMODE_SWCTRL,
1851                 },
1852         },
1853 };
1854
1855 /* timer4 */
1856 static struct omap_hwmod omap44xx_timer4_hwmod = {
1857         .name           = "timer4",
1858         .class          = &omap44xx_timer_hwmod_class,
1859         .clkdm_name     = "l4_per_clkdm",
1860         .main_clk       = "cm2_dm4_mux",
1861         .prcm = {
1862                 .omap4 = {
1863                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET,
1864                         .context_offs = OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET,
1865                         .modulemode   = MODULEMODE_SWCTRL,
1866                 },
1867         },
1868 };
1869
1870 /* timer5 */
1871 static struct omap_hwmod omap44xx_timer5_hwmod = {
1872         .name           = "timer5",
1873         .class          = &omap44xx_timer_hwmod_class,
1874         .clkdm_name     = "abe_clkdm",
1875         .main_clk       = "timer5_sync_mux",
1876         .prcm = {
1877                 .omap4 = {
1878                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET,
1879                         .context_offs = OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET,
1880                         .modulemode   = MODULEMODE_SWCTRL,
1881                 },
1882         },
1883 };
1884
1885 /* timer6 */
1886 static struct omap_hwmod omap44xx_timer6_hwmod = {
1887         .name           = "timer6",
1888         .class          = &omap44xx_timer_hwmod_class,
1889         .clkdm_name     = "abe_clkdm",
1890         .main_clk       = "timer6_sync_mux",
1891         .prcm = {
1892                 .omap4 = {
1893                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET,
1894                         .context_offs = OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET,
1895                         .modulemode   = MODULEMODE_SWCTRL,
1896                 },
1897         },
1898 };
1899
1900 /* timer7 */
1901 static struct omap_hwmod omap44xx_timer7_hwmod = {
1902         .name           = "timer7",
1903         .class          = &omap44xx_timer_hwmod_class,
1904         .clkdm_name     = "abe_clkdm",
1905         .main_clk       = "timer7_sync_mux",
1906         .prcm = {
1907                 .omap4 = {
1908                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET,
1909                         .context_offs = OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET,
1910                         .modulemode   = MODULEMODE_SWCTRL,
1911                 },
1912         },
1913 };
1914
1915 /* timer8 */
1916 static struct omap_hwmod omap44xx_timer8_hwmod = {
1917         .name           = "timer8",
1918         .class          = &omap44xx_timer_hwmod_class,
1919         .clkdm_name     = "abe_clkdm",
1920         .main_clk       = "timer8_sync_mux",
1921         .prcm = {
1922                 .omap4 = {
1923                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET,
1924                         .context_offs = OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET,
1925                         .modulemode   = MODULEMODE_SWCTRL,
1926                 },
1927         },
1928 };
1929
1930 /* timer9 */
1931 static struct omap_hwmod omap44xx_timer9_hwmod = {
1932         .name           = "timer9",
1933         .class          = &omap44xx_timer_hwmod_class,
1934         .clkdm_name     = "l4_per_clkdm",
1935         .main_clk       = "cm2_dm9_mux",
1936         .prcm = {
1937                 .omap4 = {
1938                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET,
1939                         .context_offs = OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET,
1940                         .modulemode   = MODULEMODE_SWCTRL,
1941                 },
1942         },
1943 };
1944
1945 /* timer10 */
1946 static struct omap_hwmod omap44xx_timer10_hwmod = {
1947         .name           = "timer10",
1948         .class          = &omap44xx_timer_1ms_hwmod_class,
1949         .clkdm_name     = "l4_per_clkdm",
1950         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
1951         .main_clk       = "cm2_dm10_mux",
1952         .prcm = {
1953                 .omap4 = {
1954                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET,
1955                         .context_offs = OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET,
1956                         .modulemode   = MODULEMODE_SWCTRL,
1957                 },
1958         },
1959 };
1960
1961 /* timer11 */
1962 static struct omap_hwmod omap44xx_timer11_hwmod = {
1963         .name           = "timer11",
1964         .class          = &omap44xx_timer_hwmod_class,
1965         .clkdm_name     = "l4_per_clkdm",
1966         .main_clk       = "cm2_dm11_mux",
1967         .prcm = {
1968                 .omap4 = {
1969                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET,
1970                         .context_offs = OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET,
1971                         .modulemode   = MODULEMODE_SWCTRL,
1972                 },
1973         },
1974 };
1975
1976 /*
1977  * 'usb_host_fs' class
1978  * full-speed usb host controller
1979  */
1980
1981 /* The IP is not compliant to type1 / type2 scheme */
1982 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_fs_sysc = {
1983         .rev_offs       = 0x0000,
1984         .sysc_offs      = 0x0210,
1985         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
1986                            SYSC_HAS_SOFTRESET),
1987         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1988                            SIDLE_SMART_WKUP),
1989         .sysc_fields    = &omap_hwmod_sysc_type_usb_host_fs,
1990 };
1991
1992 static struct omap_hwmod_class omap44xx_usb_host_fs_hwmod_class = {
1993         .name   = "usb_host_fs",
1994         .sysc   = &omap44xx_usb_host_fs_sysc,
1995 };
1996
1997 /* usb_host_fs */
1998 static struct omap_hwmod omap44xx_usb_host_fs_hwmod = {
1999         .name           = "usb_host_fs",
2000         .class          = &omap44xx_usb_host_fs_hwmod_class,
2001         .clkdm_name     = "l3_init_clkdm",
2002         .main_clk       = "usb_host_fs_fck",
2003         .prcm = {
2004                 .omap4 = {
2005                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_FS_CLKCTRL_OFFSET,
2006                         .context_offs = OMAP4_RM_L3INIT_USB_HOST_FS_CONTEXT_OFFSET,
2007                         .modulemode   = MODULEMODE_SWCTRL,
2008                 },
2009         },
2010 };
2011
2012 /*
2013  * 'usb_host_hs' class
2014  * high-speed multi-port usb host controller
2015  */
2016
2017 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc = {
2018         .rev_offs       = 0x0000,
2019         .sysc_offs      = 0x0010,
2020         .syss_offs      = 0x0014,
2021         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
2022                            SYSC_HAS_SOFTRESET | SYSC_HAS_RESET_STATUS),
2023         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2024                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2025                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2026         .sysc_fields    = &omap_hwmod_sysc_type2,
2027 };
2028
2029 static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class = {
2030         .name   = "usb_host_hs",
2031         .sysc   = &omap44xx_usb_host_hs_sysc,
2032 };
2033
2034 /* usb_host_hs */
2035 static struct omap_hwmod omap44xx_usb_host_hs_hwmod = {
2036         .name           = "usb_host_hs",
2037         .class          = &omap44xx_usb_host_hs_hwmod_class,
2038         .clkdm_name     = "l3_init_clkdm",
2039         .main_clk       = "usb_host_hs_fck",
2040         .prcm = {
2041                 .omap4 = {
2042                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET,
2043                         .context_offs = OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET,
2044                         .modulemode   = MODULEMODE_SWCTRL,
2045                 },
2046         },
2047
2048         /*
2049          * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
2050          * id: i660
2051          *
2052          * Description:
2053          * In the following configuration :
2054          * - USBHOST module is set to smart-idle mode
2055          * - PRCM asserts idle_req to the USBHOST module ( This typically
2056          *   happens when the system is going to a low power mode : all ports
2057          *   have been suspended, the master part of the USBHOST module has
2058          *   entered the standby state, and SW has cut the functional clocks)
2059          * - an USBHOST interrupt occurs before the module is able to answer
2060          *   idle_ack, typically a remote wakeup IRQ.
2061          * Then the USB HOST module will enter a deadlock situation where it
2062          * is no more accessible nor functional.
2063          *
2064          * Workaround:
2065          * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
2066          */
2067
2068         /*
2069          * Errata: USB host EHCI may stall when entering smart-standby mode
2070          * Id: i571
2071          *
2072          * Description:
2073          * When the USBHOST module is set to smart-standby mode, and when it is
2074          * ready to enter the standby state (i.e. all ports are suspended and
2075          * all attached devices are in suspend mode), then it can wrongly assert
2076          * the Mstandby signal too early while there are still some residual OCP
2077          * transactions ongoing. If this condition occurs, the internal state
2078          * machine may go to an undefined state and the USB link may be stuck
2079          * upon the next resume.
2080          *
2081          * Workaround:
2082          * Don't use smart standby; use only force standby,
2083          * hence HWMOD_SWSUP_MSTANDBY
2084          */
2085
2086         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
2087 };
2088
2089 /*
2090  * 'usb_tll_hs' class
2091  * usb_tll_hs module is the adapter on the usb_host_hs ports
2092  */
2093
2094 static struct omap_hwmod_class_sysconfig omap44xx_usb_tll_hs_sysc = {
2095         .rev_offs       = 0x0000,
2096         .sysc_offs      = 0x0010,
2097         .syss_offs      = 0x0014,
2098         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2099                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
2100                            SYSC_HAS_AUTOIDLE),
2101         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2102         .sysc_fields    = &omap_hwmod_sysc_type1,
2103 };
2104
2105 static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class = {
2106         .name   = "usb_tll_hs",
2107         .sysc   = &omap44xx_usb_tll_hs_sysc,
2108 };
2109
2110 static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = {
2111         .name           = "usb_tll_hs",
2112         .class          = &omap44xx_usb_tll_hs_hwmod_class,
2113         .clkdm_name     = "l3_init_clkdm",
2114         .main_clk       = "usb_tll_hs_ick",
2115         .prcm = {
2116                 .omap4 = {
2117                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET,
2118                         .context_offs = OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET,
2119                         .modulemode   = MODULEMODE_HWCTRL,
2120                 },
2121         },
2122 };
2123
2124 /*
2125  * interfaces
2126  */
2127
2128 /* l3_main_1 -> dmm */
2129 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
2130         .master         = &omap44xx_l3_main_1_hwmod,
2131         .slave          = &omap44xx_dmm_hwmod,
2132         .clk            = "l3_div_ck",
2133         .user           = OCP_USER_SDMA,
2134 };
2135
2136 /* mpu -> dmm */
2137 static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
2138         .master         = &omap44xx_mpu_hwmod,
2139         .slave          = &omap44xx_dmm_hwmod,
2140         .clk            = "l3_div_ck",
2141         .user           = OCP_USER_MPU,
2142 };
2143
2144 /* iva -> l3_instr */
2145 static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
2146         .master         = &omap44xx_iva_hwmod,
2147         .slave          = &omap44xx_l3_instr_hwmod,
2148         .clk            = "l3_div_ck",
2149         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2150 };
2151
2152 /* l3_main_3 -> l3_instr */
2153 static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
2154         .master         = &omap44xx_l3_main_3_hwmod,
2155         .slave          = &omap44xx_l3_instr_hwmod,
2156         .clk            = "l3_div_ck",
2157         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2158 };
2159
2160 /* ocp_wp_noc -> l3_instr */
2161 static struct omap_hwmod_ocp_if omap44xx_ocp_wp_noc__l3_instr = {
2162         .master         = &omap44xx_ocp_wp_noc_hwmod,
2163         .slave          = &omap44xx_l3_instr_hwmod,
2164         .clk            = "l3_div_ck",
2165         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2166 };
2167
2168 /* dsp -> l3_main_1 */
2169 static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
2170         .master         = &omap44xx_dsp_hwmod,
2171         .slave          = &omap44xx_l3_main_1_hwmod,
2172         .clk            = "l3_div_ck",
2173         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2174 };
2175
2176 /* dss -> l3_main_1 */
2177 static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = {
2178         .master         = &omap44xx_dss_hwmod,
2179         .slave          = &omap44xx_l3_main_1_hwmod,
2180         .clk            = "l3_div_ck",
2181         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2182 };
2183
2184 /* l3_main_2 -> l3_main_1 */
2185 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
2186         .master         = &omap44xx_l3_main_2_hwmod,
2187         .slave          = &omap44xx_l3_main_1_hwmod,
2188         .clk            = "l3_div_ck",
2189         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2190 };
2191
2192 /* l4_cfg -> l3_main_1 */
2193 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
2194         .master         = &omap44xx_l4_cfg_hwmod,
2195         .slave          = &omap44xx_l3_main_1_hwmod,
2196         .clk            = "l4_div_ck",
2197         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2198 };
2199
2200 /* mpu -> l3_main_1 */
2201 static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
2202         .master         = &omap44xx_mpu_hwmod,
2203         .slave          = &omap44xx_l3_main_1_hwmod,
2204         .clk            = "l3_div_ck",
2205         .user           = OCP_USER_MPU,
2206 };
2207
2208 /* debugss -> l3_main_2 */
2209 static struct omap_hwmod_ocp_if omap44xx_debugss__l3_main_2 = {
2210         .master         = &omap44xx_debugss_hwmod,
2211         .slave          = &omap44xx_l3_main_2_hwmod,
2212         .clk            = "dbgclk_mux_ck",
2213         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2214 };
2215
2216 /* dma_system -> l3_main_2 */
2217 static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
2218         .master         = &omap44xx_dma_system_hwmod,
2219         .slave          = &omap44xx_l3_main_2_hwmod,
2220         .clk            = "l3_div_ck",
2221         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2222 };
2223
2224 /* fdif -> l3_main_2 */
2225 static struct omap_hwmod_ocp_if omap44xx_fdif__l3_main_2 = {
2226         .master         = &omap44xx_fdif_hwmod,
2227         .slave          = &omap44xx_l3_main_2_hwmod,
2228         .clk            = "l3_div_ck",
2229         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2230 };
2231
2232 /* hsi -> l3_main_2 */
2233 static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = {
2234         .master         = &omap44xx_hsi_hwmod,
2235         .slave          = &omap44xx_l3_main_2_hwmod,
2236         .clk            = "l3_div_ck",
2237         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2238 };
2239
2240 /* ipu -> l3_main_2 */
2241 static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = {
2242         .master         = &omap44xx_ipu_hwmod,
2243         .slave          = &omap44xx_l3_main_2_hwmod,
2244         .clk            = "l3_div_ck",
2245         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2246 };
2247
2248 /* iss -> l3_main_2 */
2249 static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = {
2250         .master         = &omap44xx_iss_hwmod,
2251         .slave          = &omap44xx_l3_main_2_hwmod,
2252         .clk            = "l3_div_ck",
2253         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2254 };
2255
2256 /* iva -> l3_main_2 */
2257 static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
2258         .master         = &omap44xx_iva_hwmod,
2259         .slave          = &omap44xx_l3_main_2_hwmod,
2260         .clk            = "l3_div_ck",
2261         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2262 };
2263
2264 /* l3_main_1 -> l3_main_2 */
2265 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
2266         .master         = &omap44xx_l3_main_1_hwmod,
2267         .slave          = &omap44xx_l3_main_2_hwmod,
2268         .clk            = "l3_div_ck",
2269         .user           = OCP_USER_MPU,
2270 };
2271
2272 /* l4_cfg -> l3_main_2 */
2273 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
2274         .master         = &omap44xx_l4_cfg_hwmod,
2275         .slave          = &omap44xx_l3_main_2_hwmod,
2276         .clk            = "l4_div_ck",
2277         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2278 };
2279
2280 /* usb_host_fs -> l3_main_2 */
2281 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_usb_host_fs__l3_main_2 = {
2282         .master         = &omap44xx_usb_host_fs_hwmod,
2283         .slave          = &omap44xx_l3_main_2_hwmod,
2284         .clk            = "l3_div_ck",
2285         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2286 };
2287
2288 /* usb_host_hs -> l3_main_2 */
2289 static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2 = {
2290         .master         = &omap44xx_usb_host_hs_hwmod,
2291         .slave          = &omap44xx_l3_main_2_hwmod,
2292         .clk            = "l3_div_ck",
2293         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2294 };
2295
2296 /* l3_main_1 -> l3_main_3 */
2297 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
2298         .master         = &omap44xx_l3_main_1_hwmod,
2299         .slave          = &omap44xx_l3_main_3_hwmod,
2300         .clk            = "l3_div_ck",
2301         .user           = OCP_USER_MPU,
2302 };
2303
2304 /* l3_main_2 -> l3_main_3 */
2305 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
2306         .master         = &omap44xx_l3_main_2_hwmod,
2307         .slave          = &omap44xx_l3_main_3_hwmod,
2308         .clk            = "l3_div_ck",
2309         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2310 };
2311
2312 /* l4_cfg -> l3_main_3 */
2313 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
2314         .master         = &omap44xx_l4_cfg_hwmod,
2315         .slave          = &omap44xx_l3_main_3_hwmod,
2316         .clk            = "l4_div_ck",
2317         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2318 };
2319
2320 /* aess -> l4_abe */
2321 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_aess__l4_abe = {
2322         .master         = &omap44xx_aess_hwmod,
2323         .slave          = &omap44xx_l4_abe_hwmod,
2324         .clk            = "ocp_abe_iclk",
2325         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2326 };
2327
2328 /* dsp -> l4_abe */
2329 static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
2330         .master         = &omap44xx_dsp_hwmod,
2331         .slave          = &omap44xx_l4_abe_hwmod,
2332         .clk            = "ocp_abe_iclk",
2333         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2334 };
2335
2336 /* l3_main_1 -> l4_abe */
2337 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
2338         .master         = &omap44xx_l3_main_1_hwmod,
2339         .slave          = &omap44xx_l4_abe_hwmod,
2340         .clk            = "l3_div_ck",
2341         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2342 };
2343
2344 /* mpu -> l4_abe */
2345 static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
2346         .master         = &omap44xx_mpu_hwmod,
2347         .slave          = &omap44xx_l4_abe_hwmod,
2348         .clk            = "ocp_abe_iclk",
2349         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2350 };
2351
2352 /* l3_main_1 -> l4_cfg */
2353 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
2354         .master         = &omap44xx_l3_main_1_hwmod,
2355         .slave          = &omap44xx_l4_cfg_hwmod,
2356         .clk            = "l3_div_ck",
2357         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2358 };
2359
2360 /* l3_main_2 -> l4_per */
2361 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
2362         .master         = &omap44xx_l3_main_2_hwmod,
2363         .slave          = &omap44xx_l4_per_hwmod,
2364         .clk            = "l3_div_ck",
2365         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2366 };
2367
2368 /* l4_cfg -> l4_wkup */
2369 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
2370         .master         = &omap44xx_l4_cfg_hwmod,
2371         .slave          = &omap44xx_l4_wkup_hwmod,
2372         .clk            = "l4_div_ck",
2373         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2374 };
2375
2376 /* mpu -> mpu_private */
2377 static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
2378         .master         = &omap44xx_mpu_hwmod,
2379         .slave          = &omap44xx_mpu_private_hwmod,
2380         .clk            = "l3_div_ck",
2381         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2382 };
2383
2384 /* l4_cfg -> ocp_wp_noc */
2385 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp_wp_noc = {
2386         .master         = &omap44xx_l4_cfg_hwmod,
2387         .slave          = &omap44xx_ocp_wp_noc_hwmod,
2388         .clk            = "l4_div_ck",
2389         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2390 };
2391
2392 /* l4_abe -> aess */
2393 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess = {
2394         .master         = &omap44xx_l4_abe_hwmod,
2395         .slave          = &omap44xx_aess_hwmod,
2396         .clk            = "ocp_abe_iclk",
2397         .user           = OCP_USER_MPU,
2398 };
2399
2400 /* l4_abe -> aess (dma) */
2401 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess_dma = {
2402         .master         = &omap44xx_l4_abe_hwmod,
2403         .slave          = &omap44xx_aess_hwmod,
2404         .clk            = "ocp_abe_iclk",
2405         .user           = OCP_USER_SDMA,
2406 };
2407
2408 /* l4_wkup -> counter_32k */
2409 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
2410         .master         = &omap44xx_l4_wkup_hwmod,
2411         .slave          = &omap44xx_counter_32k_hwmod,
2412         .clk            = "l4_wkup_clk_mux_ck",
2413         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2414 };
2415
2416 /* l4_cfg -> ctrl_module_core */
2417 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_core = {
2418         .master         = &omap44xx_l4_cfg_hwmod,
2419         .slave          = &omap44xx_ctrl_module_core_hwmod,
2420         .clk            = "l4_div_ck",
2421         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2422 };
2423
2424 /* l4_cfg -> ctrl_module_pad_core */
2425 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_pad_core = {
2426         .master         = &omap44xx_l4_cfg_hwmod,
2427         .slave          = &omap44xx_ctrl_module_pad_core_hwmod,
2428         .clk            = "l4_div_ck",
2429         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2430 };
2431
2432 /* l4_wkup -> ctrl_module_wkup */
2433 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_wkup = {
2434         .master         = &omap44xx_l4_wkup_hwmod,
2435         .slave          = &omap44xx_ctrl_module_wkup_hwmod,
2436         .clk            = "l4_wkup_clk_mux_ck",
2437         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2438 };
2439
2440 /* l4_wkup -> ctrl_module_pad_wkup */
2441 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_pad_wkup = {
2442         .master         = &omap44xx_l4_wkup_hwmod,
2443         .slave          = &omap44xx_ctrl_module_pad_wkup_hwmod,
2444         .clk            = "l4_wkup_clk_mux_ck",
2445         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2446 };
2447
2448 /* l3_instr -> debugss */
2449 static struct omap_hwmod_ocp_if omap44xx_l3_instr__debugss = {
2450         .master         = &omap44xx_l3_instr_hwmod,
2451         .slave          = &omap44xx_debugss_hwmod,
2452         .clk            = "l3_div_ck",
2453         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2454 };
2455
2456 /* l4_cfg -> dma_system */
2457 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
2458         .master         = &omap44xx_l4_cfg_hwmod,
2459         .slave          = &omap44xx_dma_system_hwmod,
2460         .clk            = "l4_div_ck",
2461         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2462 };
2463
2464 /* l4_abe -> dmic */
2465 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
2466         .master         = &omap44xx_l4_abe_hwmod,
2467         .slave          = &omap44xx_dmic_hwmod,
2468         .clk            = "ocp_abe_iclk",
2469         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2470 };
2471
2472 /* dsp -> iva */
2473 static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
2474         .master         = &omap44xx_dsp_hwmod,
2475         .slave          = &omap44xx_iva_hwmod,
2476         .clk            = "dpll_iva_m5x2_ck",
2477         .user           = OCP_USER_DSP,
2478 };
2479
2480 /* dsp -> sl2if */
2481 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_dsp__sl2if = {
2482         .master         = &omap44xx_dsp_hwmod,
2483         .slave          = &omap44xx_sl2if_hwmod,
2484         .clk            = "dpll_iva_m5x2_ck",
2485         .user           = OCP_USER_DSP,
2486 };
2487
2488 /* l4_cfg -> dsp */
2489 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
2490         .master         = &omap44xx_l4_cfg_hwmod,
2491         .slave          = &omap44xx_dsp_hwmod,
2492         .clk            = "l4_div_ck",
2493         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2494 };
2495
2496 /* l3_main_2 -> dss */
2497 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
2498         .master         = &omap44xx_l3_main_2_hwmod,
2499         .slave          = &omap44xx_dss_hwmod,
2500         .clk            = "l3_div_ck",
2501         .user           = OCP_USER_SDMA,
2502 };
2503
2504 /* l4_per -> dss */
2505 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
2506         .master         = &omap44xx_l4_per_hwmod,
2507         .slave          = &omap44xx_dss_hwmod,
2508         .clk            = "l4_div_ck",
2509         .user           = OCP_USER_MPU,
2510 };
2511
2512 /* l3_main_2 -> dss_dispc */
2513 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
2514         .master         = &omap44xx_l3_main_2_hwmod,
2515         .slave          = &omap44xx_dss_dispc_hwmod,
2516         .clk            = "l3_div_ck",
2517         .user           = OCP_USER_SDMA,
2518 };
2519
2520 /* l4_per -> dss_dispc */
2521 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
2522         .master         = &omap44xx_l4_per_hwmod,
2523         .slave          = &omap44xx_dss_dispc_hwmod,
2524         .clk            = "l4_div_ck",
2525         .user           = OCP_USER_MPU,
2526 };
2527
2528 /* l3_main_2 -> dss_dsi1 */
2529 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
2530         .master         = &omap44xx_l3_main_2_hwmod,
2531         .slave          = &omap44xx_dss_dsi1_hwmod,
2532         .clk            = "l3_div_ck",
2533         .user           = OCP_USER_SDMA,
2534 };
2535
2536 /* l4_per -> dss_dsi1 */
2537 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
2538         .master         = &omap44xx_l4_per_hwmod,
2539         .slave          = &omap44xx_dss_dsi1_hwmod,
2540         .clk            = "l4_div_ck",
2541         .user           = OCP_USER_MPU,
2542 };
2543
2544 /* l3_main_2 -> dss_dsi2 */
2545 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
2546         .master         = &omap44xx_l3_main_2_hwmod,
2547         .slave          = &omap44xx_dss_dsi2_hwmod,
2548         .clk            = "l3_div_ck",
2549         .user           = OCP_USER_SDMA,
2550 };
2551
2552 /* l4_per -> dss_dsi2 */
2553 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
2554         .master         = &omap44xx_l4_per_hwmod,
2555         .slave          = &omap44xx_dss_dsi2_hwmod,
2556         .clk            = "l4_div_ck",
2557         .user           = OCP_USER_MPU,
2558 };
2559
2560 /* l3_main_2 -> dss_hdmi */
2561 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
2562         .master         = &omap44xx_l3_main_2_hwmod,
2563         .slave          = &omap44xx_dss_hdmi_hwmod,
2564         .clk            = "l3_div_ck",
2565         .user           = OCP_USER_SDMA,
2566 };
2567
2568 /* l4_per -> dss_hdmi */
2569 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
2570         .master         = &omap44xx_l4_per_hwmod,
2571         .slave          = &omap44xx_dss_hdmi_hwmod,
2572         .clk            = "l4_div_ck",
2573         .user           = OCP_USER_MPU,
2574 };
2575
2576 /* l3_main_2 -> dss_rfbi */
2577 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
2578         .master         = &omap44xx_l3_main_2_hwmod,
2579         .slave          = &omap44xx_dss_rfbi_hwmod,
2580         .clk            = "l3_div_ck",
2581         .user           = OCP_USER_SDMA,
2582 };
2583
2584 /* l4_per -> dss_rfbi */
2585 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
2586         .master         = &omap44xx_l4_per_hwmod,
2587         .slave          = &omap44xx_dss_rfbi_hwmod,
2588         .clk            = "l4_div_ck",
2589         .user           = OCP_USER_MPU,
2590 };
2591
2592 /* l3_main_2 -> dss_venc */
2593 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
2594         .master         = &omap44xx_l3_main_2_hwmod,
2595         .slave          = &omap44xx_dss_venc_hwmod,
2596         .clk            = "l3_div_ck",
2597         .user           = OCP_USER_SDMA,
2598 };
2599
2600 /* l4_per -> dss_venc */
2601 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
2602         .master         = &omap44xx_l4_per_hwmod,
2603         .slave          = &omap44xx_dss_venc_hwmod,
2604         .clk            = "l4_div_ck",
2605         .user           = OCP_USER_MPU,
2606 };
2607
2608 /* l3_main_2 -> sham */
2609 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__sha0 = {
2610         .master         = &omap44xx_l3_main_2_hwmod,
2611         .slave          = &omap44xx_sha0_hwmod,
2612         .clk            = "l3_div_ck",
2613         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2614 };
2615
2616 /* l4_per -> elm */
2617 static struct omap_hwmod_ocp_if omap44xx_l4_per__elm = {
2618         .master         = &omap44xx_l4_per_hwmod,
2619         .slave          = &omap44xx_elm_hwmod,
2620         .clk            = "l4_div_ck",
2621         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2622 };
2623
2624 /* l4_cfg -> fdif */
2625 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__fdif = {
2626         .master         = &omap44xx_l4_cfg_hwmod,
2627         .slave          = &omap44xx_fdif_hwmod,
2628         .clk            = "l4_div_ck",
2629         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2630 };
2631
2632 /* l3_main_2 -> gpmc */
2633 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = {
2634         .master         = &omap44xx_l3_main_2_hwmod,
2635         .slave          = &omap44xx_gpmc_hwmod,
2636         .clk            = "l3_div_ck",
2637         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2638 };
2639
2640 /* l4_cfg -> hsi */
2641 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
2642         .master         = &omap44xx_l4_cfg_hwmod,
2643         .slave          = &omap44xx_hsi_hwmod,
2644         .clk            = "l4_div_ck",
2645         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2646 };
2647
2648 /* l3_main_2 -> ipu */
2649 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = {
2650         .master         = &omap44xx_l3_main_2_hwmod,
2651         .slave          = &omap44xx_ipu_hwmod,
2652         .clk            = "l3_div_ck",
2653         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2654 };
2655
2656 /* l3_main_2 -> iss */
2657 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
2658         .master         = &omap44xx_l3_main_2_hwmod,
2659         .slave          = &omap44xx_iss_hwmod,
2660         .clk            = "l3_div_ck",
2661         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2662 };
2663
2664 /* iva -> sl2if */
2665 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_iva__sl2if = {
2666         .master         = &omap44xx_iva_hwmod,
2667         .slave          = &omap44xx_sl2if_hwmod,
2668         .clk            = "dpll_iva_m5x2_ck",
2669         .user           = OCP_USER_IVA,
2670 };
2671
2672 /* l3_main_2 -> iva */
2673 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
2674         .master         = &omap44xx_l3_main_2_hwmod,
2675         .slave          = &omap44xx_iva_hwmod,
2676         .clk            = "l3_div_ck",
2677         .user           = OCP_USER_MPU,
2678 };
2679
2680 /* l4_wkup -> kbd */
2681 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
2682         .master         = &omap44xx_l4_wkup_hwmod,
2683         .slave          = &omap44xx_kbd_hwmod,
2684         .clk            = "l4_wkup_clk_mux_ck",
2685         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2686 };
2687
2688 /* l4_abe -> mcpdm */
2689 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
2690         .master         = &omap44xx_l4_abe_hwmod,
2691         .slave          = &omap44xx_mcpdm_hwmod,
2692         .clk            = "ocp_abe_iclk",
2693         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2694 };
2695
2696 /* l3_main_2 -> ocmc_ram */
2697 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ocmc_ram = {
2698         .master         = &omap44xx_l3_main_2_hwmod,
2699         .slave          = &omap44xx_ocmc_ram_hwmod,
2700         .clk            = "l3_div_ck",
2701         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2702 };
2703
2704 /* l4_cfg -> ocp2scp_usb_phy */
2705 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp2scp_usb_phy = {
2706         .master         = &omap44xx_l4_cfg_hwmod,
2707         .slave          = &omap44xx_ocp2scp_usb_phy_hwmod,
2708         .clk            = "l4_div_ck",
2709         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2710 };
2711
2712 /* mpu_private -> prcm_mpu */
2713 static struct omap_hwmod_ocp_if omap44xx_mpu_private__prcm_mpu = {
2714         .master         = &omap44xx_mpu_private_hwmod,
2715         .slave          = &omap44xx_prcm_mpu_hwmod,
2716         .clk            = "l3_div_ck",
2717         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2718 };
2719
2720 /* l4_wkup -> cm_core_aon */
2721 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__cm_core_aon = {
2722         .master         = &omap44xx_l4_wkup_hwmod,
2723         .slave          = &omap44xx_cm_core_aon_hwmod,
2724         .clk            = "l4_wkup_clk_mux_ck",
2725         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2726 };
2727
2728 /* l4_cfg -> cm_core */
2729 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__cm_core = {
2730         .master         = &omap44xx_l4_cfg_hwmod,
2731         .slave          = &omap44xx_cm_core_hwmod,
2732         .clk            = "l4_div_ck",
2733         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2734 };
2735
2736 /* l4_wkup -> prm */
2737 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__prm = {
2738         .master         = &omap44xx_l4_wkup_hwmod,
2739         .slave          = &omap44xx_prm_hwmod,
2740         .clk            = "l4_wkup_clk_mux_ck",
2741         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2742 };
2743
2744 /* l4_wkup -> scrm */
2745 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__scrm = {
2746         .master         = &omap44xx_l4_wkup_hwmod,
2747         .slave          = &omap44xx_scrm_hwmod,
2748         .clk            = "l4_wkup_clk_mux_ck",
2749         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2750 };
2751
2752 /* l3_main_2 -> sl2if */
2753 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l3_main_2__sl2if = {
2754         .master         = &omap44xx_l3_main_2_hwmod,
2755         .slave          = &omap44xx_sl2if_hwmod,
2756         .clk            = "l3_div_ck",
2757         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2758 };
2759
2760 /* l4_abe -> slimbus1 */
2761 static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1 = {
2762         .master         = &omap44xx_l4_abe_hwmod,
2763         .slave          = &omap44xx_slimbus1_hwmod,
2764         .clk            = "ocp_abe_iclk",
2765         .user           = OCP_USER_MPU,
2766 };
2767
2768 /* l4_abe -> slimbus1 (dma) */
2769 static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1_dma = {
2770         .master         = &omap44xx_l4_abe_hwmod,
2771         .slave          = &omap44xx_slimbus1_hwmod,
2772         .clk            = "ocp_abe_iclk",
2773         .user           = OCP_USER_SDMA,
2774 };
2775
2776 /* l4_per -> slimbus2 */
2777 static struct omap_hwmod_ocp_if omap44xx_l4_per__slimbus2 = {
2778         .master         = &omap44xx_l4_per_hwmod,
2779         .slave          = &omap44xx_slimbus2_hwmod,
2780         .clk            = "l4_div_ck",
2781         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2782 };
2783
2784 /* l4_cfg -> smartreflex_core */
2785 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
2786         .master         = &omap44xx_l4_cfg_hwmod,
2787         .slave          = &omap44xx_smartreflex_core_hwmod,
2788         .clk            = "l4_div_ck",
2789         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2790 };
2791
2792 /* l4_cfg -> smartreflex_iva */
2793 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
2794         .master         = &omap44xx_l4_cfg_hwmod,
2795         .slave          = &omap44xx_smartreflex_iva_hwmod,
2796         .clk            = "l4_div_ck",
2797         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2798 };
2799
2800 /* l4_cfg -> smartreflex_mpu */
2801 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
2802         .master         = &omap44xx_l4_cfg_hwmod,
2803         .slave          = &omap44xx_smartreflex_mpu_hwmod,
2804         .clk            = "l4_div_ck",
2805         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2806 };
2807
2808 /* l4_cfg -> spinlock */
2809 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
2810         .master         = &omap44xx_l4_cfg_hwmod,
2811         .slave          = &omap44xx_spinlock_hwmod,
2812         .clk            = "l4_div_ck",
2813         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2814 };
2815
2816 /* l4_wkup -> timer1 */
2817 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
2818         .master         = &omap44xx_l4_wkup_hwmod,
2819         .slave          = &omap44xx_timer1_hwmod,
2820         .clk            = "l4_wkup_clk_mux_ck",
2821         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2822 };
2823
2824 /* l4_per -> timer2 */
2825 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
2826         .master         = &omap44xx_l4_per_hwmod,
2827         .slave          = &omap44xx_timer2_hwmod,
2828         .clk            = "l4_div_ck",
2829         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2830 };
2831
2832 /* l4_per -> timer3 */
2833 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
2834         .master         = &omap44xx_l4_per_hwmod,
2835         .slave          = &omap44xx_timer3_hwmod,
2836         .clk            = "l4_div_ck",
2837         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2838 };
2839
2840 /* l4_per -> timer4 */
2841 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
2842         .master         = &omap44xx_l4_per_hwmod,
2843         .slave          = &omap44xx_timer4_hwmod,
2844         .clk            = "l4_div_ck",
2845         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2846 };
2847
2848 /* l4_abe -> timer5 */
2849 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
2850         .master         = &omap44xx_l4_abe_hwmod,
2851         .slave          = &omap44xx_timer5_hwmod,
2852         .clk            = "ocp_abe_iclk",
2853         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2854 };
2855
2856 /* l4_abe -> timer6 */
2857 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
2858         .master         = &omap44xx_l4_abe_hwmod,
2859         .slave          = &omap44xx_timer6_hwmod,
2860         .clk            = "ocp_abe_iclk",
2861         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2862 };
2863
2864 /* l4_abe -> timer7 */
2865 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
2866         .master         = &omap44xx_l4_abe_hwmod,
2867         .slave          = &omap44xx_timer7_hwmod,
2868         .clk            = "ocp_abe_iclk",
2869         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2870 };
2871
2872 /* l4_abe -> timer8 */
2873 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
2874         .master         = &omap44xx_l4_abe_hwmod,
2875         .slave          = &omap44xx_timer8_hwmod,
2876         .clk            = "ocp_abe_iclk",
2877         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2878 };
2879
2880 /* l4_per -> timer9 */
2881 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
2882         .master         = &omap44xx_l4_per_hwmod,
2883         .slave          = &omap44xx_timer9_hwmod,
2884         .clk            = "l4_div_ck",
2885         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2886 };
2887
2888 /* l4_per -> timer10 */
2889 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
2890         .master         = &omap44xx_l4_per_hwmod,
2891         .slave          = &omap44xx_timer10_hwmod,
2892         .clk            = "l4_div_ck",
2893         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2894 };
2895
2896 /* l4_per -> timer11 */
2897 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
2898         .master         = &omap44xx_l4_per_hwmod,
2899         .slave          = &omap44xx_timer11_hwmod,
2900         .clk            = "l4_div_ck",
2901         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2902 };
2903
2904 /* l4_cfg -> usb_host_fs */
2905 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_cfg__usb_host_fs = {
2906         .master         = &omap44xx_l4_cfg_hwmod,
2907         .slave          = &omap44xx_usb_host_fs_hwmod,
2908         .clk            = "l4_div_ck",
2909         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2910 };
2911
2912 /* l4_cfg -> usb_host_hs */
2913 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = {
2914         .master         = &omap44xx_l4_cfg_hwmod,
2915         .slave          = &omap44xx_usb_host_hs_hwmod,
2916         .clk            = "l4_div_ck",
2917         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2918 };
2919
2920 /* l4_cfg -> usb_tll_hs */
2921 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = {
2922         .master         = &omap44xx_l4_cfg_hwmod,
2923         .slave          = &omap44xx_usb_tll_hs_hwmod,
2924         .clk            = "l4_div_ck",
2925         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2926 };
2927
2928 /* mpu -> emif1 */
2929 static struct omap_hwmod_ocp_if omap44xx_mpu__emif1 = {
2930         .master         = &omap44xx_mpu_hwmod,
2931         .slave          = &omap44xx_emif1_hwmod,
2932         .clk            = "l3_div_ck",
2933         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2934 };
2935
2936 /* mpu -> emif2 */
2937 static struct omap_hwmod_ocp_if omap44xx_mpu__emif2 = {
2938         .master         = &omap44xx_mpu_hwmod,
2939         .slave          = &omap44xx_emif2_hwmod,
2940         .clk            = "l3_div_ck",
2941         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2942 };
2943
2944 static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
2945         &omap44xx_l3_main_1__dmm,
2946         &omap44xx_mpu__dmm,
2947         &omap44xx_iva__l3_instr,
2948         &omap44xx_l3_main_3__l3_instr,
2949         &omap44xx_ocp_wp_noc__l3_instr,
2950         &omap44xx_dsp__l3_main_1,
2951         &omap44xx_dss__l3_main_1,
2952         &omap44xx_l3_main_2__l3_main_1,
2953         &omap44xx_l4_cfg__l3_main_1,
2954         &omap44xx_mpu__l3_main_1,
2955         &omap44xx_debugss__l3_main_2,
2956         &omap44xx_dma_system__l3_main_2,
2957         &omap44xx_fdif__l3_main_2,
2958         &omap44xx_hsi__l3_main_2,
2959         &omap44xx_ipu__l3_main_2,
2960         &omap44xx_iss__l3_main_2,
2961         &omap44xx_iva__l3_main_2,
2962         &omap44xx_l3_main_1__l3_main_2,
2963         &omap44xx_l4_cfg__l3_main_2,
2964         /* &omap44xx_usb_host_fs__l3_main_2, */
2965         &omap44xx_usb_host_hs__l3_main_2,
2966         &omap44xx_l3_main_1__l3_main_3,
2967         &omap44xx_l3_main_2__l3_main_3,
2968         &omap44xx_l4_cfg__l3_main_3,
2969         &omap44xx_aess__l4_abe,
2970         &omap44xx_dsp__l4_abe,
2971         &omap44xx_l3_main_1__l4_abe,
2972         &omap44xx_mpu__l4_abe,
2973         &omap44xx_l3_main_1__l4_cfg,
2974         &omap44xx_l3_main_2__l4_per,
2975         &omap44xx_l4_cfg__l4_wkup,
2976         &omap44xx_mpu__mpu_private,
2977         &omap44xx_l4_cfg__ocp_wp_noc,
2978         &omap44xx_l4_abe__aess,
2979         &omap44xx_l4_abe__aess_dma,
2980         &omap44xx_l4_wkup__counter_32k,
2981         &omap44xx_l4_cfg__ctrl_module_core,
2982         &omap44xx_l4_cfg__ctrl_module_pad_core,
2983         &omap44xx_l4_wkup__ctrl_module_wkup,
2984         &omap44xx_l4_wkup__ctrl_module_pad_wkup,
2985         &omap44xx_l3_instr__debugss,
2986         &omap44xx_l4_cfg__dma_system,
2987         &omap44xx_l4_abe__dmic,
2988         &omap44xx_dsp__iva,
2989         /* &omap44xx_dsp__sl2if, */
2990         &omap44xx_l4_cfg__dsp,
2991         &omap44xx_l3_main_2__dss,
2992         &omap44xx_l4_per__dss,
2993         &omap44xx_l3_main_2__dss_dispc,
2994         &omap44xx_l4_per__dss_dispc,
2995         &omap44xx_l3_main_2__dss_dsi1,
2996         &omap44xx_l4_per__dss_dsi1,
2997         &omap44xx_l3_main_2__dss_dsi2,
2998         &omap44xx_l4_per__dss_dsi2,
2999         &omap44xx_l3_main_2__dss_hdmi,
3000         &omap44xx_l4_per__dss_hdmi,
3001         &omap44xx_l3_main_2__dss_rfbi,
3002         &omap44xx_l4_per__dss_rfbi,
3003         &omap44xx_l3_main_2__dss_venc,
3004         &omap44xx_l4_per__dss_venc,
3005         &omap44xx_l4_per__elm,
3006         &omap44xx_l4_cfg__fdif,
3007         &omap44xx_l3_main_2__gpmc,
3008         &omap44xx_l4_cfg__hsi,
3009         &omap44xx_l3_main_2__ipu,
3010         &omap44xx_l3_main_2__iss,
3011         /* &omap44xx_iva__sl2if, */
3012         &omap44xx_l3_main_2__iva,
3013         &omap44xx_l4_wkup__kbd,
3014         &omap44xx_l4_abe__mcpdm,
3015         &omap44xx_l3_main_2__mmu_ipu,
3016         &omap44xx_l4_cfg__mmu_dsp,
3017         &omap44xx_l3_main_2__ocmc_ram,
3018         &omap44xx_l4_cfg__ocp2scp_usb_phy,
3019         &omap44xx_mpu_private__prcm_mpu,
3020         &omap44xx_l4_wkup__cm_core_aon,
3021         &omap44xx_l4_cfg__cm_core,
3022         &omap44xx_l4_wkup__prm,
3023         &omap44xx_l4_wkup__scrm,
3024         /* &omap44xx_l3_main_2__sl2if, */
3025         &omap44xx_l4_abe__slimbus1,
3026         &omap44xx_l4_abe__slimbus1_dma,
3027         &omap44xx_l4_per__slimbus2,
3028         &omap44xx_l4_cfg__smartreflex_core,
3029         &omap44xx_l4_cfg__smartreflex_iva,
3030         &omap44xx_l4_cfg__smartreflex_mpu,
3031         &omap44xx_l4_cfg__spinlock,
3032         &omap44xx_l4_wkup__timer1,
3033         &omap44xx_l4_per__timer2,
3034         &omap44xx_l4_per__timer3,
3035         &omap44xx_l4_per__timer4,
3036         &omap44xx_l4_abe__timer5,
3037         &omap44xx_l4_abe__timer6,
3038         &omap44xx_l4_abe__timer7,
3039         &omap44xx_l4_abe__timer8,
3040         &omap44xx_l4_per__timer9,
3041         &omap44xx_l4_per__timer10,
3042         &omap44xx_l4_per__timer11,
3043         /* &omap44xx_l4_cfg__usb_host_fs, */
3044         &omap44xx_l4_cfg__usb_host_hs,
3045         &omap44xx_l4_cfg__usb_tll_hs,
3046         &omap44xx_mpu__emif1,
3047         &omap44xx_mpu__emif2,
3048         &omap44xx_l3_main_2__aes1,
3049         &omap44xx_l3_main_2__aes2,
3050         &omap44xx_l3_main_2__des,
3051         &omap44xx_l3_main_2__sha0,
3052         NULL,
3053 };
3054
3055 int __init omap44xx_hwmod_init(void)
3056 {
3057         omap_hwmod_init();
3058         return omap_hwmod_register_links(omap44xx_hwmod_ocp_ifs);
3059 }
3060