arch/arm/mach-omap2/omap_hwmod_44xx_data.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Hardware modules present on the OMAP44xx chips
   4  *
   5  * Copyright (C) 2009-2012 Texas Instruments, Inc.
   6  * Copyright (C) 2009-2010 Nokia Corporation
   7  *
   8  * Paul Walmsley
   9  * Benoit Cousson
  10  *
  11  * This file is automatically generated from the OMAP hardware databases.
  12  * We respectfully ask that any modifications to this file be coordinated
  13  * with the public linux-omap@vger.kernel.org mailing list and the
  14  * authors above to ensure that the autogeneration scripts are kept
  15  * up-to-date with the file contents.
  16  * Note that this file is currently not in sync with autogeneration scripts.
  17  * The above note to be removed, once it is synced up.
  18  */
  19
  20 #include <linux/io.h>
  21 #include <linux/power/smartreflex.h>
  22
  23 #include <linux/omap-dma.h>
  24
  25 #include "omap_hwmod.h"
  26 #include "omap_hwmod_common_data.h"
  27 #include "cm1_44xx.h"
  28 #include "cm2_44xx.h"
  29 #include "prm44xx.h"
  30 #include "prm-regbits-44xx.h"
  31
  32 /* Base offset for all OMAP4 interrupts external to MPUSS */
  33 #define OMAP44XX_IRQ_GIC_START  32
  34
  35 /* Base offset for all OMAP4 dma requests */
  36 #define OMAP44XX_DMA_REQ_START  1
  37
  38 /*
  39  * IP blocks
  40  */
  41
  42 /*
  43  * 'dmm' class
  44  * instance(s): dmm
  45  */
  46 static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
  47         .name   = "dmm",
  48 };
  49
  50 /* dmm */
  51 static struct omap_hwmod omap44xx_dmm_hwmod = {
  52         .name           = "dmm",
  53         .class          = &omap44xx_dmm_hwmod_class,
  54         .clkdm_name     = "l3_emif_clkdm",
  55         .prcm = {
  56                 .omap4 = {
  57                         .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET,
  58                         .context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET,
  59                 },
  60         },
  61 };
  62
  63 /*
  64  * 'l3' class
  65  * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
  66  */
  67 static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
  68         .name   = "l3",
  69 };
  70
  71 /* l3_instr */
  72 static struct omap_hwmod omap44xx_l3_instr_hwmod = {
  73         .name           = "l3_instr",
  74         .class          = &omap44xx_l3_hwmod_class,
  75         .clkdm_name     = "l3_instr_clkdm",
  76         .prcm = {
  77                 .omap4 = {
  78                         .clkctrl_offs = OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
  79                         .context_offs = OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
  80                         .modulemode   = MODULEMODE_HWCTRL,
  81                 },
  82         },
  83 };
  84
  85 /* l3_main_1 */
  86 static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
  87         .name           = "l3_main_1",
  88         .class          = &omap44xx_l3_hwmod_class,
  89         .clkdm_name     = "l3_1_clkdm",
  90         .prcm = {
  91                 .omap4 = {
  92                         .clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET,
  93                         .context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET,
  94                 },
  95         },
  96 };
  97
  98 /* l3_main_2 */
  99 static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
 100         .name           = "l3_main_2",
 101         .class          = &omap44xx_l3_hwmod_class,
 102         .clkdm_name     = "l3_2_clkdm",
 103         .prcm = {
 104                 .omap4 = {
 105                         .clkctrl_offs = OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET,
 106                         .context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET,
 107                 },
 108         },
 109 };
 110
 111 /* l3_main_3 */
 112 static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
 113         .name           = "l3_main_3",
 114         .class          = &omap44xx_l3_hwmod_class,
 115         .clkdm_name     = "l3_instr_clkdm",
 116         .prcm = {
 117                 .omap4 = {
 118                         .clkctrl_offs = OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET,
 119                         .context_offs = OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET,
 120                         .modulemode   = MODULEMODE_HWCTRL,
 121                 },
 122         },
 123 };
 124
 125 /*
 126  * 'l4' class
 127  * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
 128  */
 129 static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
 130         .name   = "l4",
 131 };
 132
 133 /* l4_abe */
 134 static struct omap_hwmod omap44xx_l4_abe_hwmod = {
 135         .name           = "l4_abe",
 136         .class          = &omap44xx_l4_hwmod_class,
 137         .clkdm_name     = "abe_clkdm",
 138         .prcm = {
 139                 .omap4 = {
 140                         .clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET,
 141                         .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
 142                         .lostcontext_mask = OMAP4430_LOSTMEM_AESSMEM_MASK,
 143                         .flags        = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 144                 },
 145         },
 146 };
 147
 148 /* l4_cfg */
 149 static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
 150         .name           = "l4_cfg",
 151         .class          = &omap44xx_l4_hwmod_class,
 152         .clkdm_name     = "l4_cfg_clkdm",
 153         .prcm = {
 154                 .omap4 = {
 155                         .clkctrl_offs = OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
 156                         .context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
 157                 },
 158         },
 159 };
 160
 161 /* l4_per */
 162 static struct omap_hwmod omap44xx_l4_per_hwmod = {
 163         .name           = "l4_per",
 164         .class          = &omap44xx_l4_hwmod_class,
 165         .clkdm_name     = "l4_per_clkdm",
 166         .prcm = {
 167                 .omap4 = {
 168                         .clkctrl_offs = OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET,
 169                         .context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET,
 170                 },
 171         },
 172 };
 173
 174 /* l4_wkup */
 175 static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
 176         .name           = "l4_wkup",
 177         .class          = &omap44xx_l4_hwmod_class,
 178         .clkdm_name     = "l4_wkup_clkdm",
 179         .prcm = {
 180                 .omap4 = {
 181                         .clkctrl_offs = OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
 182                         .context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET,
 183                 },
 184         },
 185 };
 186
 187 /*
 188  * 'mpu_bus' class
 189  * instance(s): mpu_private
 190  */
 191 static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
 192         .name   = "mpu_bus",
 193 };
 194
 195 /* mpu_private */
 196 static struct omap_hwmod omap44xx_mpu_private_hwmod = {
 197         .name           = "mpu_private",
 198         .class          = &omap44xx_mpu_bus_hwmod_class,
 199         .clkdm_name     = "mpuss_clkdm",
 200         .prcm = {
 201                 .omap4 = {
 202                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 203                 },
 204         },
 205 };
 206
 207 /*
 208  * 'ocp_wp_noc' class
 209  * instance(s): ocp_wp_noc
 210  */
 211 static struct omap_hwmod_class omap44xx_ocp_wp_noc_hwmod_class = {
 212         .name   = "ocp_wp_noc",
 213 };
 214
 215 /* ocp_wp_noc */
 216 static struct omap_hwmod omap44xx_ocp_wp_noc_hwmod = {
 217         .name           = "ocp_wp_noc",
 218         .class          = &omap44xx_ocp_wp_noc_hwmod_class,
 219         .clkdm_name     = "l3_instr_clkdm",
 220         .prcm = {
 221                 .omap4 = {
 222                         .clkctrl_offs = OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET,
 223                         .context_offs = OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET,
 224                         .modulemode   = MODULEMODE_HWCTRL,
 225                 },
 226         },
 227 };
 228
 229 /*
 230  * Modules omap_hwmod structures
 231  *
 232  * The following IPs are excluded for the moment because:
 233  * - They do not need an explicit SW control using omap_hwmod API.
 234  * - They still need to be validated with the driver
 235  *   properly adapted to omap_hwmod / omap_device
 236  *
 237  * usim
 238  */
 239
 240 /*
 241  * 'aess' class
 242  * audio engine sub system
 243  */
 244
 245 static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = {
 246         .rev_offs       = 0x0000,
 247         .sysc_offs      = 0x0010,
 248         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
 249         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 250                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART |
 251                            MSTANDBY_SMART_WKUP),
 252         .sysc_fields    = &omap_hwmod_sysc_type2,
 253 };
 254
 255 static struct omap_hwmod_class omap44xx_aess_hwmod_class = {
 256         .name   = "aess",
 257         .sysc   = &omap44xx_aess_sysc,
 258         .enable_preprogram = omap_hwmod_aess_preprogram,
 259 };
 260
 261 /* aess */
 262 static struct omap_hwmod omap44xx_aess_hwmod = {
 263         .name           = "aess",
 264         .class          = &omap44xx_aess_hwmod_class,
 265         .clkdm_name     = "abe_clkdm",
 266         .main_clk       = "aess_fclk",
 267         .prcm = {
 268                 .omap4 = {
 269                         .clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET,
 270                         .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
 271                         .lostcontext_mask = OMAP4430_LOSTCONTEXT_DFF_MASK,
 272                         .modulemode   = MODULEMODE_SWCTRL,
 273                 },
 274         },
 275 };
 276
 277 /*
 278  * 'counter' class
 279  * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
 280  */
 281
 282 static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = {
 283         .rev_offs       = 0x0000,
 284         .sysc_offs      = 0x0004,
 285         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 286         .idlemodes      = (SIDLE_FORCE | SIDLE_NO),
 287         .sysc_fields    = &omap_hwmod_sysc_type1,
 288 };
 289
 290 static struct omap_hwmod_class omap44xx_counter_hwmod_class = {
 291         .name   = "counter",
 292         .sysc   = &omap44xx_counter_sysc,
 293 };
 294
 295 /* counter_32k */
 296 static struct omap_hwmod omap44xx_counter_32k_hwmod = {
 297         .name           = "counter_32k",
 298         .class          = &omap44xx_counter_hwmod_class,
 299         .clkdm_name     = "l4_wkup_clkdm",
 300         .flags          = HWMOD_SWSUP_SIDLE,
 301         .main_clk       = "sys_32k_ck",
 302         .prcm = {
 303                 .omap4 = {
 304                         .clkctrl_offs = OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
 305                         .context_offs = OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET,
 306                 },
 307         },
 308 };
 309
 310 /*
 311  * 'ctrl_module' class
 312  * attila core control module + core pad control module + wkup pad control
 313  * module + attila wkup control module
 314  */
 315
 316 static struct omap_hwmod_class_sysconfig omap44xx_ctrl_module_sysc = {
 317         .rev_offs       = 0x0000,
 318         .sysc_offs      = 0x0010,
 319         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 320         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 321                            SIDLE_SMART_WKUP),
 322         .sysc_fields    = &omap_hwmod_sysc_type2,
 323 };
 324
 325 static struct omap_hwmod_class omap44xx_ctrl_module_hwmod_class = {
 326         .name   = "ctrl_module",
 327         .sysc   = &omap44xx_ctrl_module_sysc,
 328 };
 329
 330 /* ctrl_module_core */
 331 static struct omap_hwmod omap44xx_ctrl_module_core_hwmod = {
 332         .name           = "ctrl_module_core",
 333         .class          = &omap44xx_ctrl_module_hwmod_class,
 334         .clkdm_name     = "l4_cfg_clkdm",
 335         .prcm = {
 336                 .omap4 = {
 337                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 338                 },
 339         },
 340 };
 341
 342 /* ctrl_module_pad_core */
 343 static struct omap_hwmod omap44xx_ctrl_module_pad_core_hwmod = {
 344         .name           = "ctrl_module_pad_core",
 345         .class          = &omap44xx_ctrl_module_hwmod_class,
 346         .clkdm_name     = "l4_cfg_clkdm",
 347         .prcm = {
 348                 .omap4 = {
 349                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 350                 },
 351         },
 352 };
 353
 354 /* ctrl_module_wkup */
 355 static struct omap_hwmod omap44xx_ctrl_module_wkup_hwmod = {
 356         .name           = "ctrl_module_wkup",
 357         .class          = &omap44xx_ctrl_module_hwmod_class,
 358         .clkdm_name     = "l4_wkup_clkdm",
 359         .prcm = {
 360                 .omap4 = {
 361                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 362                 },
 363         },
 364 };
 365
 366 /* ctrl_module_pad_wkup */
 367 static struct omap_hwmod omap44xx_ctrl_module_pad_wkup_hwmod = {
 368         .name           = "ctrl_module_pad_wkup",
 369         .class          = &omap44xx_ctrl_module_hwmod_class,
 370         .clkdm_name     = "l4_wkup_clkdm",
 371         .prcm = {
 372                 .omap4 = {
 373                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 374                 },
 375         },
 376 };
 377
 378 /*
 379  * 'debugss' class
 380  * debug and emulation sub system
 381  */
 382
 383 static struct omap_hwmod_class omap44xx_debugss_hwmod_class = {
 384         .name   = "debugss",
 385 };
 386
 387 /* debugss */
 388 static struct omap_hwmod omap44xx_debugss_hwmod = {
 389         .name           = "debugss",
 390         .class          = &omap44xx_debugss_hwmod_class,
 391         .clkdm_name     = "emu_sys_clkdm",
 392         .main_clk       = "trace_clk_div_ck",
 393         .prcm = {
 394                 .omap4 = {
 395                         .clkctrl_offs = OMAP4_CM_EMU_DEBUGSS_CLKCTRL_OFFSET,
 396                         .context_offs = OMAP4_RM_EMU_DEBUGSS_CONTEXT_OFFSET,
 397                 },
 398         },
 399 };
 400
 401 /*
 402  * 'dma' class
 403  * dma controller for data exchange between memory to memory (i.e. internal or
 404  * external memory) and gp peripherals to memory or memory to gp peripherals
 405  */
 406
 407 static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = {
 408         .rev_offs       = 0x0000,
 409         .sysc_offs      = 0x002c,
 410         .syss_offs      = 0x0028,
 411         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 412                            SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
 413                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 414                            SYSS_HAS_RESET_STATUS),
 415         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 416                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 417         .sysc_fields    = &omap_hwmod_sysc_type1,
 418 };
 419
 420 static struct omap_hwmod_class omap44xx_dma_hwmod_class = {
 421         .name   = "dma",
 422         .sysc   = &omap44xx_dma_sysc,
 423 };
 424
 425 /* dma dev_attr */
 426 static struct omap_dma_dev_attr dma_dev_attr = {
 427         .dev_caps       = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
 428                           IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
 429         .lch_count      = 32,
 430 };
 431
 432 /* dma_system */
 433 static struct omap_hwmod omap44xx_dma_system_hwmod = {
 434         .name           = "dma_system",
 435         .class          = &omap44xx_dma_hwmod_class,
 436         .clkdm_name     = "l3_dma_clkdm",
 437         .main_clk       = "l3_div_ck",
 438         .prcm = {
 439                 .omap4 = {
 440                         .clkctrl_offs = OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET,
 441                         .context_offs = OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET,
 442                 },
 443         },
 444         .dev_attr       = &dma_dev_attr,
 445 };
 446
 447 /*
 448  * 'dmic' class
 449  * digital microphone controller
 450  */
 451
 452 static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = {
 453         .rev_offs       = 0x0000,
 454         .sysc_offs      = 0x0010,
 455         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
 456                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
 457         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 458                            SIDLE_SMART_WKUP),
 459         .sysc_fields    = &omap_hwmod_sysc_type2,
 460 };
 461
 462 static struct omap_hwmod_class omap44xx_dmic_hwmod_class = {
 463         .name   = "dmic",
 464         .sysc   = &omap44xx_dmic_sysc,
 465 };
 466
 467 /* dmic */
 468 static struct omap_hwmod omap44xx_dmic_hwmod = {
 469         .name           = "dmic",
 470         .class          = &omap44xx_dmic_hwmod_class,
 471         .clkdm_name     = "abe_clkdm",
 472         .main_clk       = "func_dmic_abe_gfclk",
 473         .prcm = {
 474                 .omap4 = {
 475                         .clkctrl_offs = OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET,
 476                         .context_offs = OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET,
 477                         .modulemode   = MODULEMODE_SWCTRL,
 478                 },
 479         },
 480 };
 481
 482 /*
 483  * 'dsp' class
 484  * dsp sub-system
 485  */
 486
 487 static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
 488         .name   = "dsp",
 489 };
 490
 491 /* dsp */
 492 static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
 493         { .name = "dsp", .rst_shift = 0 },
 494 };
 495
 496 static struct omap_hwmod omap44xx_dsp_hwmod = {
 497         .name           = "dsp",
 498         .class          = &omap44xx_dsp_hwmod_class,
 499         .clkdm_name     = "tesla_clkdm",
 500         .rst_lines      = omap44xx_dsp_resets,
 501         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_dsp_resets),
 502         .main_clk       = "dpll_iva_m4x2_ck",
 503         .prcm = {
 504                 .omap4 = {
 505                         .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
 506                         .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
 507                         .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
 508                         .modulemode   = MODULEMODE_HWCTRL,
 509                 },
 510         },
 511 };
 512
 513 /*
 514  * 'dss' class
 515  * display sub-system
 516  */
 517
 518 static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = {
 519         .rev_offs       = 0x0000,
 520         .syss_offs      = 0x0014,
 521         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 522 };
 523
 524 static struct omap_hwmod_class omap44xx_dss_hwmod_class = {
 525         .name   = "dss",
 526         .sysc   = &omap44xx_dss_sysc,
 527         .reset  = omap_dss_reset,
 528 };
 529
 530 /* dss */
 531 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
 532         { .role = "sys_clk", .clk = "dss_sys_clk" },
 533         { .role = "tv_clk", .clk = "dss_tv_clk" },
 534         { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
 535 };
 536
 537 static struct omap_hwmod omap44xx_dss_hwmod = {
 538         .name           = "dss_core",
 539         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 540         .class          = &omap44xx_dss_hwmod_class,
 541         .clkdm_name     = "l3_dss_clkdm",
 542         .main_clk       = "dss_dss_clk",
 543         .prcm = {
 544                 .omap4 = {
 545                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 546                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 547                         .modulemode   = MODULEMODE_SWCTRL,
 548                 },
 549         },
 550         .opt_clks       = dss_opt_clks,
 551         .opt_clks_cnt   = ARRAY_SIZE(dss_opt_clks),
 552 };
 553
 554 /*
 555  * 'dispc' class
 556  * display controller
 557  */
 558
 559 static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = {
 560         .rev_offs       = 0x0000,
 561         .sysc_offs      = 0x0010,
 562         .syss_offs      = 0x0014,
 563         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 564                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
 565                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 566                            SYSS_HAS_RESET_STATUS),
 567         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 568                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 569         .sysc_fields    = &omap_hwmod_sysc_type1,
 570 };
 571
 572 static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
 573         .name   = "dispc",
 574         .sysc   = &omap44xx_dispc_sysc,
 575 };
 576
 577 /* dss_dispc */
 578 static struct omap_dss_dispc_dev_attr omap44xx_dss_dispc_dev_attr = {
 579         .manager_count          = 3,
 580         .has_framedonetv_irq    = 1
 581 };
 582
 583 static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
 584         .name           = "dss_dispc",
 585         .class          = &omap44xx_dispc_hwmod_class,
 586         .clkdm_name     = "l3_dss_clkdm",
 587         .main_clk       = "dss_dss_clk",
 588         .prcm = {
 589                 .omap4 = {
 590                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 591                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 592                 },
 593         },
 594         .dev_attr       = &omap44xx_dss_dispc_dev_attr,
 595         .parent_hwmod   = &omap44xx_dss_hwmod,
 596 };
 597
 598 /*
 599  * 'dsi' class
 600  * display serial interface controller
 601  */
 602
 603 static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = {
 604         .rev_offs       = 0x0000,
 605         .sysc_offs      = 0x0010,
 606         .syss_offs      = 0x0014,
 607         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 608                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 609                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 610         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 611         .sysc_fields    = &omap_hwmod_sysc_type1,
 612 };
 613
 614 static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
 615         .name   = "dsi",
 616         .sysc   = &omap44xx_dsi_sysc,
 617 };
 618
 619 /* dss_dsi1 */
 620 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
 621         { .role = "sys_clk", .clk = "dss_sys_clk" },
 622 };
 623
 624 static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
 625         .name           = "dss_dsi1",
 626         .class          = &omap44xx_dsi_hwmod_class,
 627         .clkdm_name     = "l3_dss_clkdm",
 628         .main_clk       = "dss_dss_clk",
 629         .prcm = {
 630                 .omap4 = {
 631                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 632                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 633                 },
 634         },
 635         .opt_clks       = dss_dsi1_opt_clks,
 636         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi1_opt_clks),
 637         .parent_hwmod   = &omap44xx_dss_hwmod,
 638 };
 639
 640 /* dss_dsi2 */
 641 static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = {
 642         { .role = "sys_clk", .clk = "dss_sys_clk" },
 643 };
 644
 645 static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
 646         .name           = "dss_dsi2",
 647         .class          = &omap44xx_dsi_hwmod_class,
 648         .clkdm_name     = "l3_dss_clkdm",
 649         .main_clk       = "dss_dss_clk",
 650         .prcm = {
 651                 .omap4 = {
 652                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 653                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 654                 },
 655         },
 656         .opt_clks       = dss_dsi2_opt_clks,
 657         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi2_opt_clks),
 658         .parent_hwmod   = &omap44xx_dss_hwmod,
 659 };
 660
 661 /*
 662  * 'hdmi' class
 663  * hdmi controller
 664  */
 665
 666 static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = {
 667         .rev_offs       = 0x0000,
 668         .sysc_offs      = 0x0010,
 669         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
 670                            SYSC_HAS_SOFTRESET),
 671         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 672                            SIDLE_SMART_WKUP),
 673         .sysc_fields    = &omap_hwmod_sysc_type2,
 674 };
 675
 676 static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
 677         .name   = "hdmi",
 678         .sysc   = &omap44xx_hdmi_sysc,
 679 };
 680
 681 /* dss_hdmi */
 682 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
 683         { .role = "sys_clk", .clk = "dss_sys_clk" },
 684         { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
 685 };
 686
 687 static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
 688         .name           = "dss_hdmi",
 689         .class          = &omap44xx_hdmi_hwmod_class,
 690         .clkdm_name     = "l3_dss_clkdm",
 691         /*
 692          * HDMI audio requires to use no-idle mode. Hence,
 693          * set idle mode by software.
 694          */
 695         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_OPT_CLKS_NEEDED,
 696         .main_clk       = "dss_48mhz_clk",
 697         .prcm = {
 698                 .omap4 = {
 699                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 700                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 701                 },
 702         },
 703         .opt_clks       = dss_hdmi_opt_clks,
 704         .opt_clks_cnt   = ARRAY_SIZE(dss_hdmi_opt_clks),
 705         .parent_hwmod   = &omap44xx_dss_hwmod,
 706 };
 707
 708 /*
 709  * 'rfbi' class
 710  * remote frame buffer interface
 711  */
 712
 713 static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = {
 714         .rev_offs       = 0x0000,
 715         .sysc_offs      = 0x0010,
 716         .syss_offs      = 0x0014,
 717         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
 718                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 719         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 720         .sysc_fields    = &omap_hwmod_sysc_type1,
 721 };
 722
 723 static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
 724         .name   = "rfbi",
 725         .sysc   = &omap44xx_rfbi_sysc,
 726 };
 727
 728 /* dss_rfbi */
 729 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
 730         { .role = "ick", .clk = "l3_div_ck" },
 731 };
 732
 733 static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
 734         .name           = "dss_rfbi",
 735         .class          = &omap44xx_rfbi_hwmod_class,
 736         .clkdm_name     = "l3_dss_clkdm",
 737         .main_clk       = "dss_dss_clk",
 738         .prcm = {
 739                 .omap4 = {
 740                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 741                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 742                 },
 743         },
 744         .opt_clks       = dss_rfbi_opt_clks,
 745         .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
 746         .parent_hwmod   = &omap44xx_dss_hwmod,
 747 };
 748
 749 /*
 750  * 'venc' class
 751  * video encoder
 752  */
 753
 754 static struct omap_hwmod_class omap44xx_venc_hwmod_class = {
 755         .name   = "venc",
 756 };
 757
 758 /* dss_venc */
 759 static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = {
 760         { .role = "tv_clk", .clk = "dss_tv_clk" },
 761 };
 762
 763 static struct omap_hwmod omap44xx_dss_venc_hwmod = {
 764         .name           = "dss_venc",
 765         .class          = &omap44xx_venc_hwmod_class,
 766         .clkdm_name     = "l3_dss_clkdm",
 767         .main_clk       = "dss_tv_clk",
 768         .flags          = HWMOD_OPT_CLKS_NEEDED,
 769         .prcm = {
 770                 .omap4 = {
 771                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 772                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 773                 },
 774         },
 775         .parent_hwmod   = &omap44xx_dss_hwmod,
 776         .opt_clks       = dss_venc_opt_clks,
 777         .opt_clks_cnt   = ARRAY_SIZE(dss_venc_opt_clks),
 778 };
 779
 780 /* sha0 HIB2 (the 'P' (public) device) */
 781 static struct omap_hwmod_class_sysconfig omap44xx_sha0_sysc = {
 782         .rev_offs       = 0x100,
 783         .sysc_offs      = 0x110,
 784         .syss_offs      = 0x114,
 785         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 786 };
 787
 788 static struct omap_hwmod_class omap44xx_sha0_hwmod_class = {
 789         .name           = "sham",
 790         .sysc           = &omap44xx_sha0_sysc,
 791 };
 792
 793 struct omap_hwmod omap44xx_sha0_hwmod = {
 794         .name           = "sham",
 795         .class          = &omap44xx_sha0_hwmod_class,
 796         .clkdm_name     = "l4_secure_clkdm",
 797         .main_clk       = "l3_div_ck",
 798         .prcm           = {
 799                 .omap4 = {
 800                         .clkctrl_offs = OMAP4_CM_L4SEC_SHA2MD51_CLKCTRL_OFFSET,
 801                         .context_offs = OMAP4_RM_L4SEC_SHA2MD51_CONTEXT_OFFSET,
 802                         .modulemode   = MODULEMODE_SWCTRL,
 803                 },
 804         },
 805 };
 806
 807 /*
 808  * 'elm' class
 809  * bch error location module
 810  */
 811
 812 static struct omap_hwmod_class_sysconfig omap44xx_elm_sysc = {
 813         .rev_offs       = 0x0000,
 814         .sysc_offs      = 0x0010,
 815         .syss_offs      = 0x0014,
 816         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 817                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 818                            SYSS_HAS_RESET_STATUS),
 819         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 820         .sysc_fields    = &omap_hwmod_sysc_type1,
 821 };
 822
 823 static struct omap_hwmod_class omap44xx_elm_hwmod_class = {
 824         .name   = "elm",
 825         .sysc   = &omap44xx_elm_sysc,
 826 };
 827
 828 /* elm */
 829 static struct omap_hwmod omap44xx_elm_hwmod = {
 830         .name           = "elm",
 831         .class          = &omap44xx_elm_hwmod_class,
 832         .clkdm_name     = "l4_per_clkdm",
 833         .prcm = {
 834                 .omap4 = {
 835                         .clkctrl_offs = OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET,
 836                         .context_offs = OMAP4_RM_L4PER_ELM_CONTEXT_OFFSET,
 837                 },
 838         },
 839 };
 840
 841 /*
 842  * 'emif' class
 843  * external memory interface no1
 844  */
 845
 846 static struct omap_hwmod_class_sysconfig omap44xx_emif_sysc = {
 847         .rev_offs       = 0x0000,
 848 };
 849
 850 static struct omap_hwmod_class omap44xx_emif_hwmod_class = {
 851         .name   = "emif",
 852         .sysc   = &omap44xx_emif_sysc,
 853 };
 854
 855 /* emif1 */
 856 static struct omap_hwmod omap44xx_emif1_hwmod = {
 857         .name           = "emif1",
 858         .class          = &omap44xx_emif_hwmod_class,
 859         .clkdm_name     = "l3_emif_clkdm",
 860         .flags          = HWMOD_INIT_NO_IDLE,
 861         .main_clk       = "ddrphy_ck",
 862         .prcm = {
 863                 .omap4 = {
 864                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET,
 865                         .context_offs = OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET,
 866                         .modulemode   = MODULEMODE_HWCTRL,
 867                 },
 868         },
 869 };
 870
 871 /* emif2 */
 872 static struct omap_hwmod omap44xx_emif2_hwmod = {
 873         .name           = "emif2",
 874         .class          = &omap44xx_emif_hwmod_class,
 875         .clkdm_name     = "l3_emif_clkdm",
 876         .flags          = HWMOD_INIT_NO_IDLE,
 877         .main_clk       = "ddrphy_ck",
 878         .prcm = {
 879                 .omap4 = {
 880                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET,
 881                         .context_offs = OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET,
 882                         .modulemode   = MODULEMODE_HWCTRL,
 883                 },
 884         },
 885 };
 886
 887 /*
 888     Crypto modules AES0/1 belong to:
 889         PD_L4_PER power domain
 890         CD_L4_SEC clock domain
 891         On the L3, the AES modules are mapped to
 892         L3_CLK2: Peripherals and multimedia sub clock domain
 893 */
 894 static struct omap_hwmod_class_sysconfig omap44xx_aes_sysc = {
 895         .rev_offs       = 0x80,
 896         .sysc_offs      = 0x84,
 897         .syss_offs      = 0x88,
 898         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 899 };
 900
 901 static struct omap_hwmod_class omap44xx_aes_hwmod_class = {
 902         .name           = "aes",
 903         .sysc           = &omap44xx_aes_sysc,
 904 };
 905
 906 static struct omap_hwmod omap44xx_aes1_hwmod = {
 907         .name           = "aes1",
 908         .class          = &omap44xx_aes_hwmod_class,
 909         .clkdm_name     = "l4_secure_clkdm",
 910         .main_clk       = "l3_div_ck",
 911         .prcm           = {
 912                 .omap4  = {
 913                         .context_offs   = OMAP4_RM_L4SEC_AES1_CONTEXT_OFFSET,
 914                         .clkctrl_offs   = OMAP4_CM_L4SEC_AES1_CLKCTRL_OFFSET,
 915                         .modulemode     = MODULEMODE_SWCTRL,
 916                 },
 917         },
 918 };
 919
 920 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__aes1 = {
 921         .master         = &omap44xx_l4_per_hwmod,
 922         .slave          = &omap44xx_aes1_hwmod,
 923         .clk            = "l3_div_ck",
 924         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 925 };
 926
 927 static struct omap_hwmod omap44xx_aes2_hwmod = {
 928         .name           = "aes2",
 929         .class          = &omap44xx_aes_hwmod_class,
 930         .clkdm_name     = "l4_secure_clkdm",
 931         .main_clk       = "l3_div_ck",
 932         .prcm           = {
 933                 .omap4  = {
 934                         .context_offs   = OMAP4_RM_L4SEC_AES2_CONTEXT_OFFSET,
 935                         .clkctrl_offs   = OMAP4_CM_L4SEC_AES2_CLKCTRL_OFFSET,
 936                         .modulemode     = MODULEMODE_SWCTRL,
 937                 },
 938         },
 939 };
 940
 941 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__aes2 = {
 942         .master         = &omap44xx_l4_per_hwmod,
 943         .slave          = &omap44xx_aes2_hwmod,
 944         .clk            = "l3_div_ck",
 945         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 946 };
 947
 948 /*
 949  * 'des' class for DES3DES module
 950  */
 951 static struct omap_hwmod_class_sysconfig omap44xx_des_sysc = {
 952         .rev_offs       = 0x30,
 953         .sysc_offs      = 0x34,
 954         .syss_offs      = 0x38,
 955         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 956 };
 957
 958 static struct omap_hwmod_class omap44xx_des_hwmod_class = {
 959         .name           = "des",
 960         .sysc           = &omap44xx_des_sysc,
 961 };
 962
 963 static struct omap_hwmod omap44xx_des_hwmod = {
 964         .name           = "des",
 965         .class          = &omap44xx_des_hwmod_class,
 966         .clkdm_name     = "l4_secure_clkdm",
 967         .main_clk       = "l3_div_ck",
 968         .prcm           = {
 969                 .omap4  = {
 970                         .context_offs   = OMAP4_RM_L4SEC_DES3DES_CONTEXT_OFFSET,
 971                         .clkctrl_offs   = OMAP4_CM_L4SEC_DES3DES_CLKCTRL_OFFSET,
 972                         .modulemode     = MODULEMODE_SWCTRL,
 973                 },
 974         },
 975 };
 976
 977 struct omap_hwmod_ocp_if omap44xx_l3_main_2__des = {
 978         .master         = &omap44xx_l3_main_2_hwmod,
 979         .slave          = &omap44xx_des_hwmod,
 980         .clk            = "l3_div_ck",
 981         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 982 };
 983
 984 /*
 985  * 'fdif' class
 986  * face detection hw accelerator module
 987  */
 988
 989 static struct omap_hwmod_class_sysconfig omap44xx_fdif_sysc = {
 990         .rev_offs       = 0x0000,
 991         .sysc_offs      = 0x0010,
 992         /*
 993          * FDIF needs 100 OCP clk cycles delay after a softreset before
 994          * accessing sysconfig again.
 995          * The lowest frequency at the moment for L3 bus is 100 MHz, so
 996          * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
 997          *
 998          * TODO: Indicate errata when available.
 999          */
1000         .srst_udelay    = 2,
1001         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1002                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1003         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1004                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1005         .sysc_fields    = &omap_hwmod_sysc_type2,
1006 };
1007
1008 static struct omap_hwmod_class omap44xx_fdif_hwmod_class = {
1009         .name   = "fdif",
1010         .sysc   = &omap44xx_fdif_sysc,
1011 };
1012
1013 /* fdif */
1014 static struct omap_hwmod omap44xx_fdif_hwmod = {
1015         .name           = "fdif",
1016         .class          = &omap44xx_fdif_hwmod_class,
1017         .clkdm_name     = "iss_clkdm",
1018         .main_clk       = "fdif_fck",
1019         .prcm = {
1020                 .omap4 = {
1021                         .clkctrl_offs = OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET,
1022                         .context_offs = OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET,
1023                         .modulemode   = MODULEMODE_SWCTRL,
1024                 },
1025         },
1026 };
1027
1028 /*
1029  * 'gpmc' class
1030  * general purpose memory controller
1031  */
1032
1033 static struct omap_hwmod_class_sysconfig omap44xx_gpmc_sysc = {
1034         .rev_offs       = 0x0000,
1035         .sysc_offs      = 0x0010,
1036         .syss_offs      = 0x0014,
1037         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1038                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1039         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1040         .sysc_fields    = &omap_hwmod_sysc_type1,
1041 };
1042
1043 static struct omap_hwmod_class omap44xx_gpmc_hwmod_class = {
1044         .name   = "gpmc",
1045         .sysc   = &omap44xx_gpmc_sysc,
1046 };
1047
1048 /* gpmc */
1049 static struct omap_hwmod omap44xx_gpmc_hwmod = {
1050         .name           = "gpmc",
1051         .class          = &omap44xx_gpmc_hwmod_class,
1052         .clkdm_name     = "l3_2_clkdm",
1053         /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
1054         .flags          = DEBUG_OMAP_GPMC_HWMOD_FLAGS,
1055         .prcm = {
1056                 .omap4 = {
1057                         .clkctrl_offs = OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET,
1058                         .context_offs = OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET,
1059                         .modulemode   = MODULEMODE_HWCTRL,
1060                 },
1061         },
1062 };
1063
1064 /*
1065  * 'hdq1w' class
1066  * hdq / 1-wire serial interface controller
1067  */
1068
1069 static struct omap_hwmod_class_sysconfig omap44xx_hdq1w_sysc = {
1070         .rev_offs       = 0x0000,
1071         .sysc_offs      = 0x0014,
1072         .syss_offs      = 0x0018,
1073         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
1074                            SYSS_HAS_RESET_STATUS),
1075         .sysc_fields    = &omap_hwmod_sysc_type1,
1076 };
1077
1078 static struct omap_hwmod_class omap44xx_hdq1w_hwmod_class = {
1079         .name   = "hdq1w",
1080         .sysc   = &omap44xx_hdq1w_sysc,
1081 };
1082
1083 /* hdq1w */
1084 static struct omap_hwmod omap44xx_hdq1w_hwmod = {
1085         .name           = "hdq1w",
1086         .class          = &omap44xx_hdq1w_hwmod_class,
1087         .clkdm_name     = "l4_per_clkdm",
1088         .flags          = HWMOD_INIT_NO_RESET, /* XXX temporary */
1089         .main_clk       = "func_12m_fclk",
1090         .prcm = {
1091                 .omap4 = {
1092                         .clkctrl_offs = OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
1093                         .context_offs = OMAP4_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
1094                         .modulemode   = MODULEMODE_SWCTRL,
1095                 },
1096         },
1097 };
1098
1099 /*
1100  * 'hsi' class
1101  * mipi high-speed synchronous serial interface (multichannel and full-duplex
1102  * serial if)
1103  */
1104
1105 static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = {
1106         .rev_offs       = 0x0000,
1107         .sysc_offs      = 0x0010,
1108         .syss_offs      = 0x0014,
1109         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE |
1110                            SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
1111                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1112         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1113                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1114                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1115         .sysc_fields    = &omap_hwmod_sysc_type1,
1116 };
1117
1118 static struct omap_hwmod_class omap44xx_hsi_hwmod_class = {
1119         .name   = "hsi",
1120         .sysc   = &omap44xx_hsi_sysc,
1121 };
1122
1123 /* hsi */
1124 static struct omap_hwmod omap44xx_hsi_hwmod = {
1125         .name           = "hsi",
1126         .class          = &omap44xx_hsi_hwmod_class,
1127         .clkdm_name     = "l3_init_clkdm",
1128         .main_clk       = "hsi_fck",
1129         .prcm = {
1130                 .omap4 = {
1131                         .clkctrl_offs = OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET,
1132                         .context_offs = OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET,
1133                         .modulemode   = MODULEMODE_HWCTRL,
1134                 },
1135         },
1136 };
1137
1138 /*
1139  * 'ipu' class
1140  * imaging processor unit
1141  */
1142
1143 static struct omap_hwmod_class omap44xx_ipu_hwmod_class = {
1144         .name   = "ipu",
1145 };
1146
1147 /* ipu */
1148 static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
1149         { .name = "cpu0", .rst_shift = 0 },
1150         { .name = "cpu1", .rst_shift = 1 },
1151 };
1152
1153 static struct omap_hwmod omap44xx_ipu_hwmod = {
1154         .name           = "ipu",
1155         .class          = &omap44xx_ipu_hwmod_class,
1156         .clkdm_name     = "ducati_clkdm",
1157         .rst_lines      = omap44xx_ipu_resets,
1158         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_ipu_resets),
1159         .main_clk       = "ducati_clk_mux_ck",
1160         .prcm = {
1161                 .omap4 = {
1162                         .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
1163                         .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
1164                         .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
1165                         .modulemode   = MODULEMODE_HWCTRL,
1166                 },
1167         },
1168 };
1169
1170 /*
1171  * 'iss' class
1172  * external images sensor pixel data processor
1173  */
1174
1175 static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = {
1176         .rev_offs       = 0x0000,
1177         .sysc_offs      = 0x0010,
1178         /*
1179          * ISS needs 100 OCP clk cycles delay after a softreset before
1180          * accessing sysconfig again.
1181          * The lowest frequency at the moment for L3 bus is 100 MHz, so
1182          * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
1183          *
1184          * TODO: Indicate errata when available.
1185          */
1186         .srst_udelay    = 2,
1187         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1188                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1189         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1190                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1191                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1192         .sysc_fields    = &omap_hwmod_sysc_type2,
1193 };
1194
1195 static struct omap_hwmod_class omap44xx_iss_hwmod_class = {
1196         .name   = "iss",
1197         .sysc   = &omap44xx_iss_sysc,
1198 };
1199
1200 /* iss */
1201 static struct omap_hwmod_opt_clk iss_opt_clks[] = {
1202         { .role = "ctrlclk", .clk = "iss_ctrlclk" },
1203 };
1204
1205 static struct omap_hwmod omap44xx_iss_hwmod = {
1206         .name           = "iss",
1207         .class          = &omap44xx_iss_hwmod_class,
1208         .clkdm_name     = "iss_clkdm",
1209         .main_clk       = "ducati_clk_mux_ck",
1210         .prcm = {
1211                 .omap4 = {
1212                         .clkctrl_offs = OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET,
1213                         .context_offs = OMAP4_RM_CAM_ISS_CONTEXT_OFFSET,
1214                         .modulemode   = MODULEMODE_SWCTRL,
1215                 },
1216         },
1217         .opt_clks       = iss_opt_clks,
1218         .opt_clks_cnt   = ARRAY_SIZE(iss_opt_clks),
1219 };
1220
1221 /*
1222  * 'iva' class
1223  * multi-standard video encoder/decoder hardware accelerator
1224  */
1225
1226 static struct omap_hwmod_class omap44xx_iva_hwmod_class = {
1227         .name   = "iva",
1228 };
1229
1230 /* iva */
1231 static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
1232         { .name = "seq0", .rst_shift = 0 },
1233         { .name = "seq1", .rst_shift = 1 },
1234         { .name = "logic", .rst_shift = 2 },
1235 };
1236
1237 static struct omap_hwmod omap44xx_iva_hwmod = {
1238         .name           = "iva",
1239         .class          = &omap44xx_iva_hwmod_class,
1240         .clkdm_name     = "ivahd_clkdm",
1241         .rst_lines      = omap44xx_iva_resets,
1242         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_resets),
1243         .main_clk       = "dpll_iva_m5x2_ck",
1244         .prcm = {
1245                 .omap4 = {
1246                         .clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET,
1247                         .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
1248                         .context_offs = OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET,
1249                         .modulemode   = MODULEMODE_HWCTRL,
1250                 },
1251         },
1252 };
1253
1254 /*
1255  * 'kbd' class
1256  * keyboard controller
1257  */
1258
1259 static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = {
1260         .rev_offs       = 0x0000,
1261         .sysc_offs      = 0x0010,
1262         .syss_offs      = 0x0014,
1263         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1264                            SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
1265                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1266                            SYSS_HAS_RESET_STATUS),
1267         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1268         .sysc_fields    = &omap_hwmod_sysc_type1,
1269 };
1270
1271 static struct omap_hwmod_class omap44xx_kbd_hwmod_class = {
1272         .name   = "kbd",
1273         .sysc   = &omap44xx_kbd_sysc,
1274 };
1275
1276 /* kbd */
1277 static struct omap_hwmod omap44xx_kbd_hwmod = {
1278         .name           = "kbd",
1279         .class          = &omap44xx_kbd_hwmod_class,
1280         .clkdm_name     = "l4_wkup_clkdm",
1281         .main_clk       = "sys_32k_ck",
1282         .prcm = {
1283                 .omap4 = {
1284                         .clkctrl_offs = OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET,
1285                         .context_offs = OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET,
1286                         .modulemode   = MODULEMODE_SWCTRL,
1287                 },
1288         },
1289 };
1290
1291
1292 /*
1293  * 'mcasp' class
1294  * multi-channel audio serial port controller
1295  */
1296
1297 /* The IP is not compliant to type1 / type2 scheme */
1298 static struct omap_hwmod_class_sysconfig omap44xx_mcasp_sysc = {
1299         .rev_offs       = 0,
1300         .sysc_offs      = 0x0004,
1301         .sysc_flags     = SYSC_HAS_SIDLEMODE,
1302         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1303                            SIDLE_SMART_WKUP),
1304         .sysc_fields    = &omap_hwmod_sysc_type_mcasp,
1305 };
1306
1307 static struct omap_hwmod_class omap44xx_mcasp_hwmod_class = {
1308         .name   = "mcasp",
1309         .sysc   = &omap44xx_mcasp_sysc,
1310 };
1311
1312 /* mcasp */
1313 static struct omap_hwmod omap44xx_mcasp_hwmod = {
1314         .name           = "mcasp",
1315         .class          = &omap44xx_mcasp_hwmod_class,
1316         .clkdm_name     = "abe_clkdm",
1317         .main_clk       = "func_mcasp_abe_gfclk",
1318         .prcm = {
1319                 .omap4 = {
1320                         .clkctrl_offs = OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET,
1321                         .context_offs = OMAP4_RM_ABE_MCASP_CONTEXT_OFFSET,
1322                         .modulemode   = MODULEMODE_SWCTRL,
1323                 },
1324         },
1325 };
1326
1327 /*
1328  * 'mcpdm' class
1329  * multi channel pdm controller (proprietary interface with phoenix power
1330  * ic)
1331  */
1332
1333 static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc = {
1334         .rev_offs       = 0x0000,
1335         .sysc_offs      = 0x0010,
1336         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1337                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1338         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1339                            SIDLE_SMART_WKUP),
1340         .sysc_fields    = &omap_hwmod_sysc_type2,
1341 };
1342
1343 static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = {
1344         .name   = "mcpdm",
1345         .sysc   = &omap44xx_mcpdm_sysc,
1346 };
1347
1348 /* mcpdm */
1349 static struct omap_hwmod omap44xx_mcpdm_hwmod = {
1350         .name           = "mcpdm",
1351         .class          = &omap44xx_mcpdm_hwmod_class,
1352         .clkdm_name     = "abe_clkdm",
1353         /*
1354          * It's suspected that the McPDM requires an off-chip main
1355          * functional clock, controlled via I2C.  This IP block is
1356          * currently reset very early during boot, before I2C is
1357          * available, so it doesn't seem that we have any choice in
1358          * the kernel other than to avoid resetting it.
1359          *
1360          * Also, McPDM needs to be configured to NO_IDLE mode when it
1361          * is in used otherwise vital clocks will be gated which
1362          * results 'slow motion' audio playback.
1363          */
1364         .flags          = HWMOD_EXT_OPT_MAIN_CLK | HWMOD_SWSUP_SIDLE,
1365         .main_clk       = "pad_clks_ck",
1366         .prcm = {
1367                 .omap4 = {
1368                         .clkctrl_offs = OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET,
1369                         .context_offs = OMAP4_RM_ABE_PDM_CONTEXT_OFFSET,
1370                         .modulemode   = MODULEMODE_SWCTRL,
1371                 },
1372         },
1373 };
1374
1375 /*
1376  * 'mmu' class
1377  * The memory management unit performs virtual to physical address translation
1378  * for its requestors.
1379  */
1380
1381 static struct omap_hwmod_class_sysconfig mmu_sysc = {
1382         .rev_offs       = 0x000,
1383         .sysc_offs      = 0x010,
1384         .syss_offs      = 0x014,
1385         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1386                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1387         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1388         .sysc_fields    = &omap_hwmod_sysc_type1,
1389 };
1390
1391 static struct omap_hwmod_class omap44xx_mmu_hwmod_class = {
1392         .name = "mmu",
1393         .sysc = &mmu_sysc,
1394 };
1395
1396 /* mmu ipu */
1397
1398 static struct omap_hwmod omap44xx_mmu_ipu_hwmod;
1399 static struct omap_hwmod_rst_info omap44xx_mmu_ipu_resets[] = {
1400         { .name = "mmu_cache", .rst_shift = 2 },
1401 };
1402
1403 /* l3_main_2 -> mmu_ipu */
1404 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__mmu_ipu = {
1405         .master         = &omap44xx_l3_main_2_hwmod,
1406         .slave          = &omap44xx_mmu_ipu_hwmod,
1407         .clk            = "l3_div_ck",
1408         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1409 };
1410
1411 static struct omap_hwmod omap44xx_mmu_ipu_hwmod = {
1412         .name           = "mmu_ipu",
1413         .class          = &omap44xx_mmu_hwmod_class,
1414         .clkdm_name     = "ducati_clkdm",
1415         .rst_lines      = omap44xx_mmu_ipu_resets,
1416         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_mmu_ipu_resets),
1417         .main_clk       = "ducati_clk_mux_ck",
1418         .prcm = {
1419                 .omap4 = {
1420                         .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
1421                         .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
1422                         .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
1423                         .modulemode   = MODULEMODE_HWCTRL,
1424                 },
1425         },
1426 };
1427
1428 /* mmu dsp */
1429
1430 static struct omap_hwmod omap44xx_mmu_dsp_hwmod;
1431 static struct omap_hwmod_rst_info omap44xx_mmu_dsp_resets[] = {
1432         { .name = "mmu_cache", .rst_shift = 1 },
1433 };
1434
1435 /* l4_cfg -> dsp */
1436 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mmu_dsp = {
1437         .master         = &omap44xx_l4_cfg_hwmod,
1438         .slave          = &omap44xx_mmu_dsp_hwmod,
1439         .clk            = "l4_div_ck",
1440         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1441 };
1442
1443 static struct omap_hwmod omap44xx_mmu_dsp_hwmod = {
1444         .name           = "mmu_dsp",
1445         .class          = &omap44xx_mmu_hwmod_class,
1446         .clkdm_name     = "tesla_clkdm",
1447         .rst_lines      = omap44xx_mmu_dsp_resets,
1448         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_mmu_dsp_resets),
1449         .main_clk       = "dpll_iva_m4x2_ck",
1450         .prcm = {
1451                 .omap4 = {
1452                         .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
1453                         .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
1454                         .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
1455                         .modulemode   = MODULEMODE_HWCTRL,
1456                 },
1457         },
1458 };
1459
1460 /*
1461  * 'mpu' class
1462  * mpu sub-system
1463  */
1464
1465 static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
1466         .name   = "mpu",
1467 };
1468
1469 /* mpu */
1470 static struct omap_hwmod omap44xx_mpu_hwmod = {
1471         .name           = "mpu",
1472         .class          = &omap44xx_mpu_hwmod_class,
1473         .clkdm_name     = "mpuss_clkdm",
1474         .flags          = HWMOD_INIT_NO_IDLE,
1475         .main_clk       = "dpll_mpu_m2_ck",
1476         .prcm = {
1477                 .omap4 = {
1478                         .clkctrl_offs = OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET,
1479                         .context_offs = OMAP4_RM_MPU_MPU_CONTEXT_OFFSET,
1480                 },
1481         },
1482 };
1483
1484 /*
1485  * 'ocmc_ram' class
1486  * top-level core on-chip ram
1487  */
1488
1489 static struct omap_hwmod_class omap44xx_ocmc_ram_hwmod_class = {
1490         .name   = "ocmc_ram",
1491 };
1492
1493 /* ocmc_ram */
1494 static struct omap_hwmod omap44xx_ocmc_ram_hwmod = {
1495         .name           = "ocmc_ram",
1496         .class          = &omap44xx_ocmc_ram_hwmod_class,
1497         .clkdm_name     = "l3_2_clkdm",
1498         .prcm = {
1499                 .omap4 = {
1500                         .clkctrl_offs = OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET,
1501                         .context_offs = OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET,
1502                 },
1503         },
1504 };
1505
1506 /*
1507  * 'ocp2scp' class
1508  * bridge to transform ocp interface protocol to scp (serial control port)
1509  * protocol
1510  */
1511
1512 static struct omap_hwmod_class_sysconfig omap44xx_ocp2scp_sysc = {
1513         .rev_offs       = 0x0000,
1514         .sysc_offs      = 0x0010,
1515         .syss_offs      = 0x0014,
1516         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1517                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1518         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1519         .sysc_fields    = &omap_hwmod_sysc_type1,
1520 };
1521
1522 static struct omap_hwmod_class omap44xx_ocp2scp_hwmod_class = {
1523         .name   = "ocp2scp",
1524         .sysc   = &omap44xx_ocp2scp_sysc,
1525 };
1526
1527 /* ocp2scp_usb_phy */
1528 static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = {
1529         .name           = "ocp2scp_usb_phy",
1530         .class          = &omap44xx_ocp2scp_hwmod_class,
1531         .clkdm_name     = "l3_init_clkdm",
1532         /*
1533          * ocp2scp_usb_phy_phy_48m is provided by the OMAP4 PRCM IP
1534          * block as an "optional clock," and normally should never be
1535          * specified as the main_clk for an OMAP IP block.  However it
1536          * turns out that this clock is actually the main clock for
1537          * the ocp2scp_usb_phy IP block:
1538          * http://lists.infradead.org/pipermail/linux-arm-kernel/2012-September/119943.html
1539          * So listing ocp2scp_usb_phy_phy_48m as a main_clk here seems
1540          * to be the best workaround.
1541          */
1542         .main_clk       = "ocp2scp_usb_phy_phy_48m",
1543         .prcm = {
1544                 .omap4 = {
1545                         .clkctrl_offs = OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET,
1546                         .context_offs = OMAP4_RM_L3INIT_USBPHYOCP2SCP_CONTEXT_OFFSET,
1547                         .modulemode   = MODULEMODE_HWCTRL,
1548                 },
1549         },
1550 };
1551
1552 /*
1553  * 'prcm' class
1554  * power and reset manager (part of the prcm infrastructure) + clock manager 2
1555  * + clock manager 1 (in always on power domain) + local prm in mpu
1556  */
1557
1558 static struct omap_hwmod_class omap44xx_prcm_hwmod_class = {
1559         .name   = "prcm",
1560 };
1561
1562 /* prcm_mpu */
1563 static struct omap_hwmod omap44xx_prcm_mpu_hwmod = {
1564         .name           = "prcm_mpu",
1565         .class          = &omap44xx_prcm_hwmod_class,
1566         .clkdm_name     = "l4_wkup_clkdm",
1567         .flags          = HWMOD_NO_IDLEST,
1568         .prcm = {
1569                 .omap4 = {
1570                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
1571                 },
1572         },
1573 };
1574
1575 /* cm_core_aon */
1576 static struct omap_hwmod omap44xx_cm_core_aon_hwmod = {
1577         .name           = "cm_core_aon",
1578         .class          = &omap44xx_prcm_hwmod_class,
1579         .flags          = HWMOD_NO_IDLEST,
1580         .prcm = {
1581                 .omap4 = {
1582                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
1583                 },
1584         },
1585 };
1586
1587 /* cm_core */
1588 static struct omap_hwmod omap44xx_cm_core_hwmod = {
1589         .name           = "cm_core",
1590         .class          = &omap44xx_prcm_hwmod_class,
1591         .flags          = HWMOD_NO_IDLEST,
1592         .prcm = {
1593                 .omap4 = {
1594                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
1595                 },
1596         },
1597 };
1598
1599 /* prm */
1600 static struct omap_hwmod_rst_info omap44xx_prm_resets[] = {
1601         { .name = "rst_global_warm_sw", .rst_shift = 0 },
1602         { .name = "rst_global_cold_sw", .rst_shift = 1 },
1603 };
1604
1605 static struct omap_hwmod omap44xx_prm_hwmod = {
1606         .name           = "prm",
1607         .class          = &omap44xx_prcm_hwmod_class,
1608         .rst_lines      = omap44xx_prm_resets,
1609         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_prm_resets),
1610 };
1611
1612 /*
1613  * 'scrm' class
1614  * system clock and reset manager
1615  */
1616
1617 static struct omap_hwmod_class omap44xx_scrm_hwmod_class = {
1618         .name   = "scrm",
1619 };
1620
1621 /* scrm */
1622 static struct omap_hwmod omap44xx_scrm_hwmod = {
1623         .name           = "scrm",
1624         .class          = &omap44xx_scrm_hwmod_class,
1625         .clkdm_name     = "l4_wkup_clkdm",
1626         .prcm = {
1627                 .omap4 = {
1628                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
1629                 },
1630         },
1631 };
1632
1633 /*
1634  * 'sl2if' class
1635  * shared level 2 memory interface
1636  */
1637
1638 static struct omap_hwmod_class omap44xx_sl2if_hwmod_class = {
1639         .name   = "sl2if",
1640 };
1641
1642 /* sl2if */
1643 static struct omap_hwmod omap44xx_sl2if_hwmod = {
1644         .name           = "sl2if",
1645         .class          = &omap44xx_sl2if_hwmod_class,
1646         .clkdm_name     = "ivahd_clkdm",
1647         .prcm = {
1648                 .omap4 = {
1649                         .clkctrl_offs = OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET,
1650                         .context_offs = OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET,
1651                         .modulemode   = MODULEMODE_HWCTRL,
1652                 },
1653         },
1654 };
1655
1656 /*
1657  * 'slimbus' class
1658  * bidirectional, multi-drop, multi-channel two-line serial interface between
1659  * the device and external components
1660  */
1661
1662 static struct omap_hwmod_class_sysconfig omap44xx_slimbus_sysc = {
1663         .rev_offs       = 0x0000,
1664         .sysc_offs      = 0x0010,
1665         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1666                            SYSC_HAS_SOFTRESET),
1667         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1668                            SIDLE_SMART_WKUP),
1669         .sysc_fields    = &omap_hwmod_sysc_type2,
1670 };
1671
1672 static struct omap_hwmod_class omap44xx_slimbus_hwmod_class = {
1673         .name   = "slimbus",
1674         .sysc   = &omap44xx_slimbus_sysc,
1675 };
1676
1677 /* slimbus1 */
1678 static struct omap_hwmod_opt_clk slimbus1_opt_clks[] = {
1679         { .role = "fclk_1", .clk = "slimbus1_fclk_1" },
1680         { .role = "fclk_0", .clk = "slimbus1_fclk_0" },
1681         { .role = "fclk_2", .clk = "slimbus1_fclk_2" },
1682         { .role = "slimbus_clk", .clk = "slimbus1_slimbus_clk" },
1683 };
1684
1685 static struct omap_hwmod omap44xx_slimbus1_hwmod = {
1686         .name           = "slimbus1",
1687         .class          = &omap44xx_slimbus_hwmod_class,
1688         .clkdm_name     = "abe_clkdm",
1689         .prcm = {
1690                 .omap4 = {
1691                         .clkctrl_offs = OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET,
1692                         .context_offs = OMAP4_RM_ABE_SLIMBUS_CONTEXT_OFFSET,
1693                         .modulemode   = MODULEMODE_SWCTRL,
1694                 },
1695         },
1696         .opt_clks       = slimbus1_opt_clks,
1697         .opt_clks_cnt   = ARRAY_SIZE(slimbus1_opt_clks),
1698 };
1699
1700 /* slimbus2 */
1701 static struct omap_hwmod_opt_clk slimbus2_opt_clks[] = {
1702         { .role = "fclk_1", .clk = "slimbus2_fclk_1" },
1703         { .role = "fclk_0", .clk = "slimbus2_fclk_0" },
1704         { .role = "slimbus_clk", .clk = "slimbus2_slimbus_clk" },
1705 };
1706
1707 static struct omap_hwmod omap44xx_slimbus2_hwmod = {
1708         .name           = "slimbus2",
1709         .class          = &omap44xx_slimbus_hwmod_class,
1710         .clkdm_name     = "l4_per_clkdm",
1711         .prcm = {
1712                 .omap4 = {
1713                         .clkctrl_offs = OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET,
1714                         .context_offs = OMAP4_RM_L4PER_SLIMBUS2_CONTEXT_OFFSET,
1715                         .modulemode   = MODULEMODE_SWCTRL,
1716                 },
1717         },
1718         .opt_clks       = slimbus2_opt_clks,
1719         .opt_clks_cnt   = ARRAY_SIZE(slimbus2_opt_clks),
1720 };
1721
1722 /*
1723  * 'smartreflex' class
1724  * smartreflex module (monitor silicon performance and outputs a measure of
1725  * performance error)
1726  */
1727
1728 /* The IP is not compliant to type1 / type2 scheme */
1729 static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
1730         .rev_offs       = -ENODEV,
1731         .sysc_offs      = 0x0038,
1732         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
1733         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1734                            SIDLE_SMART_WKUP),
1735         .sysc_fields    = &omap36xx_sr_sysc_fields,
1736 };
1737
1738 static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
1739         .name   = "smartreflex",
1740         .sysc   = &omap44xx_smartreflex_sysc,
1741 };
1742
1743 /* smartreflex_core */
1744 static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
1745         .sensor_voltdm_name   = "core",
1746 };
1747
1748 static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
1749         .name           = "smartreflex_core",
1750         .class          = &omap44xx_smartreflex_hwmod_class,
1751         .clkdm_name     = "l4_ao_clkdm",
1752
1753         .main_clk       = "smartreflex_core_fck",
1754         .prcm = {
1755                 .omap4 = {
1756                         .clkctrl_offs = OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET,
1757                         .context_offs = OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET,
1758                         .modulemode   = MODULEMODE_SWCTRL,
1759                 },
1760         },
1761         .dev_attr       = &smartreflex_core_dev_attr,
1762 };
1763
1764 /* smartreflex_iva */
1765 static struct omap_smartreflex_dev_attr smartreflex_iva_dev_attr = {
1766         .sensor_voltdm_name     = "iva",
1767 };
1768
1769 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
1770         .name           = "smartreflex_iva",
1771         .class          = &omap44xx_smartreflex_hwmod_class,
1772         .clkdm_name     = "l4_ao_clkdm",
1773         .main_clk       = "smartreflex_iva_fck",
1774         .prcm = {
1775                 .omap4 = {
1776                         .clkctrl_offs = OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET,
1777                         .context_offs = OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET,
1778                         .modulemode   = MODULEMODE_SWCTRL,
1779                 },
1780         },
1781         .dev_attr       = &smartreflex_iva_dev_attr,
1782 };
1783
1784 /* smartreflex_mpu */
1785 static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
1786         .sensor_voltdm_name     = "mpu",
1787 };
1788
1789 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
1790         .name           = "smartreflex_mpu",
1791         .class          = &omap44xx_smartreflex_hwmod_class,
1792         .clkdm_name     = "l4_ao_clkdm",
1793         .main_clk       = "smartreflex_mpu_fck",
1794         .prcm = {
1795                 .omap4 = {
1796                         .clkctrl_offs = OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET,
1797                         .context_offs = OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET,
1798                         .modulemode   = MODULEMODE_SWCTRL,
1799                 },
1800         },
1801         .dev_attr       = &smartreflex_mpu_dev_attr,
1802 };
1803
1804 /*
1805  * 'spinlock' class
1806  * spinlock provides hardware assistance for synchronizing the processes
1807  * running on multiple processors
1808  */
1809
1810 static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = {
1811         .rev_offs       = 0x0000,
1812         .sysc_offs      = 0x0010,
1813         .syss_offs      = 0x0014,
1814         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1815                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1816                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1817         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1818         .sysc_fields    = &omap_hwmod_sysc_type1,
1819 };
1820
1821 static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = {
1822         .name   = "spinlock",
1823         .sysc   = &omap44xx_spinlock_sysc,
1824 };
1825
1826 /* spinlock */
1827 static struct omap_hwmod omap44xx_spinlock_hwmod = {
1828         .name           = "spinlock",
1829         .class          = &omap44xx_spinlock_hwmod_class,
1830         .clkdm_name     = "l4_cfg_clkdm",
1831         .prcm = {
1832                 .omap4 = {
1833                         .clkctrl_offs = OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET,
1834                         .context_offs = OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET,
1835                 },
1836         },
1837 };
1838
1839 /*
1840  * 'timer' class
1841  * general purpose timer module with accurate 1ms tick
1842  * This class contains several variants: ['timer_1ms', 'timer']
1843  */
1844
1845 static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = {
1846         .rev_offs       = 0x0000,
1847         .sysc_offs      = 0x0010,
1848         .syss_offs      = 0x0014,
1849         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1850                            SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
1851                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1852                            SYSS_HAS_RESET_STATUS),
1853         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1854         .sysc_fields    = &omap_hwmod_sysc_type1,
1855 };
1856
1857 static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = {
1858         .name   = "timer",
1859         .sysc   = &omap44xx_timer_1ms_sysc,
1860 };
1861
1862 static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = {
1863         .rev_offs       = 0x0000,
1864         .sysc_offs      = 0x0010,
1865         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1866                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1867         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1868                            SIDLE_SMART_WKUP),
1869         .sysc_fields    = &omap_hwmod_sysc_type2,
1870 };
1871
1872 static struct omap_hwmod_class omap44xx_timer_hwmod_class = {
1873         .name   = "timer",
1874         .sysc   = &omap44xx_timer_sysc,
1875 };
1876
1877 /* timer1 */
1878 static struct omap_hwmod omap44xx_timer1_hwmod = {
1879         .name           = "timer1",
1880         .class          = &omap44xx_timer_1ms_hwmod_class,
1881         .clkdm_name     = "l4_wkup_clkdm",
1882         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
1883         .main_clk       = "dmt1_clk_mux",
1884         .prcm = {
1885                 .omap4 = {
1886                         .clkctrl_offs = OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
1887                         .context_offs = OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET,
1888                         .modulemode   = MODULEMODE_SWCTRL,
1889                 },
1890         },
1891 };
1892
1893 /* timer2 */
1894 static struct omap_hwmod omap44xx_timer2_hwmod = {
1895         .name           = "timer2",
1896         .class          = &omap44xx_timer_1ms_hwmod_class,
1897         .clkdm_name     = "l4_per_clkdm",
1898         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
1899         .main_clk       = "cm2_dm2_mux",
1900         .prcm = {
1901                 .omap4 = {
1902                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET,
1903                         .context_offs = OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET,
1904                         .modulemode   = MODULEMODE_SWCTRL,
1905                 },
1906         },
1907 };
1908
1909 /* timer3 */
1910 static struct omap_hwmod omap44xx_timer3_hwmod = {
1911         .name           = "timer3",
1912         .class          = &omap44xx_timer_hwmod_class,
1913         .clkdm_name     = "l4_per_clkdm",
1914         .main_clk       = "cm2_dm3_mux",
1915         .prcm = {
1916                 .omap4 = {
1917                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET,
1918                         .context_offs = OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET,
1919                         .modulemode   = MODULEMODE_SWCTRL,
1920                 },
1921         },
1922 };
1923
1924 /* timer4 */
1925 static struct omap_hwmod omap44xx_timer4_hwmod = {
1926         .name           = "timer4",
1927         .class          = &omap44xx_timer_hwmod_class,
1928         .clkdm_name     = "l4_per_clkdm",
1929         .main_clk       = "cm2_dm4_mux",
1930         .prcm = {
1931                 .omap4 = {
1932                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET,
1933                         .context_offs = OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET,
1934                         .modulemode   = MODULEMODE_SWCTRL,
1935                 },
1936         },
1937 };
1938
1939 /* timer5 */
1940 static struct omap_hwmod omap44xx_timer5_hwmod = {
1941         .name           = "timer5",
1942         .class          = &omap44xx_timer_hwmod_class,
1943         .clkdm_name     = "abe_clkdm",
1944         .main_clk       = "timer5_sync_mux",
1945         .prcm = {
1946                 .omap4 = {
1947                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET,
1948                         .context_offs = OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET,
1949                         .modulemode   = MODULEMODE_SWCTRL,
1950                 },
1951         },
1952 };
1953
1954 /* timer6 */
1955 static struct omap_hwmod omap44xx_timer6_hwmod = {
1956         .name           = "timer6",
1957         .class          = &omap44xx_timer_hwmod_class,
1958         .clkdm_name     = "abe_clkdm",
1959         .main_clk       = "timer6_sync_mux",
1960         .prcm = {
1961                 .omap4 = {
1962                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET,
1963                         .context_offs = OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET,
1964                         .modulemode   = MODULEMODE_SWCTRL,
1965                 },
1966         },
1967 };
1968
1969 /* timer7 */
1970 static struct omap_hwmod omap44xx_timer7_hwmod = {
1971         .name           = "timer7",
1972         .class          = &omap44xx_timer_hwmod_class,
1973         .clkdm_name     = "abe_clkdm",
1974         .main_clk       = "timer7_sync_mux",
1975         .prcm = {
1976                 .omap4 = {
1977                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET,
1978                         .context_offs = OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET,
1979                         .modulemode   = MODULEMODE_SWCTRL,
1980                 },
1981         },
1982 };
1983
1984 /* timer8 */
1985 static struct omap_hwmod omap44xx_timer8_hwmod = {
1986         .name           = "timer8",
1987         .class          = &omap44xx_timer_hwmod_class,
1988         .clkdm_name     = "abe_clkdm",
1989         .main_clk       = "timer8_sync_mux",
1990         .prcm = {
1991                 .omap4 = {
1992                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET,
1993                         .context_offs = OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET,
1994                         .modulemode   = MODULEMODE_SWCTRL,
1995                 },
1996         },
1997 };
1998
1999 /* timer9 */
2000 static struct omap_hwmod omap44xx_timer9_hwmod = {
2001         .name           = "timer9",
2002         .class          = &omap44xx_timer_hwmod_class,
2003         .clkdm_name     = "l4_per_clkdm",
2004         .main_clk       = "cm2_dm9_mux",
2005         .prcm = {
2006                 .omap4 = {
2007                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET,
2008                         .context_offs = OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET,
2009                         .modulemode   = MODULEMODE_SWCTRL,
2010                 },
2011         },
2012 };
2013
2014 /* timer10 */
2015 static struct omap_hwmod omap44xx_timer10_hwmod = {
2016         .name           = "timer10",
2017         .class          = &omap44xx_timer_1ms_hwmod_class,
2018         .clkdm_name     = "l4_per_clkdm",
2019         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
2020         .main_clk       = "cm2_dm10_mux",
2021         .prcm = {
2022                 .omap4 = {
2023                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET,
2024                         .context_offs = OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET,
2025                         .modulemode   = MODULEMODE_SWCTRL,
2026                 },
2027         },
2028 };
2029
2030 /* timer11 */
2031 static struct omap_hwmod omap44xx_timer11_hwmod = {
2032         .name           = "timer11",
2033         .class          = &omap44xx_timer_hwmod_class,
2034         .clkdm_name     = "l4_per_clkdm",
2035         .main_clk       = "cm2_dm11_mux",
2036         .prcm = {
2037                 .omap4 = {
2038                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET,
2039                         .context_offs = OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET,
2040                         .modulemode   = MODULEMODE_SWCTRL,
2041                 },
2042         },
2043 };
2044
2045 /*
2046  * 'usb_host_fs' class
2047  * full-speed usb host controller
2048  */
2049
2050 /* The IP is not compliant to type1 / type2 scheme */
2051 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_fs_sysc = {
2052         .rev_offs       = 0x0000,
2053         .sysc_offs      = 0x0210,
2054         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
2055                            SYSC_HAS_SOFTRESET),
2056         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2057                            SIDLE_SMART_WKUP),
2058         .sysc_fields    = &omap_hwmod_sysc_type_usb_host_fs,
2059 };
2060
2061 static struct omap_hwmod_class omap44xx_usb_host_fs_hwmod_class = {
2062         .name   = "usb_host_fs",
2063         .sysc   = &omap44xx_usb_host_fs_sysc,
2064 };
2065
2066 /* usb_host_fs */
2067 static struct omap_hwmod omap44xx_usb_host_fs_hwmod = {
2068         .name           = "usb_host_fs",
2069         .class          = &omap44xx_usb_host_fs_hwmod_class,
2070         .clkdm_name     = "l3_init_clkdm",
2071         .main_clk       = "usb_host_fs_fck",
2072         .prcm = {
2073                 .omap4 = {
2074                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_FS_CLKCTRL_OFFSET,
2075                         .context_offs = OMAP4_RM_L3INIT_USB_HOST_FS_CONTEXT_OFFSET,
2076                         .modulemode   = MODULEMODE_SWCTRL,
2077                 },
2078         },
2079 };
2080
2081 /*
2082  * 'usb_host_hs' class
2083  * high-speed multi-port usb host controller
2084  */
2085
2086 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc = {
2087         .rev_offs       = 0x0000,
2088         .sysc_offs      = 0x0010,
2089         .syss_offs      = 0x0014,
2090         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
2091                            SYSC_HAS_SOFTRESET | SYSC_HAS_RESET_STATUS),
2092         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2093                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2094                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2095         .sysc_fields    = &omap_hwmod_sysc_type2,
2096 };
2097
2098 static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class = {
2099         .name   = "usb_host_hs",
2100         .sysc   = &omap44xx_usb_host_hs_sysc,
2101 };
2102
2103 /* usb_host_hs */
2104 static struct omap_hwmod omap44xx_usb_host_hs_hwmod = {
2105         .name           = "usb_host_hs",
2106         .class          = &omap44xx_usb_host_hs_hwmod_class,
2107         .clkdm_name     = "l3_init_clkdm",
2108         .main_clk       = "usb_host_hs_fck",
2109         .prcm = {
2110                 .omap4 = {
2111                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET,
2112                         .context_offs = OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET,
2113                         .modulemode   = MODULEMODE_SWCTRL,
2114                 },
2115         },
2116
2117         /*
2118          * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
2119          * id: i660
2120          *
2121          * Description:
2122          * In the following configuration :
2123          * - USBHOST module is set to smart-idle mode
2124          * - PRCM asserts idle_req to the USBHOST module ( This typically
2125          *   happens when the system is going to a low power mode : all ports
2126          *   have been suspended, the master part of the USBHOST module has
2127          *   entered the standby state, and SW has cut the functional clocks)
2128          * - an USBHOST interrupt occurs before the module is able to answer
2129          *   idle_ack, typically a remote wakeup IRQ.
2130          * Then the USB HOST module will enter a deadlock situation where it
2131          * is no more accessible nor functional.
2132          *
2133          * Workaround:
2134          * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
2135          */
2136
2137         /*
2138          * Errata: USB host EHCI may stall when entering smart-standby mode
2139          * Id: i571
2140          *
2141          * Description:
2142          * When the USBHOST module is set to smart-standby mode, and when it is
2143          * ready to enter the standby state (i.e. all ports are suspended and
2144          * all attached devices are in suspend mode), then it can wrongly assert
2145          * the Mstandby signal too early while there are still some residual OCP
2146          * transactions ongoing. If this condition occurs, the internal state
2147          * machine may go to an undefined state and the USB link may be stuck
2148          * upon the next resume.
2149          *
2150          * Workaround:
2151          * Don't use smart standby; use only force standby,
2152          * hence HWMOD_SWSUP_MSTANDBY
2153          */
2154
2155         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
2156 };
2157
2158 /*
2159  * 'usb_otg_hs' class
2160  * high-speed on-the-go universal serial bus (usb_otg_hs) controller
2161  */
2162
2163 static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = {
2164         .rev_offs       = 0x0400,
2165         .sysc_offs      = 0x0404,
2166         .syss_offs      = 0x0408,
2167         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
2168                            SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
2169                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2170         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2171                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2172                            MSTANDBY_SMART),
2173         .sysc_fields    = &omap_hwmod_sysc_type1,
2174 };
2175
2176 static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = {
2177         .name   = "usb_otg_hs",
2178         .sysc   = &omap44xx_usb_otg_hs_sysc,
2179 };
2180
2181 /* usb_otg_hs */
2182 static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = {
2183         { .role = "xclk", .clk = "usb_otg_hs_xclk" },
2184 };
2185
2186 static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
2187         .name           = "usb_otg_hs",
2188         .class          = &omap44xx_usb_otg_hs_hwmod_class,
2189         .clkdm_name     = "l3_init_clkdm",
2190         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
2191         .main_clk       = "usb_otg_hs_ick",
2192         .prcm = {
2193                 .omap4 = {
2194                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET,
2195                         .context_offs = OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET,
2196                         .modulemode   = MODULEMODE_HWCTRL,
2197                 },
2198         },
2199         .opt_clks       = usb_otg_hs_opt_clks,
2200         .opt_clks_cnt   = ARRAY_SIZE(usb_otg_hs_opt_clks),
2201 };
2202
2203 /*
2204  * 'usb_tll_hs' class
2205  * usb_tll_hs module is the adapter on the usb_host_hs ports
2206  */
2207
2208 static struct omap_hwmod_class_sysconfig omap44xx_usb_tll_hs_sysc = {
2209         .rev_offs       = 0x0000,
2210         .sysc_offs      = 0x0010,
2211         .syss_offs      = 0x0014,
2212         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2213                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
2214                            SYSC_HAS_AUTOIDLE),
2215         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2216         .sysc_fields    = &omap_hwmod_sysc_type1,
2217 };
2218
2219 static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class = {
2220         .name   = "usb_tll_hs",
2221         .sysc   = &omap44xx_usb_tll_hs_sysc,
2222 };
2223
2224 static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = {
2225         .name           = "usb_tll_hs",
2226         .class          = &omap44xx_usb_tll_hs_hwmod_class,
2227         .clkdm_name     = "l3_init_clkdm",
2228         .main_clk       = "usb_tll_hs_ick",
2229         .prcm = {
2230                 .omap4 = {
2231                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET,
2232                         .context_offs = OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET,
2233                         .modulemode   = MODULEMODE_HWCTRL,
2234                 },
2235         },
2236 };
2237
2238 /*
2239  * interfaces
2240  */
2241
2242 /* l3_main_1 -> dmm */
2243 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
2244         .master         = &omap44xx_l3_main_1_hwmod,
2245         .slave          = &omap44xx_dmm_hwmod,
2246         .clk            = "l3_div_ck",
2247         .user           = OCP_USER_SDMA,
2248 };
2249
2250 /* mpu -> dmm */
2251 static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
2252         .master         = &omap44xx_mpu_hwmod,
2253         .slave          = &omap44xx_dmm_hwmod,
2254         .clk            = "l3_div_ck",
2255         .user           = OCP_USER_MPU,
2256 };
2257
2258 /* iva -> l3_instr */
2259 static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
2260         .master         = &omap44xx_iva_hwmod,
2261         .slave          = &omap44xx_l3_instr_hwmod,
2262         .clk            = "l3_div_ck",
2263         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2264 };
2265
2266 /* l3_main_3 -> l3_instr */
2267 static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
2268         .master         = &omap44xx_l3_main_3_hwmod,
2269         .slave          = &omap44xx_l3_instr_hwmod,
2270         .clk            = "l3_div_ck",
2271         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2272 };
2273
2274 /* ocp_wp_noc -> l3_instr */
2275 static struct omap_hwmod_ocp_if omap44xx_ocp_wp_noc__l3_instr = {
2276         .master         = &omap44xx_ocp_wp_noc_hwmod,
2277         .slave          = &omap44xx_l3_instr_hwmod,
2278         .clk            = "l3_div_ck",
2279         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2280 };
2281
2282 /* dsp -> l3_main_1 */
2283 static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
2284         .master         = &omap44xx_dsp_hwmod,
2285         .slave          = &omap44xx_l3_main_1_hwmod,
2286         .clk            = "l3_div_ck",
2287         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2288 };
2289
2290 /* dss -> l3_main_1 */
2291 static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = {
2292         .master         = &omap44xx_dss_hwmod,
2293         .slave          = &omap44xx_l3_main_1_hwmod,
2294         .clk            = "l3_div_ck",
2295         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2296 };
2297
2298 /* l3_main_2 -> l3_main_1 */
2299 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
2300         .master         = &omap44xx_l3_main_2_hwmod,
2301         .slave          = &omap44xx_l3_main_1_hwmod,
2302         .clk            = "l3_div_ck",
2303         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2304 };
2305
2306 /* l4_cfg -> l3_main_1 */
2307 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
2308         .master         = &omap44xx_l4_cfg_hwmod,
2309         .slave          = &omap44xx_l3_main_1_hwmod,
2310         .clk            = "l4_div_ck",
2311         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2312 };
2313
2314 /* mpu -> l3_main_1 */
2315 static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
2316         .master         = &omap44xx_mpu_hwmod,
2317         .slave          = &omap44xx_l3_main_1_hwmod,
2318         .clk            = "l3_div_ck",
2319         .user           = OCP_USER_MPU,
2320 };
2321
2322 /* debugss -> l3_main_2 */
2323 static struct omap_hwmod_ocp_if omap44xx_debugss__l3_main_2 = {
2324         .master         = &omap44xx_debugss_hwmod,
2325         .slave          = &omap44xx_l3_main_2_hwmod,
2326         .clk            = "dbgclk_mux_ck",
2327         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2328 };
2329
2330 /* dma_system -> l3_main_2 */
2331 static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
2332         .master         = &omap44xx_dma_system_hwmod,
2333         .slave          = &omap44xx_l3_main_2_hwmod,
2334         .clk            = "l3_div_ck",
2335         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2336 };
2337
2338 /* fdif -> l3_main_2 */
2339 static struct omap_hwmod_ocp_if omap44xx_fdif__l3_main_2 = {
2340         .master         = &omap44xx_fdif_hwmod,
2341         .slave          = &omap44xx_l3_main_2_hwmod,
2342         .clk            = "l3_div_ck",
2343         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2344 };
2345
2346 /* hsi -> l3_main_2 */
2347 static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = {
2348         .master         = &omap44xx_hsi_hwmod,
2349         .slave          = &omap44xx_l3_main_2_hwmod,
2350         .clk            = "l3_div_ck",
2351         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2352 };
2353
2354 /* ipu -> l3_main_2 */
2355 static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = {
2356         .master         = &omap44xx_ipu_hwmod,
2357         .slave          = &omap44xx_l3_main_2_hwmod,
2358         .clk            = "l3_div_ck",
2359         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2360 };
2361
2362 /* iss -> l3_main_2 */
2363 static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = {
2364         .master         = &omap44xx_iss_hwmod,
2365         .slave          = &omap44xx_l3_main_2_hwmod,
2366         .clk            = "l3_div_ck",
2367         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2368 };
2369
2370 /* iva -> l3_main_2 */
2371 static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
2372         .master         = &omap44xx_iva_hwmod,
2373         .slave          = &omap44xx_l3_main_2_hwmod,
2374         .clk            = "l3_div_ck",
2375         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2376 };
2377
2378 /* l3_main_1 -> l3_main_2 */
2379 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
2380         .master         = &omap44xx_l3_main_1_hwmod,
2381         .slave          = &omap44xx_l3_main_2_hwmod,
2382         .clk            = "l3_div_ck",
2383         .user           = OCP_USER_MPU,
2384 };
2385
2386 /* l4_cfg -> l3_main_2 */
2387 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
2388         .master         = &omap44xx_l4_cfg_hwmod,
2389         .slave          = &omap44xx_l3_main_2_hwmod,
2390         .clk            = "l4_div_ck",
2391         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2392 };
2393
2394 /* usb_host_fs -> l3_main_2 */
2395 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_usb_host_fs__l3_main_2 = {
2396         .master         = &omap44xx_usb_host_fs_hwmod,
2397         .slave          = &omap44xx_l3_main_2_hwmod,
2398         .clk            = "l3_div_ck",
2399         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2400 };
2401
2402 /* usb_host_hs -> l3_main_2 */
2403 static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2 = {
2404         .master         = &omap44xx_usb_host_hs_hwmod,
2405         .slave          = &omap44xx_l3_main_2_hwmod,
2406         .clk            = "l3_div_ck",
2407         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2408 };
2409
2410 /* usb_otg_hs -> l3_main_2 */
2411 static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = {
2412         .master         = &omap44xx_usb_otg_hs_hwmod,
2413         .slave          = &omap44xx_l3_main_2_hwmod,
2414         .clk            = "l3_div_ck",
2415         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2416 };
2417
2418 /* l3_main_1 -> l3_main_3 */
2419 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
2420         .master         = &omap44xx_l3_main_1_hwmod,
2421         .slave          = &omap44xx_l3_main_3_hwmod,
2422         .clk            = "l3_div_ck",
2423         .user           = OCP_USER_MPU,
2424 };
2425
2426 /* l3_main_2 -> l3_main_3 */
2427 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
2428         .master         = &omap44xx_l3_main_2_hwmod,
2429         .slave          = &omap44xx_l3_main_3_hwmod,
2430         .clk            = "l3_div_ck",
2431         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2432 };
2433
2434 /* l4_cfg -> l3_main_3 */
2435 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
2436         .master         = &omap44xx_l4_cfg_hwmod,
2437         .slave          = &omap44xx_l3_main_3_hwmod,
2438         .clk            = "l4_div_ck",
2439         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2440 };
2441
2442 /* aess -> l4_abe */
2443 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_aess__l4_abe = {
2444         .master         = &omap44xx_aess_hwmod,
2445         .slave          = &omap44xx_l4_abe_hwmod,
2446         .clk            = "ocp_abe_iclk",
2447         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2448 };
2449
2450 /* dsp -> l4_abe */
2451 static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
2452         .master         = &omap44xx_dsp_hwmod,
2453         .slave          = &omap44xx_l4_abe_hwmod,
2454         .clk            = "ocp_abe_iclk",
2455         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2456 };
2457
2458 /* l3_main_1 -> l4_abe */
2459 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
2460         .master         = &omap44xx_l3_main_1_hwmod,
2461         .slave          = &omap44xx_l4_abe_hwmod,
2462         .clk            = "l3_div_ck",
2463         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2464 };
2465
2466 /* mpu -> l4_abe */
2467 static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
2468         .master         = &omap44xx_mpu_hwmod,
2469         .slave          = &omap44xx_l4_abe_hwmod,
2470         .clk            = "ocp_abe_iclk",
2471         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2472 };
2473
2474 /* l3_main_1 -> l4_cfg */
2475 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
2476         .master         = &omap44xx_l3_main_1_hwmod,
2477         .slave          = &omap44xx_l4_cfg_hwmod,
2478         .clk            = "l3_div_ck",
2479         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2480 };
2481
2482 /* l3_main_2 -> l4_per */
2483 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
2484         .master         = &omap44xx_l3_main_2_hwmod,
2485         .slave          = &omap44xx_l4_per_hwmod,
2486         .clk            = "l3_div_ck",
2487         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2488 };
2489
2490 /* l4_cfg -> l4_wkup */
2491 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
2492         .master         = &omap44xx_l4_cfg_hwmod,
2493         .slave          = &omap44xx_l4_wkup_hwmod,
2494         .clk            = "l4_div_ck",
2495         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2496 };
2497
2498 /* mpu -> mpu_private */
2499 static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
2500         .master         = &omap44xx_mpu_hwmod,
2501         .slave          = &omap44xx_mpu_private_hwmod,
2502         .clk            = "l3_div_ck",
2503         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2504 };
2505
2506 /* l4_cfg -> ocp_wp_noc */
2507 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp_wp_noc = {
2508         .master         = &omap44xx_l4_cfg_hwmod,
2509         .slave          = &omap44xx_ocp_wp_noc_hwmod,
2510         .clk            = "l4_div_ck",
2511         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2512 };
2513
2514 /* l4_abe -> aess */
2515 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess = {
2516         .master         = &omap44xx_l4_abe_hwmod,
2517         .slave          = &omap44xx_aess_hwmod,
2518         .clk            = "ocp_abe_iclk",
2519         .user           = OCP_USER_MPU,
2520 };
2521
2522 /* l4_abe -> aess (dma) */
2523 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess_dma = {
2524         .master         = &omap44xx_l4_abe_hwmod,
2525         .slave          = &omap44xx_aess_hwmod,
2526         .clk            = "ocp_abe_iclk",
2527         .user           = OCP_USER_SDMA,
2528 };
2529
2530 /* l4_wkup -> counter_32k */
2531 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
2532         .master         = &omap44xx_l4_wkup_hwmod,
2533         .slave          = &omap44xx_counter_32k_hwmod,
2534         .clk            = "l4_wkup_clk_mux_ck",
2535         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2536 };
2537
2538 /* l4_cfg -> ctrl_module_core */
2539 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_core = {
2540         .master         = &omap44xx_l4_cfg_hwmod,
2541         .slave          = &omap44xx_ctrl_module_core_hwmod,
2542         .clk            = "l4_div_ck",
2543         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2544 };
2545
2546 /* l4_cfg -> ctrl_module_pad_core */
2547 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_pad_core = {
2548         .master         = &omap44xx_l4_cfg_hwmod,
2549         .slave          = &omap44xx_ctrl_module_pad_core_hwmod,
2550         .clk            = "l4_div_ck",
2551         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2552 };
2553
2554 /* l4_wkup -> ctrl_module_wkup */
2555 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_wkup = {
2556         .master         = &omap44xx_l4_wkup_hwmod,
2557         .slave          = &omap44xx_ctrl_module_wkup_hwmod,
2558         .clk            = "l4_wkup_clk_mux_ck",
2559         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2560 };
2561
2562 /* l4_wkup -> ctrl_module_pad_wkup */
2563 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_pad_wkup = {
2564         .master         = &omap44xx_l4_wkup_hwmod,
2565         .slave          = &omap44xx_ctrl_module_pad_wkup_hwmod,
2566         .clk            = "l4_wkup_clk_mux_ck",
2567         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2568 };
2569
2570 /* l3_instr -> debugss */
2571 static struct omap_hwmod_ocp_if omap44xx_l3_instr__debugss = {
2572         .master         = &omap44xx_l3_instr_hwmod,
2573         .slave          = &omap44xx_debugss_hwmod,
2574         .clk            = "l3_div_ck",
2575         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2576 };
2577
2578 /* l4_cfg -> dma_system */
2579 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
2580         .master         = &omap44xx_l4_cfg_hwmod,
2581         .slave          = &omap44xx_dma_system_hwmod,
2582         .clk            = "l4_div_ck",
2583         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2584 };
2585
2586 /* l4_abe -> dmic */
2587 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
2588         .master         = &omap44xx_l4_abe_hwmod,
2589         .slave          = &omap44xx_dmic_hwmod,
2590         .clk            = "ocp_abe_iclk",
2591         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2592 };
2593
2594 /* dsp -> iva */
2595 static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
2596         .master         = &omap44xx_dsp_hwmod,
2597         .slave          = &omap44xx_iva_hwmod,
2598         .clk            = "dpll_iva_m5x2_ck",
2599         .user           = OCP_USER_DSP,
2600 };
2601
2602 /* dsp -> sl2if */
2603 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_dsp__sl2if = {
2604         .master         = &omap44xx_dsp_hwmod,
2605         .slave          = &omap44xx_sl2if_hwmod,
2606         .clk            = "dpll_iva_m5x2_ck",
2607         .user           = OCP_USER_DSP,
2608 };
2609
2610 /* l4_cfg -> dsp */
2611 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
2612         .master         = &omap44xx_l4_cfg_hwmod,
2613         .slave          = &omap44xx_dsp_hwmod,
2614         .clk            = "l4_div_ck",
2615         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2616 };
2617
2618 /* l3_main_2 -> dss */
2619 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
2620         .master         = &omap44xx_l3_main_2_hwmod,
2621         .slave          = &omap44xx_dss_hwmod,
2622         .clk            = "l3_div_ck",
2623         .user           = OCP_USER_SDMA,
2624 };
2625
2626 /* l4_per -> dss */
2627 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
2628         .master         = &omap44xx_l4_per_hwmod,
2629         .slave          = &omap44xx_dss_hwmod,
2630         .clk            = "l4_div_ck",
2631         .user           = OCP_USER_MPU,
2632 };
2633
2634 /* l3_main_2 -> dss_dispc */
2635 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
2636         .master         = &omap44xx_l3_main_2_hwmod,
2637         .slave          = &omap44xx_dss_dispc_hwmod,
2638         .clk            = "l3_div_ck",
2639         .user           = OCP_USER_SDMA,
2640 };
2641
2642 /* l4_per -> dss_dispc */
2643 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
2644         .master         = &omap44xx_l4_per_hwmod,
2645         .slave          = &omap44xx_dss_dispc_hwmod,
2646         .clk            = "l4_div_ck",
2647         .user           = OCP_USER_MPU,
2648 };
2649
2650 /* l3_main_2 -> dss_dsi1 */
2651 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
2652         .master         = &omap44xx_l3_main_2_hwmod,
2653         .slave          = &omap44xx_dss_dsi1_hwmod,
2654         .clk            = "l3_div_ck",
2655         .user           = OCP_USER_SDMA,
2656 };
2657
2658 /* l4_per -> dss_dsi1 */
2659 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
2660         .master         = &omap44xx_l4_per_hwmod,
2661         .slave          = &omap44xx_dss_dsi1_hwmod,
2662         .clk            = "l4_div_ck",
2663         .user           = OCP_USER_MPU,
2664 };
2665
2666 /* l3_main_2 -> dss_dsi2 */
2667 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
2668         .master         = &omap44xx_l3_main_2_hwmod,
2669         .slave          = &omap44xx_dss_dsi2_hwmod,
2670         .clk            = "l3_div_ck",
2671         .user           = OCP_USER_SDMA,
2672 };
2673
2674 /* l4_per -> dss_dsi2 */
2675 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
2676         .master         = &omap44xx_l4_per_hwmod,
2677         .slave          = &omap44xx_dss_dsi2_hwmod,
2678         .clk            = "l4_div_ck",
2679         .user           = OCP_USER_MPU,
2680 };
2681
2682 /* l3_main_2 -> dss_hdmi */
2683 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
2684         .master         = &omap44xx_l3_main_2_hwmod,
2685         .slave          = &omap44xx_dss_hdmi_hwmod,
2686         .clk            = "l3_div_ck",
2687         .user           = OCP_USER_SDMA,
2688 };
2689
2690 /* l4_per -> dss_hdmi */
2691 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
2692         .master         = &omap44xx_l4_per_hwmod,
2693         .slave          = &omap44xx_dss_hdmi_hwmod,
2694         .clk            = "l4_div_ck",
2695         .user           = OCP_USER_MPU,
2696 };
2697
2698 /* l3_main_2 -> dss_rfbi */
2699 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
2700         .master         = &omap44xx_l3_main_2_hwmod,
2701         .slave          = &omap44xx_dss_rfbi_hwmod,
2702         .clk            = "l3_div_ck",
2703         .user           = OCP_USER_SDMA,
2704 };
2705
2706 /* l4_per -> dss_rfbi */
2707 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
2708         .master         = &omap44xx_l4_per_hwmod,
2709         .slave          = &omap44xx_dss_rfbi_hwmod,
2710         .clk            = "l4_div_ck",
2711         .user           = OCP_USER_MPU,
2712 };
2713
2714 /* l3_main_2 -> dss_venc */
2715 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
2716         .master         = &omap44xx_l3_main_2_hwmod,
2717         .slave          = &omap44xx_dss_venc_hwmod,
2718         .clk            = "l3_div_ck",
2719         .user           = OCP_USER_SDMA,
2720 };
2721
2722 /* l4_per -> dss_venc */
2723 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
2724         .master         = &omap44xx_l4_per_hwmod,
2725         .slave          = &omap44xx_dss_venc_hwmod,
2726         .clk            = "l4_div_ck",
2727         .user           = OCP_USER_MPU,
2728 };
2729
2730 /* l3_main_2 -> sham */
2731 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__sha0 = {
2732         .master         = &omap44xx_l3_main_2_hwmod,
2733         .slave          = &omap44xx_sha0_hwmod,
2734         .clk            = "l3_div_ck",
2735         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2736 };
2737
2738 /* l4_per -> elm */
2739 static struct omap_hwmod_ocp_if omap44xx_l4_per__elm = {
2740         .master         = &omap44xx_l4_per_hwmod,
2741         .slave          = &omap44xx_elm_hwmod,
2742         .clk            = "l4_div_ck",
2743         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2744 };
2745
2746 /* l4_cfg -> fdif */
2747 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__fdif = {
2748         .master         = &omap44xx_l4_cfg_hwmod,
2749         .slave          = &omap44xx_fdif_hwmod,
2750         .clk            = "l4_div_ck",
2751         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2752 };
2753
2754 /* l3_main_2 -> gpmc */
2755 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = {
2756         .master         = &omap44xx_l3_main_2_hwmod,
2757         .slave          = &omap44xx_gpmc_hwmod,
2758         .clk            = "l3_div_ck",
2759         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2760 };
2761
2762 /* l4_per -> hdq1w */
2763 static struct omap_hwmod_ocp_if omap44xx_l4_per__hdq1w = {
2764         .master         = &omap44xx_l4_per_hwmod,
2765         .slave          = &omap44xx_hdq1w_hwmod,
2766         .clk            = "l4_div_ck",
2767         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2768 };
2769
2770 /* l4_cfg -> hsi */
2771 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
2772         .master         = &omap44xx_l4_cfg_hwmod,
2773         .slave          = &omap44xx_hsi_hwmod,
2774         .clk            = "l4_div_ck",
2775         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2776 };
2777
2778 /* l3_main_2 -> ipu */
2779 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = {
2780         .master         = &omap44xx_l3_main_2_hwmod,
2781         .slave          = &omap44xx_ipu_hwmod,
2782         .clk            = "l3_div_ck",
2783         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2784 };
2785
2786 /* l3_main_2 -> iss */
2787 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
2788         .master         = &omap44xx_l3_main_2_hwmod,
2789         .slave          = &omap44xx_iss_hwmod,
2790         .clk            = "l3_div_ck",
2791         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2792 };
2793
2794 /* iva -> sl2if */
2795 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_iva__sl2if = {
2796         .master         = &omap44xx_iva_hwmod,
2797         .slave          = &omap44xx_sl2if_hwmod,
2798         .clk            = "dpll_iva_m5x2_ck",
2799         .user           = OCP_USER_IVA,
2800 };
2801
2802 /* l3_main_2 -> iva */
2803 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
2804         .master         = &omap44xx_l3_main_2_hwmod,
2805         .slave          = &omap44xx_iva_hwmod,
2806         .clk            = "l3_div_ck",
2807         .user           = OCP_USER_MPU,
2808 };
2809
2810 /* l4_wkup -> kbd */
2811 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
2812         .master         = &omap44xx_l4_wkup_hwmod,
2813         .slave          = &omap44xx_kbd_hwmod,
2814         .clk            = "l4_wkup_clk_mux_ck",
2815         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2816 };
2817
2818 /* l4_abe -> mcasp */
2819 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp = {
2820         .master         = &omap44xx_l4_abe_hwmod,
2821         .slave          = &omap44xx_mcasp_hwmod,
2822         .clk            = "ocp_abe_iclk",
2823         .user           = OCP_USER_MPU,
2824 };
2825
2826 /* l4_abe -> mcasp (dma) */
2827 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp_dma = {
2828         .master         = &omap44xx_l4_abe_hwmod,
2829         .slave          = &omap44xx_mcasp_hwmod,
2830         .clk            = "ocp_abe_iclk",
2831         .user           = OCP_USER_SDMA,
2832 };
2833
2834 /* l4_abe -> mcpdm */
2835 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
2836         .master         = &omap44xx_l4_abe_hwmod,
2837         .slave          = &omap44xx_mcpdm_hwmod,
2838         .clk            = "ocp_abe_iclk",
2839         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2840 };
2841
2842 /* l3_main_2 -> ocmc_ram */
2843 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ocmc_ram = {
2844         .master         = &omap44xx_l3_main_2_hwmod,
2845         .slave          = &omap44xx_ocmc_ram_hwmod,
2846         .clk            = "l3_div_ck",
2847         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2848 };
2849
2850 /* l4_cfg -> ocp2scp_usb_phy */
2851 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp2scp_usb_phy = {
2852         .master         = &omap44xx_l4_cfg_hwmod,
2853         .slave          = &omap44xx_ocp2scp_usb_phy_hwmod,
2854         .clk            = "l4_div_ck",
2855         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2856 };
2857
2858 /* mpu_private -> prcm_mpu */
2859 static struct omap_hwmod_ocp_if omap44xx_mpu_private__prcm_mpu = {
2860         .master         = &omap44xx_mpu_private_hwmod,
2861         .slave          = &omap44xx_prcm_mpu_hwmod,
2862         .clk            = "l3_div_ck",
2863         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2864 };
2865
2866 /* l4_wkup -> cm_core_aon */
2867 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__cm_core_aon = {
2868         .master         = &omap44xx_l4_wkup_hwmod,
2869         .slave          = &omap44xx_cm_core_aon_hwmod,
2870         .clk            = "l4_wkup_clk_mux_ck",
2871         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2872 };
2873
2874 /* l4_cfg -> cm_core */
2875 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__cm_core = {
2876         .master         = &omap44xx_l4_cfg_hwmod,
2877         .slave          = &omap44xx_cm_core_hwmod,
2878         .clk            = "l4_div_ck",
2879         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2880 };
2881
2882 /* l4_wkup -> prm */
2883 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__prm = {
2884         .master         = &omap44xx_l4_wkup_hwmod,
2885         .slave          = &omap44xx_prm_hwmod,
2886         .clk            = "l4_wkup_clk_mux_ck",
2887         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2888 };
2889
2890 /* l4_wkup -> scrm */
2891 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__scrm = {
2892         .master         = &omap44xx_l4_wkup_hwmod,
2893         .slave          = &omap44xx_scrm_hwmod,
2894         .clk            = "l4_wkup_clk_mux_ck",
2895         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2896 };
2897
2898 /* l3_main_2 -> sl2if */
2899 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l3_main_2__sl2if = {
2900         .master         = &omap44xx_l3_main_2_hwmod,
2901         .slave          = &omap44xx_sl2if_hwmod,
2902         .clk            = "l3_div_ck",
2903         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2904 };
2905
2906 /* l4_abe -> slimbus1 */
2907 static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1 = {
2908         .master         = &omap44xx_l4_abe_hwmod,
2909         .slave          = &omap44xx_slimbus1_hwmod,
2910         .clk            = "ocp_abe_iclk",
2911         .user           = OCP_USER_MPU,
2912 };
2913
2914 /* l4_abe -> slimbus1 (dma) */
2915 static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1_dma = {
2916         .master         = &omap44xx_l4_abe_hwmod,
2917         .slave          = &omap44xx_slimbus1_hwmod,
2918         .clk            = "ocp_abe_iclk",
2919         .user           = OCP_USER_SDMA,
2920 };
2921
2922 /* l4_per -> slimbus2 */
2923 static struct omap_hwmod_ocp_if omap44xx_l4_per__slimbus2 = {
2924         .master         = &omap44xx_l4_per_hwmod,
2925         .slave          = &omap44xx_slimbus2_hwmod,
2926         .clk            = "l4_div_ck",
2927         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2928 };
2929
2930 /* l4_cfg -> smartreflex_core */
2931 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
2932         .master         = &omap44xx_l4_cfg_hwmod,
2933         .slave          = &omap44xx_smartreflex_core_hwmod,
2934         .clk            = "l4_div_ck",
2935         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2936 };
2937
2938 /* l4_cfg -> smartreflex_iva */
2939 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
2940         .master         = &omap44xx_l4_cfg_hwmod,
2941         .slave          = &omap44xx_smartreflex_iva_hwmod,
2942         .clk            = "l4_div_ck",
2943         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2944 };
2945
2946 /* l4_cfg -> smartreflex_mpu */
2947 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
2948         .master         = &omap44xx_l4_cfg_hwmod,
2949         .slave          = &omap44xx_smartreflex_mpu_hwmod,
2950         .clk            = "l4_div_ck",
2951         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2952 };
2953
2954 /* l4_cfg -> spinlock */
2955 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
2956         .master         = &omap44xx_l4_cfg_hwmod,
2957         .slave          = &omap44xx_spinlock_hwmod,
2958         .clk            = "l4_div_ck",
2959         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2960 };
2961
2962 /* l4_wkup -> timer1 */
2963 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
2964         .master         = &omap44xx_l4_wkup_hwmod,
2965         .slave          = &omap44xx_timer1_hwmod,
2966         .clk            = "l4_wkup_clk_mux_ck",
2967         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2968 };
2969
2970 /* l4_per -> timer2 */
2971 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
2972         .master         = &omap44xx_l4_per_hwmod,
2973         .slave          = &omap44xx_timer2_hwmod,
2974         .clk            = "l4_div_ck",
2975         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2976 };
2977
2978 /* l4_per -> timer3 */
2979 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
2980         .master         = &omap44xx_l4_per_hwmod,
2981         .slave          = &omap44xx_timer3_hwmod,
2982         .clk            = "l4_div_ck",
2983         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2984 };
2985
2986 /* l4_per -> timer4 */
2987 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
2988         .master         = &omap44xx_l4_per_hwmod,
2989         .slave          = &omap44xx_timer4_hwmod,
2990         .clk            = "l4_div_ck",
2991         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2992 };
2993
2994 /* l4_abe -> timer5 */
2995 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
2996         .master         = &omap44xx_l4_abe_hwmod,
2997         .slave          = &omap44xx_timer5_hwmod,
2998         .clk            = "ocp_abe_iclk",
2999         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3000 };
3001
3002 /* l4_abe -> timer6 */
3003 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
3004         .master         = &omap44xx_l4_abe_hwmod,
3005         .slave          = &omap44xx_timer6_hwmod,
3006         .clk            = "ocp_abe_iclk",
3007         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3008 };
3009
3010 /* l4_abe -> timer7 */
3011 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
3012         .master         = &omap44xx_l4_abe_hwmod,
3013         .slave          = &omap44xx_timer7_hwmod,
3014         .clk            = "ocp_abe_iclk",
3015         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3016 };
3017
3018 /* l4_abe -> timer8 */
3019 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
3020         .master         = &omap44xx_l4_abe_hwmod,
3021         .slave          = &omap44xx_timer8_hwmod,
3022         .clk            = "ocp_abe_iclk",
3023         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3024 };
3025
3026 /* l4_per -> timer9 */
3027 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
3028         .master         = &omap44xx_l4_per_hwmod,
3029         .slave          = &omap44xx_timer9_hwmod,
3030         .clk            = "l4_div_ck",
3031         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3032 };
3033
3034 /* l4_per -> timer10 */
3035 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
3036         .master         = &omap44xx_l4_per_hwmod,
3037         .slave          = &omap44xx_timer10_hwmod,
3038         .clk            = "l4_div_ck",
3039         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3040 };
3041
3042 /* l4_per -> timer11 */
3043 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
3044         .master         = &omap44xx_l4_per_hwmod,
3045         .slave          = &omap44xx_timer11_hwmod,
3046         .clk            = "l4_div_ck",
3047         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3048 };
3049
3050 /* l4_cfg -> usb_host_fs */
3051 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_cfg__usb_host_fs = {
3052         .master         = &omap44xx_l4_cfg_hwmod,
3053         .slave          = &omap44xx_usb_host_fs_hwmod,
3054         .clk            = "l4_div_ck",
3055         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3056 };
3057
3058 /* l4_cfg -> usb_host_hs */
3059 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = {
3060         .master         = &omap44xx_l4_cfg_hwmod,
3061         .slave          = &omap44xx_usb_host_hs_hwmod,
3062         .clk            = "l4_div_ck",
3063         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3064 };
3065
3066 /* l4_cfg -> usb_otg_hs */
3067 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = {
3068         .master         = &omap44xx_l4_cfg_hwmod,
3069         .slave          = &omap44xx_usb_otg_hs_hwmod,
3070         .clk            = "l4_div_ck",
3071         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3072 };
3073
3074 /* l4_cfg -> usb_tll_hs */
3075 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = {
3076         .master         = &omap44xx_l4_cfg_hwmod,
3077         .slave          = &omap44xx_usb_tll_hs_hwmod,
3078         .clk            = "l4_div_ck",
3079         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3080 };
3081
3082 /* mpu -> emif1 */
3083 static struct omap_hwmod_ocp_if omap44xx_mpu__emif1 = {
3084         .master         = &omap44xx_mpu_hwmod,
3085         .slave          = &omap44xx_emif1_hwmod,
3086         .clk            = "l3_div_ck",
3087         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3088 };
3089
3090 /* mpu -> emif2 */
3091 static struct omap_hwmod_ocp_if omap44xx_mpu__emif2 = {
3092         .master         = &omap44xx_mpu_hwmod,
3093         .slave          = &omap44xx_emif2_hwmod,
3094         .clk            = "l3_div_ck",
3095         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3096 };
3097
3098 static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
3099         &omap44xx_l3_main_1__dmm,
3100         &omap44xx_mpu__dmm,
3101         &omap44xx_iva__l3_instr,
3102         &omap44xx_l3_main_3__l3_instr,
3103         &omap44xx_ocp_wp_noc__l3_instr,
3104         &omap44xx_dsp__l3_main_1,
3105         &omap44xx_dss__l3_main_1,
3106         &omap44xx_l3_main_2__l3_main_1,
3107         &omap44xx_l4_cfg__l3_main_1,
3108         &omap44xx_mpu__l3_main_1,
3109         &omap44xx_debugss__l3_main_2,
3110         &omap44xx_dma_system__l3_main_2,
3111         &omap44xx_fdif__l3_main_2,
3112         &omap44xx_hsi__l3_main_2,
3113         &omap44xx_ipu__l3_main_2,
3114         &omap44xx_iss__l3_main_2,
3115         &omap44xx_iva__l3_main_2,
3116         &omap44xx_l3_main_1__l3_main_2,
3117         &omap44xx_l4_cfg__l3_main_2,
3118         /* &omap44xx_usb_host_fs__l3_main_2, */
3119         &omap44xx_usb_host_hs__l3_main_2,
3120         &omap44xx_usb_otg_hs__l3_main_2,
3121         &omap44xx_l3_main_1__l3_main_3,
3122         &omap44xx_l3_main_2__l3_main_3,
3123         &omap44xx_l4_cfg__l3_main_3,
3124         &omap44xx_aess__l4_abe,
3125         &omap44xx_dsp__l4_abe,
3126         &omap44xx_l3_main_1__l4_abe,
3127         &omap44xx_mpu__l4_abe,
3128         &omap44xx_l3_main_1__l4_cfg,
3129         &omap44xx_l3_main_2__l4_per,
3130         &omap44xx_l4_cfg__l4_wkup,
3131         &omap44xx_mpu__mpu_private,
3132         &omap44xx_l4_cfg__ocp_wp_noc,
3133         &omap44xx_l4_abe__aess,
3134         &omap44xx_l4_abe__aess_dma,
3135         &omap44xx_l4_wkup__counter_32k,
3136         &omap44xx_l4_cfg__ctrl_module_core,
3137         &omap44xx_l4_cfg__ctrl_module_pad_core,
3138         &omap44xx_l4_wkup__ctrl_module_wkup,
3139         &omap44xx_l4_wkup__ctrl_module_pad_wkup,
3140         &omap44xx_l3_instr__debugss,
3141         &omap44xx_l4_cfg__dma_system,
3142         &omap44xx_l4_abe__dmic,
3143         &omap44xx_dsp__iva,
3144         /* &omap44xx_dsp__sl2if, */
3145         &omap44xx_l4_cfg__dsp,
3146         &omap44xx_l3_main_2__dss,
3147         &omap44xx_l4_per__dss,
3148         &omap44xx_l3_main_2__dss_dispc,
3149         &omap44xx_l4_per__dss_dispc,
3150         &omap44xx_l3_main_2__dss_dsi1,
3151         &omap44xx_l4_per__dss_dsi1,
3152         &omap44xx_l3_main_2__dss_dsi2,
3153         &omap44xx_l4_per__dss_dsi2,
3154         &omap44xx_l3_main_2__dss_hdmi,
3155         &omap44xx_l4_per__dss_hdmi,
3156         &omap44xx_l3_main_2__dss_rfbi,
3157         &omap44xx_l4_per__dss_rfbi,
3158         &omap44xx_l3_main_2__dss_venc,
3159         &omap44xx_l4_per__dss_venc,
3160         &omap44xx_l4_per__elm,
3161         &omap44xx_l4_cfg__fdif,
3162         &omap44xx_l3_main_2__gpmc,
3163         &omap44xx_l4_per__hdq1w,
3164         &omap44xx_l4_cfg__hsi,
3165         &omap44xx_l3_main_2__ipu,
3166         &omap44xx_l3_main_2__iss,
3167         /* &omap44xx_iva__sl2if, */
3168         &omap44xx_l3_main_2__iva,
3169         &omap44xx_l4_wkup__kbd,
3170         &omap44xx_l4_abe__mcasp,
3171         &omap44xx_l4_abe__mcasp_dma,
3172         &omap44xx_l4_abe__mcpdm,
3173         &omap44xx_l3_main_2__mmu_ipu,
3174         &omap44xx_l4_cfg__mmu_dsp,
3175         &omap44xx_l3_main_2__ocmc_ram,
3176         &omap44xx_l4_cfg__ocp2scp_usb_phy,
3177         &omap44xx_mpu_private__prcm_mpu,
3178         &omap44xx_l4_wkup__cm_core_aon,
3179         &omap44xx_l4_cfg__cm_core,
3180         &omap44xx_l4_wkup__prm,
3181         &omap44xx_l4_wkup__scrm,
3182         /* &omap44xx_l3_main_2__sl2if, */
3183         &omap44xx_l4_abe__slimbus1,
3184         &omap44xx_l4_abe__slimbus1_dma,
3185         &omap44xx_l4_per__slimbus2,
3186         &omap44xx_l4_cfg__smartreflex_core,
3187         &omap44xx_l4_cfg__smartreflex_iva,
3188         &omap44xx_l4_cfg__smartreflex_mpu,
3189         &omap44xx_l4_cfg__spinlock,
3190         &omap44xx_l4_wkup__timer1,
3191         &omap44xx_l4_per__timer2,
3192         &omap44xx_l4_per__timer3,
3193         &omap44xx_l4_per__timer4,
3194         &omap44xx_l4_abe__timer5,
3195         &omap44xx_l4_abe__timer6,
3196         &omap44xx_l4_abe__timer7,
3197         &omap44xx_l4_abe__timer8,
3198         &omap44xx_l4_per__timer9,
3199         &omap44xx_l4_per__timer10,
3200         &omap44xx_l4_per__timer11,
3201         /* &omap44xx_l4_cfg__usb_host_fs, */
3202         &omap44xx_l4_cfg__usb_host_hs,
3203         &omap44xx_l4_cfg__usb_otg_hs,
3204         &omap44xx_l4_cfg__usb_tll_hs,
3205         &omap44xx_mpu__emif1,
3206         &omap44xx_mpu__emif2,
3207         &omap44xx_l3_main_2__aes1,
3208         &omap44xx_l3_main_2__aes2,
3209         &omap44xx_l3_main_2__des,
3210         &omap44xx_l3_main_2__sha0,
3211         NULL,
3212 };
3213
3214 int __init omap44xx_hwmod_init(void)
3215 {
3216         omap_hwmod_init();
3217         return omap_hwmod_register_links(omap44xx_hwmod_ocp_ifs);
3218 }
3219