arch/arm/mach-omap2/omap_hwmod_44xx_data.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Hardware modules present on the OMAP44xx chips
   4  *
   5  * Copyright (C) 2009-2012 Texas Instruments, Inc.
   6  * Copyright (C) 2009-2010 Nokia Corporation
   7  *
   8  * Paul Walmsley
   9  * Benoit Cousson
  10  *
  11  * This file is automatically generated from the OMAP hardware databases.
  12  * We respectfully ask that any modifications to this file be coordinated
  13  * with the public linux-omap@vger.kernel.org mailing list and the
  14  * authors above to ensure that the autogeneration scripts are kept
  15  * up-to-date with the file contents.
  16  * Note that this file is currently not in sync with autogeneration scripts.
  17  * The above note to be removed, once it is synced up.
  18  */
  19
  20 #include <linux/io.h>
  21
  22 #include "omap_hwmod.h"
  23 #include "omap_hwmod_common_data.h"
  24 #include "cm1_44xx.h"
  25 #include "cm2_44xx.h"
  26 #include "prm44xx.h"
  27 #include "prm-regbits-44xx.h"
  28
  29 /* Base offset for all OMAP4 interrupts external to MPUSS */
  30 #define OMAP44XX_IRQ_GIC_START  32
  31
  32 /*
  33  * IP blocks
  34  */
  35
  36 /*
  37  * 'dmm' class
  38  * instance(s): dmm
  39  */
  40 static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
  41         .name   = "dmm",
  42 };
  43
  44 /* dmm */
  45 static struct omap_hwmod omap44xx_dmm_hwmod = {
  46         .name           = "dmm",
  47         .class          = &omap44xx_dmm_hwmod_class,
  48         .clkdm_name     = "l3_emif_clkdm",
  49         .prcm = {
  50                 .omap4 = {
  51                         .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET,
  52                         .context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET,
  53                 },
  54         },
  55 };
  56
  57 /*
  58  * 'l3' class
  59  * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
  60  */
  61 static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
  62         .name   = "l3",
  63 };
  64
  65 /* l3_instr */
  66 static struct omap_hwmod omap44xx_l3_instr_hwmod = {
  67         .name           = "l3_instr",
  68         .class          = &omap44xx_l3_hwmod_class,
  69         .clkdm_name     = "l3_instr_clkdm",
  70         .prcm = {
  71                 .omap4 = {
  72                         .clkctrl_offs = OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
  73                         .context_offs = OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
  74                         .modulemode   = MODULEMODE_HWCTRL,
  75                 },
  76         },
  77 };
  78
  79 /* l3_main_1 */
  80 static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
  81         .name           = "l3_main_1",
  82         .class          = &omap44xx_l3_hwmod_class,
  83         .clkdm_name     = "l3_1_clkdm",
  84         .prcm = {
  85                 .omap4 = {
  86                         .clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET,
  87                         .context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET,
  88                 },
  89         },
  90 };
  91
  92 /* l3_main_2 */
  93 static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
  94         .name           = "l3_main_2",
  95         .class          = &omap44xx_l3_hwmod_class,
  96         .clkdm_name     = "l3_2_clkdm",
  97         .prcm = {
  98                 .omap4 = {
  99                         .clkctrl_offs = OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET,
 100                         .context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET,
 101                 },
 102         },
 103 };
 104
 105 /* l3_main_3 */
 106 static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
 107         .name           = "l3_main_3",
 108         .class          = &omap44xx_l3_hwmod_class,
 109         .clkdm_name     = "l3_instr_clkdm",
 110         .prcm = {
 111                 .omap4 = {
 112                         .clkctrl_offs = OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET,
 113                         .context_offs = OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET,
 114                         .modulemode   = MODULEMODE_HWCTRL,
 115                 },
 116         },
 117 };
 118
 119 /*
 120  * 'l4' class
 121  * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
 122  */
 123 static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
 124         .name   = "l4",
 125 };
 126
 127 /* l4_abe */
 128 static struct omap_hwmod omap44xx_l4_abe_hwmod = {
 129         .name           = "l4_abe",
 130         .class          = &omap44xx_l4_hwmod_class,
 131         .clkdm_name     = "abe_clkdm",
 132         .prcm = {
 133                 .omap4 = {
 134                         .clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET,
 135                         .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
 136                         .lostcontext_mask = OMAP4430_LOSTMEM_AESSMEM_MASK,
 137                         .flags        = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 138                 },
 139         },
 140 };
 141
 142 /* l4_cfg */
 143 static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
 144         .name           = "l4_cfg",
 145         .class          = &omap44xx_l4_hwmod_class,
 146         .clkdm_name     = "l4_cfg_clkdm",
 147         .prcm = {
 148                 .omap4 = {
 149                         .clkctrl_offs = OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
 150                         .context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
 151                 },
 152         },
 153 };
 154
 155 /* l4_per */
 156 static struct omap_hwmod omap44xx_l4_per_hwmod = {
 157         .name           = "l4_per",
 158         .class          = &omap44xx_l4_hwmod_class,
 159         .clkdm_name     = "l4_per_clkdm",
 160         .prcm = {
 161                 .omap4 = {
 162                         .clkctrl_offs = OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET,
 163                         .context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET,
 164                 },
 165         },
 166 };
 167
 168 /* l4_wkup */
 169 static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
 170         .name           = "l4_wkup",
 171         .class          = &omap44xx_l4_hwmod_class,
 172         .clkdm_name     = "l4_wkup_clkdm",
 173         .prcm = {
 174                 .omap4 = {
 175                         .clkctrl_offs = OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
 176                         .context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET,
 177                 },
 178         },
 179 };
 180
 181 /*
 182  * 'mpu_bus' class
 183  * instance(s): mpu_private
 184  */
 185 static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
 186         .name   = "mpu_bus",
 187 };
 188
 189 /* mpu_private */
 190 static struct omap_hwmod omap44xx_mpu_private_hwmod = {
 191         .name           = "mpu_private",
 192         .class          = &omap44xx_mpu_bus_hwmod_class,
 193         .clkdm_name     = "mpuss_clkdm",
 194         .prcm = {
 195                 .omap4 = {
 196                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 197                 },
 198         },
 199 };
 200
 201 /*
 202  * 'ocp_wp_noc' class
 203  * instance(s): ocp_wp_noc
 204  */
 205 static struct omap_hwmod_class omap44xx_ocp_wp_noc_hwmod_class = {
 206         .name   = "ocp_wp_noc",
 207 };
 208
 209 /* ocp_wp_noc */
 210 static struct omap_hwmod omap44xx_ocp_wp_noc_hwmod = {
 211         .name           = "ocp_wp_noc",
 212         .class          = &omap44xx_ocp_wp_noc_hwmod_class,
 213         .clkdm_name     = "l3_instr_clkdm",
 214         .prcm = {
 215                 .omap4 = {
 216                         .clkctrl_offs = OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET,
 217                         .context_offs = OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET,
 218                         .modulemode   = MODULEMODE_HWCTRL,
 219                 },
 220         },
 221 };
 222
 223 /*
 224  * Modules omap_hwmod structures
 225  *
 226  * The following IPs are excluded for the moment because:
 227  * - They do not need an explicit SW control using omap_hwmod API.
 228  * - They still need to be validated with the driver
 229  *   properly adapted to omap_hwmod / omap_device
 230  *
 231  * usim
 232  */
 233
 234 /*
 235  * 'counter' class
 236  * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
 237  */
 238
 239 static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = {
 240         .rev_offs       = 0x0000,
 241         .sysc_offs      = 0x0004,
 242         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 243         .idlemodes      = (SIDLE_FORCE | SIDLE_NO),
 244         .sysc_fields    = &omap_hwmod_sysc_type1,
 245 };
 246
 247 static struct omap_hwmod_class omap44xx_counter_hwmod_class = {
 248         .name   = "counter",
 249         .sysc   = &omap44xx_counter_sysc,
 250 };
 251
 252 /* counter_32k */
 253 static struct omap_hwmod omap44xx_counter_32k_hwmod = {
 254         .name           = "counter_32k",
 255         .class          = &omap44xx_counter_hwmod_class,
 256         .clkdm_name     = "l4_wkup_clkdm",
 257         .flags          = HWMOD_SWSUP_SIDLE,
 258         .main_clk       = "sys_32k_ck",
 259         .prcm = {
 260                 .omap4 = {
 261                         .clkctrl_offs = OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
 262                         .context_offs = OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET,
 263                 },
 264         },
 265 };
 266
 267 /*
 268  * 'ctrl_module' class
 269  * attila core control module + core pad control module + wkup pad control
 270  * module + attila wkup control module
 271  */
 272
 273 static struct omap_hwmod_class_sysconfig omap44xx_ctrl_module_sysc = {
 274         .rev_offs       = 0x0000,
 275         .sysc_offs      = 0x0010,
 276         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 277         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 278                            SIDLE_SMART_WKUP),
 279         .sysc_fields    = &omap_hwmod_sysc_type2,
 280 };
 281
 282 static struct omap_hwmod_class omap44xx_ctrl_module_hwmod_class = {
 283         .name   = "ctrl_module",
 284         .sysc   = &omap44xx_ctrl_module_sysc,
 285 };
 286
 287 /* ctrl_module_core */
 288 static struct omap_hwmod omap44xx_ctrl_module_core_hwmod = {
 289         .name           = "ctrl_module_core",
 290         .class          = &omap44xx_ctrl_module_hwmod_class,
 291         .clkdm_name     = "l4_cfg_clkdm",
 292         .prcm = {
 293                 .omap4 = {
 294                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 295                 },
 296         },
 297 };
 298
 299 /* ctrl_module_pad_core */
 300 static struct omap_hwmod omap44xx_ctrl_module_pad_core_hwmod = {
 301         .name           = "ctrl_module_pad_core",
 302         .class          = &omap44xx_ctrl_module_hwmod_class,
 303         .clkdm_name     = "l4_cfg_clkdm",
 304         .prcm = {
 305                 .omap4 = {
 306                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 307                 },
 308         },
 309 };
 310
 311 /* ctrl_module_wkup */
 312 static struct omap_hwmod omap44xx_ctrl_module_wkup_hwmod = {
 313         .name           = "ctrl_module_wkup",
 314         .class          = &omap44xx_ctrl_module_hwmod_class,
 315         .clkdm_name     = "l4_wkup_clkdm",
 316         .prcm = {
 317                 .omap4 = {
 318                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 319                 },
 320         },
 321 };
 322
 323 /* ctrl_module_pad_wkup */
 324 static struct omap_hwmod omap44xx_ctrl_module_pad_wkup_hwmod = {
 325         .name           = "ctrl_module_pad_wkup",
 326         .class          = &omap44xx_ctrl_module_hwmod_class,
 327         .clkdm_name     = "l4_wkup_clkdm",
 328         .prcm = {
 329                 .omap4 = {
 330                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 331                 },
 332         },
 333 };
 334
 335 /*
 336  * 'debugss' class
 337  * debug and emulation sub system
 338  */
 339
 340 static struct omap_hwmod_class omap44xx_debugss_hwmod_class = {
 341         .name   = "debugss",
 342 };
 343
 344 /* debugss */
 345 static struct omap_hwmod omap44xx_debugss_hwmod = {
 346         .name           = "debugss",
 347         .class          = &omap44xx_debugss_hwmod_class,
 348         .clkdm_name     = "emu_sys_clkdm",
 349         .main_clk       = "trace_clk_div_ck",
 350         .prcm = {
 351                 .omap4 = {
 352                         .clkctrl_offs = OMAP4_CM_EMU_DEBUGSS_CLKCTRL_OFFSET,
 353                         .context_offs = OMAP4_RM_EMU_DEBUGSS_CONTEXT_OFFSET,
 354                 },
 355         },
 356 };
 357
 358 /*
 359  * 'dsp' class
 360  * dsp sub-system
 361  */
 362
 363 static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
 364         .name   = "dsp",
 365 };
 366
 367 /* dsp */
 368 static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
 369         { .name = "dsp", .rst_shift = 0 },
 370 };
 371
 372 static struct omap_hwmod omap44xx_dsp_hwmod = {
 373         .name           = "dsp",
 374         .class          = &omap44xx_dsp_hwmod_class,
 375         .clkdm_name     = "tesla_clkdm",
 376         .rst_lines      = omap44xx_dsp_resets,
 377         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_dsp_resets),
 378         .main_clk       = "dpll_iva_m4x2_ck",
 379         .prcm = {
 380                 .omap4 = {
 381                         .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
 382                         .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
 383                         .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
 384                         .modulemode   = MODULEMODE_HWCTRL,
 385                 },
 386         },
 387 };
 388
 389 /*
 390  * 'dss' class
 391  * display sub-system
 392  */
 393
 394 static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = {
 395         .rev_offs       = 0x0000,
 396         .syss_offs      = 0x0014,
 397         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 398 };
 399
 400 static struct omap_hwmod_class omap44xx_dss_hwmod_class = {
 401         .name   = "dss",
 402         .sysc   = &omap44xx_dss_sysc,
 403         .reset  = omap_dss_reset,
 404 };
 405
 406 /* dss */
 407 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
 408         { .role = "sys_clk", .clk = "dss_sys_clk" },
 409         { .role = "tv_clk", .clk = "dss_tv_clk" },
 410         { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
 411 };
 412
 413 static struct omap_hwmod omap44xx_dss_hwmod = {
 414         .name           = "dss_core",
 415         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 416         .class          = &omap44xx_dss_hwmod_class,
 417         .clkdm_name     = "l3_dss_clkdm",
 418         .main_clk       = "dss_dss_clk",
 419         .prcm = {
 420                 .omap4 = {
 421                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 422                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 423                         .modulemode   = MODULEMODE_SWCTRL,
 424                 },
 425         },
 426         .opt_clks       = dss_opt_clks,
 427         .opt_clks_cnt   = ARRAY_SIZE(dss_opt_clks),
 428 };
 429
 430 /*
 431  * 'dispc' class
 432  * display controller
 433  */
 434
 435 static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = {
 436         .rev_offs       = 0x0000,
 437         .sysc_offs      = 0x0010,
 438         .syss_offs      = 0x0014,
 439         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 440                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
 441                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 442                            SYSS_HAS_RESET_STATUS),
 443         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 444                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 445         .sysc_fields    = &omap_hwmod_sysc_type1,
 446 };
 447
 448 static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
 449         .name   = "dispc",
 450         .sysc   = &omap44xx_dispc_sysc,
 451 };
 452
 453 /* dss_dispc */
 454 static struct omap_dss_dispc_dev_attr omap44xx_dss_dispc_dev_attr = {
 455         .manager_count          = 3,
 456         .has_framedonetv_irq    = 1
 457 };
 458
 459 static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
 460         .name           = "dss_dispc",
 461         .class          = &omap44xx_dispc_hwmod_class,
 462         .clkdm_name     = "l3_dss_clkdm",
 463         .main_clk       = "dss_dss_clk",
 464         .prcm = {
 465                 .omap4 = {
 466                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 467                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 468                 },
 469         },
 470         .dev_attr       = &omap44xx_dss_dispc_dev_attr,
 471         .parent_hwmod   = &omap44xx_dss_hwmod,
 472 };
 473
 474 /*
 475  * 'dsi' class
 476  * display serial interface controller
 477  */
 478
 479 static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = {
 480         .rev_offs       = 0x0000,
 481         .sysc_offs      = 0x0010,
 482         .syss_offs      = 0x0014,
 483         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 484                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 485                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 486         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 487         .sysc_fields    = &omap_hwmod_sysc_type1,
 488 };
 489
 490 static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
 491         .name   = "dsi",
 492         .sysc   = &omap44xx_dsi_sysc,
 493 };
 494
 495 /* dss_dsi1 */
 496 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
 497         { .role = "sys_clk", .clk = "dss_sys_clk" },
 498 };
 499
 500 static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
 501         .name           = "dss_dsi1",
 502         .class          = &omap44xx_dsi_hwmod_class,
 503         .clkdm_name     = "l3_dss_clkdm",
 504         .main_clk       = "dss_dss_clk",
 505         .prcm = {
 506                 .omap4 = {
 507                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 508                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 509                 },
 510         },
 511         .opt_clks       = dss_dsi1_opt_clks,
 512         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi1_opt_clks),
 513         .parent_hwmod   = &omap44xx_dss_hwmod,
 514 };
 515
 516 /* dss_dsi2 */
 517 static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = {
 518         { .role = "sys_clk", .clk = "dss_sys_clk" },
 519 };
 520
 521 static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
 522         .name           = "dss_dsi2",
 523         .class          = &omap44xx_dsi_hwmod_class,
 524         .clkdm_name     = "l3_dss_clkdm",
 525         .main_clk       = "dss_dss_clk",
 526         .prcm = {
 527                 .omap4 = {
 528                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 529                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 530                 },
 531         },
 532         .opt_clks       = dss_dsi2_opt_clks,
 533         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi2_opt_clks),
 534         .parent_hwmod   = &omap44xx_dss_hwmod,
 535 };
 536
 537 /*
 538  * 'hdmi' class
 539  * hdmi controller
 540  */
 541
 542 static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = {
 543         .rev_offs       = 0x0000,
 544         .sysc_offs      = 0x0010,
 545         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
 546                            SYSC_HAS_SOFTRESET),
 547         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 548                            SIDLE_SMART_WKUP),
 549         .sysc_fields    = &omap_hwmod_sysc_type2,
 550 };
 551
 552 static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
 553         .name   = "hdmi",
 554         .sysc   = &omap44xx_hdmi_sysc,
 555 };
 556
 557 /* dss_hdmi */
 558 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
 559         { .role = "sys_clk", .clk = "dss_sys_clk" },
 560         { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
 561 };
 562
 563 static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
 564         .name           = "dss_hdmi",
 565         .class          = &omap44xx_hdmi_hwmod_class,
 566         .clkdm_name     = "l3_dss_clkdm",
 567         /*
 568          * HDMI audio requires to use no-idle mode. Hence,
 569          * set idle mode by software.
 570          */
 571         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_OPT_CLKS_NEEDED,
 572         .main_clk       = "dss_48mhz_clk",
 573         .prcm = {
 574                 .omap4 = {
 575                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 576                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 577                 },
 578         },
 579         .opt_clks       = dss_hdmi_opt_clks,
 580         .opt_clks_cnt   = ARRAY_SIZE(dss_hdmi_opt_clks),
 581         .parent_hwmod   = &omap44xx_dss_hwmod,
 582 };
 583
 584 /*
 585  * 'rfbi' class
 586  * remote frame buffer interface
 587  */
 588
 589 static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = {
 590         .rev_offs       = 0x0000,
 591         .sysc_offs      = 0x0010,
 592         .syss_offs      = 0x0014,
 593         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
 594                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 595         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 596         .sysc_fields    = &omap_hwmod_sysc_type1,
 597 };
 598
 599 static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
 600         .name   = "rfbi",
 601         .sysc   = &omap44xx_rfbi_sysc,
 602 };
 603
 604 /* dss_rfbi */
 605 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
 606         { .role = "ick", .clk = "l3_div_ck" },
 607 };
 608
 609 static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
 610         .name           = "dss_rfbi",
 611         .class          = &omap44xx_rfbi_hwmod_class,
 612         .clkdm_name     = "l3_dss_clkdm",
 613         .main_clk       = "dss_dss_clk",
 614         .prcm = {
 615                 .omap4 = {
 616                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 617                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 618                 },
 619         },
 620         .opt_clks       = dss_rfbi_opt_clks,
 621         .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
 622         .parent_hwmod   = &omap44xx_dss_hwmod,
 623 };
 624
 625 /*
 626  * 'venc' class
 627  * video encoder
 628  */
 629
 630 static struct omap_hwmod_class omap44xx_venc_hwmod_class = {
 631         .name   = "venc",
 632 };
 633
 634 /* dss_venc */
 635 static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = {
 636         { .role = "tv_clk", .clk = "dss_tv_clk" },
 637 };
 638
 639 static struct omap_hwmod omap44xx_dss_venc_hwmod = {
 640         .name           = "dss_venc",
 641         .class          = &omap44xx_venc_hwmod_class,
 642         .clkdm_name     = "l3_dss_clkdm",
 643         .main_clk       = "dss_tv_clk",
 644         .flags          = HWMOD_OPT_CLKS_NEEDED,
 645         .prcm = {
 646                 .omap4 = {
 647                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 648                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 649                 },
 650         },
 651         .parent_hwmod   = &omap44xx_dss_hwmod,
 652         .opt_clks       = dss_venc_opt_clks,
 653         .opt_clks_cnt   = ARRAY_SIZE(dss_venc_opt_clks),
 654 };
 655
 656 /* sha0 HIB2 (the 'P' (public) device) */
 657 static struct omap_hwmod_class_sysconfig omap44xx_sha0_sysc = {
 658         .rev_offs       = 0x100,
 659         .sysc_offs      = 0x110,
 660         .syss_offs      = 0x114,
 661         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 662 };
 663
 664 static struct omap_hwmod_class omap44xx_sha0_hwmod_class = {
 665         .name           = "sham",
 666         .sysc           = &omap44xx_sha0_sysc,
 667 };
 668
 669 static struct omap_hwmod omap44xx_sha0_hwmod = {
 670         .name           = "sham",
 671         .class          = &omap44xx_sha0_hwmod_class,
 672         .clkdm_name     = "l4_secure_clkdm",
 673         .main_clk       = "l3_div_ck",
 674         .prcm           = {
 675                 .omap4 = {
 676                         .clkctrl_offs = OMAP4_CM_L4SEC_SHA2MD51_CLKCTRL_OFFSET,
 677                         .context_offs = OMAP4_RM_L4SEC_SHA2MD51_CONTEXT_OFFSET,
 678                         .modulemode   = MODULEMODE_SWCTRL,
 679                 },
 680         },
 681 };
 682
 683
 684 /*
 685  * 'emif' class
 686  * external memory interface no1
 687  */
 688
 689 static struct omap_hwmod_class_sysconfig omap44xx_emif_sysc = {
 690         .rev_offs       = 0x0000,
 691 };
 692
 693 static struct omap_hwmod_class omap44xx_emif_hwmod_class = {
 694         .name   = "emif",
 695         .sysc   = &omap44xx_emif_sysc,
 696 };
 697
 698 /* emif1 */
 699 static struct omap_hwmod omap44xx_emif1_hwmod = {
 700         .name           = "emif1",
 701         .class          = &omap44xx_emif_hwmod_class,
 702         .clkdm_name     = "l3_emif_clkdm",
 703         .flags          = HWMOD_INIT_NO_IDLE,
 704         .main_clk       = "ddrphy_ck",
 705         .prcm = {
 706                 .omap4 = {
 707                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET,
 708                         .context_offs = OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET,
 709                         .modulemode   = MODULEMODE_HWCTRL,
 710                 },
 711         },
 712 };
 713
 714 /* emif2 */
 715 static struct omap_hwmod omap44xx_emif2_hwmod = {
 716         .name           = "emif2",
 717         .class          = &omap44xx_emif_hwmod_class,
 718         .clkdm_name     = "l3_emif_clkdm",
 719         .flags          = HWMOD_INIT_NO_IDLE,
 720         .main_clk       = "ddrphy_ck",
 721         .prcm = {
 722                 .omap4 = {
 723                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET,
 724                         .context_offs = OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET,
 725                         .modulemode   = MODULEMODE_HWCTRL,
 726                 },
 727         },
 728 };
 729
 730 /*
 731     Crypto modules AES0/1 belong to:
 732         PD_L4_PER power domain
 733         CD_L4_SEC clock domain
 734         On the L3, the AES modules are mapped to
 735         L3_CLK2: Peripherals and multimedia sub clock domain
 736 */
 737 static struct omap_hwmod_class_sysconfig omap44xx_aes_sysc = {
 738         .rev_offs       = 0x80,
 739         .sysc_offs      = 0x84,
 740         .syss_offs      = 0x88,
 741         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 742 };
 743
 744 static struct omap_hwmod_class omap44xx_aes_hwmod_class = {
 745         .name           = "aes",
 746         .sysc           = &omap44xx_aes_sysc,
 747 };
 748
 749 static struct omap_hwmod omap44xx_aes1_hwmod = {
 750         .name           = "aes1",
 751         .class          = &omap44xx_aes_hwmod_class,
 752         .clkdm_name     = "l4_secure_clkdm",
 753         .main_clk       = "l3_div_ck",
 754         .prcm           = {
 755                 .omap4  = {
 756                         .context_offs   = OMAP4_RM_L4SEC_AES1_CONTEXT_OFFSET,
 757                         .clkctrl_offs   = OMAP4_CM_L4SEC_AES1_CLKCTRL_OFFSET,
 758                         .modulemode     = MODULEMODE_SWCTRL,
 759                 },
 760         },
 761 };
 762
 763 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__aes1 = {
 764         .master         = &omap44xx_l4_per_hwmod,
 765         .slave          = &omap44xx_aes1_hwmod,
 766         .clk            = "l3_div_ck",
 767         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 768 };
 769
 770 static struct omap_hwmod omap44xx_aes2_hwmod = {
 771         .name           = "aes2",
 772         .class          = &omap44xx_aes_hwmod_class,
 773         .clkdm_name     = "l4_secure_clkdm",
 774         .main_clk       = "l3_div_ck",
 775         .prcm           = {
 776                 .omap4  = {
 777                         .context_offs   = OMAP4_RM_L4SEC_AES2_CONTEXT_OFFSET,
 778                         .clkctrl_offs   = OMAP4_CM_L4SEC_AES2_CLKCTRL_OFFSET,
 779                         .modulemode     = MODULEMODE_SWCTRL,
 780                 },
 781         },
 782 };
 783
 784 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__aes2 = {
 785         .master         = &omap44xx_l4_per_hwmod,
 786         .slave          = &omap44xx_aes2_hwmod,
 787         .clk            = "l3_div_ck",
 788         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 789 };
 790
 791 /*
 792  * 'des' class for DES3DES module
 793  */
 794 static struct omap_hwmod_class_sysconfig omap44xx_des_sysc = {
 795         .rev_offs       = 0x30,
 796         .sysc_offs      = 0x34,
 797         .syss_offs      = 0x38,
 798         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 799 };
 800
 801 static struct omap_hwmod_class omap44xx_des_hwmod_class = {
 802         .name           = "des",
 803         .sysc           = &omap44xx_des_sysc,
 804 };
 805
 806 static struct omap_hwmod omap44xx_des_hwmod = {
 807         .name           = "des",
 808         .class          = &omap44xx_des_hwmod_class,
 809         .clkdm_name     = "l4_secure_clkdm",
 810         .main_clk       = "l3_div_ck",
 811         .prcm           = {
 812                 .omap4  = {
 813                         .context_offs   = OMAP4_RM_L4SEC_DES3DES_CONTEXT_OFFSET,
 814                         .clkctrl_offs   = OMAP4_CM_L4SEC_DES3DES_CLKCTRL_OFFSET,
 815                         .modulemode     = MODULEMODE_SWCTRL,
 816                 },
 817         },
 818 };
 819
 820 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__des = {
 821         .master         = &omap44xx_l3_main_2_hwmod,
 822         .slave          = &omap44xx_des_hwmod,
 823         .clk            = "l3_div_ck",
 824         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 825 };
 826
 827 /*
 828  * 'gpmc' class
 829  * general purpose memory controller
 830  */
 831
 832 static struct omap_hwmod_class_sysconfig omap44xx_gpmc_sysc = {
 833         .rev_offs       = 0x0000,
 834         .sysc_offs      = 0x0010,
 835         .syss_offs      = 0x0014,
 836         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
 837                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 838         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 839         .sysc_fields    = &omap_hwmod_sysc_type1,
 840 };
 841
 842 static struct omap_hwmod_class omap44xx_gpmc_hwmod_class = {
 843         .name   = "gpmc",
 844         .sysc   = &omap44xx_gpmc_sysc,
 845 };
 846
 847 /* gpmc */
 848 static struct omap_hwmod omap44xx_gpmc_hwmod = {
 849         .name           = "gpmc",
 850         .class          = &omap44xx_gpmc_hwmod_class,
 851         .clkdm_name     = "l3_2_clkdm",
 852         /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
 853         .flags          = DEBUG_OMAP_GPMC_HWMOD_FLAGS,
 854         .prcm = {
 855                 .omap4 = {
 856                         .clkctrl_offs = OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET,
 857                         .context_offs = OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET,
 858                         .modulemode   = MODULEMODE_HWCTRL,
 859                 },
 860         },
 861 };
 862
 863
 864 /*
 865  * 'ipu' class
 866  * imaging processor unit
 867  */
 868
 869 static struct omap_hwmod_class omap44xx_ipu_hwmod_class = {
 870         .name   = "ipu",
 871 };
 872
 873 /* ipu */
 874 static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
 875         { .name = "cpu0", .rst_shift = 0 },
 876         { .name = "cpu1", .rst_shift = 1 },
 877 };
 878
 879 static struct omap_hwmod omap44xx_ipu_hwmod = {
 880         .name           = "ipu",
 881         .class          = &omap44xx_ipu_hwmod_class,
 882         .clkdm_name     = "ducati_clkdm",
 883         .rst_lines      = omap44xx_ipu_resets,
 884         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_ipu_resets),
 885         .main_clk       = "ducati_clk_mux_ck",
 886         .prcm = {
 887                 .omap4 = {
 888                         .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
 889                         .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
 890                         .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
 891                         .modulemode   = MODULEMODE_HWCTRL,
 892                 },
 893         },
 894 };
 895
 896 /*
 897  * 'iss' class
 898  * external images sensor pixel data processor
 899  */
 900
 901 static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = {
 902         .rev_offs       = 0x0000,
 903         .sysc_offs      = 0x0010,
 904         /*
 905          * ISS needs 100 OCP clk cycles delay after a softreset before
 906          * accessing sysconfig again.
 907          * The lowest frequency at the moment for L3 bus is 100 MHz, so
 908          * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
 909          *
 910          * TODO: Indicate errata when available.
 911          */
 912         .srst_udelay    = 2,
 913         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
 914                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
 915         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 916                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
 917                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
 918         .sysc_fields    = &omap_hwmod_sysc_type2,
 919 };
 920
 921 static struct omap_hwmod_class omap44xx_iss_hwmod_class = {
 922         .name   = "iss",
 923         .sysc   = &omap44xx_iss_sysc,
 924 };
 925
 926 /* iss */
 927 static struct omap_hwmod_opt_clk iss_opt_clks[] = {
 928         { .role = "ctrlclk", .clk = "iss_ctrlclk" },
 929 };
 930
 931 static struct omap_hwmod omap44xx_iss_hwmod = {
 932         .name           = "iss",
 933         .class          = &omap44xx_iss_hwmod_class,
 934         .clkdm_name     = "iss_clkdm",
 935         .main_clk       = "ducati_clk_mux_ck",
 936         .prcm = {
 937                 .omap4 = {
 938                         .clkctrl_offs = OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET,
 939                         .context_offs = OMAP4_RM_CAM_ISS_CONTEXT_OFFSET,
 940                         .modulemode   = MODULEMODE_SWCTRL,
 941                 },
 942         },
 943         .opt_clks       = iss_opt_clks,
 944         .opt_clks_cnt   = ARRAY_SIZE(iss_opt_clks),
 945 };
 946
 947 /*
 948  * 'iva' class
 949  * multi-standard video encoder/decoder hardware accelerator
 950  */
 951
 952 static struct omap_hwmod_class omap44xx_iva_hwmod_class = {
 953         .name   = "iva",
 954 };
 955
 956 /* iva */
 957 static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
 958         { .name = "seq0", .rst_shift = 0 },
 959         { .name = "seq1", .rst_shift = 1 },
 960         { .name = "logic", .rst_shift = 2 },
 961 };
 962
 963 static struct omap_hwmod omap44xx_iva_hwmod = {
 964         .name           = "iva",
 965         .class          = &omap44xx_iva_hwmod_class,
 966         .clkdm_name     = "ivahd_clkdm",
 967         .rst_lines      = omap44xx_iva_resets,
 968         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_resets),
 969         .main_clk       = "dpll_iva_m5x2_ck",
 970         .prcm = {
 971                 .omap4 = {
 972                         .clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET,
 973                         .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
 974                         .context_offs = OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET,
 975                         .modulemode   = MODULEMODE_HWCTRL,
 976                 },
 977         },
 978 };
 979
 980 /*
 981  * 'mpu' class
 982  * mpu sub-system
 983  */
 984
 985 static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
 986         .name   = "mpu",
 987 };
 988
 989 /* mpu */
 990 static struct omap_hwmod omap44xx_mpu_hwmod = {
 991         .name           = "mpu",
 992         .class          = &omap44xx_mpu_hwmod_class,
 993         .clkdm_name     = "mpuss_clkdm",
 994         .flags          = HWMOD_INIT_NO_IDLE,
 995         .main_clk       = "dpll_mpu_m2_ck",
 996         .prcm = {
 997                 .omap4 = {
 998                         .clkctrl_offs = OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET,
 999                         .context_offs = OMAP4_RM_MPU_MPU_CONTEXT_OFFSET,
1000                 },
1001         },
1002 };
1003
1004 /*
1005  * 'ocmc_ram' class
1006  * top-level core on-chip ram
1007  */
1008
1009 static struct omap_hwmod_class omap44xx_ocmc_ram_hwmod_class = {
1010         .name   = "ocmc_ram",
1011 };
1012
1013 /* ocmc_ram */
1014 static struct omap_hwmod omap44xx_ocmc_ram_hwmod = {
1015         .name           = "ocmc_ram",
1016         .class          = &omap44xx_ocmc_ram_hwmod_class,
1017         .clkdm_name     = "l3_2_clkdm",
1018         .prcm = {
1019                 .omap4 = {
1020                         .clkctrl_offs = OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET,
1021                         .context_offs = OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET,
1022                 },
1023         },
1024 };
1025
1026
1027 /*
1028  * 'prcm' class
1029  * power and reset manager (part of the prcm infrastructure) + clock manager 2
1030  * + clock manager 1 (in always on power domain) + local prm in mpu
1031  */
1032
1033 static struct omap_hwmod_class omap44xx_prcm_hwmod_class = {
1034         .name   = "prcm",
1035 };
1036
1037 /* prcm_mpu */
1038 static struct omap_hwmod omap44xx_prcm_mpu_hwmod = {
1039         .name           = "prcm_mpu",
1040         .class          = &omap44xx_prcm_hwmod_class,
1041         .clkdm_name     = "l4_wkup_clkdm",
1042         .flags          = HWMOD_NO_IDLEST,
1043         .prcm = {
1044                 .omap4 = {
1045                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
1046                 },
1047         },
1048 };
1049
1050 /* cm_core_aon */
1051 static struct omap_hwmod omap44xx_cm_core_aon_hwmod = {
1052         .name           = "cm_core_aon",
1053         .class          = &omap44xx_prcm_hwmod_class,
1054         .flags          = HWMOD_NO_IDLEST,
1055         .prcm = {
1056                 .omap4 = {
1057                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
1058                 },
1059         },
1060 };
1061
1062 /* cm_core */
1063 static struct omap_hwmod omap44xx_cm_core_hwmod = {
1064         .name           = "cm_core",
1065         .class          = &omap44xx_prcm_hwmod_class,
1066         .flags          = HWMOD_NO_IDLEST,
1067         .prcm = {
1068                 .omap4 = {
1069                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
1070                 },
1071         },
1072 };
1073
1074 /* prm */
1075 static struct omap_hwmod_rst_info omap44xx_prm_resets[] = {
1076         { .name = "rst_global_warm_sw", .rst_shift = 0 },
1077         { .name = "rst_global_cold_sw", .rst_shift = 1 },
1078 };
1079
1080 static struct omap_hwmod omap44xx_prm_hwmod = {
1081         .name           = "prm",
1082         .class          = &omap44xx_prcm_hwmod_class,
1083         .rst_lines      = omap44xx_prm_resets,
1084         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_prm_resets),
1085 };
1086
1087 /*
1088  * 'scrm' class
1089  * system clock and reset manager
1090  */
1091
1092 static struct omap_hwmod_class omap44xx_scrm_hwmod_class = {
1093         .name   = "scrm",
1094 };
1095
1096 /* scrm */
1097 static struct omap_hwmod omap44xx_scrm_hwmod = {
1098         .name           = "scrm",
1099         .class          = &omap44xx_scrm_hwmod_class,
1100         .clkdm_name     = "l4_wkup_clkdm",
1101         .prcm = {
1102                 .omap4 = {
1103                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
1104                 },
1105         },
1106 };
1107
1108 /*
1109  * 'sl2if' class
1110  * shared level 2 memory interface
1111  */
1112
1113 static struct omap_hwmod_class omap44xx_sl2if_hwmod_class = {
1114         .name   = "sl2if",
1115 };
1116
1117 /* sl2if */
1118 static struct omap_hwmod omap44xx_sl2if_hwmod = {
1119         .name           = "sl2if",
1120         .class          = &omap44xx_sl2if_hwmod_class,
1121         .clkdm_name     = "ivahd_clkdm",
1122         .prcm = {
1123                 .omap4 = {
1124                         .clkctrl_offs = OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET,
1125                         .context_offs = OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET,
1126                         .modulemode   = MODULEMODE_HWCTRL,
1127                 },
1128         },
1129 };
1130
1131 /*
1132  * 'timer' class
1133  * general purpose timer module with accurate 1ms tick
1134  * This class contains several variants: ['timer_1ms', 'timer']
1135  */
1136
1137 static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = {
1138         .rev_offs       = 0x0000,
1139         .sysc_offs      = 0x0010,
1140         .syss_offs      = 0x0014,
1141         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1142                            SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
1143                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1144                            SYSS_HAS_RESET_STATUS),
1145         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1146         .sysc_fields    = &omap_hwmod_sysc_type1,
1147 };
1148
1149 static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = {
1150         .name   = "timer",
1151         .sysc   = &omap44xx_timer_1ms_sysc,
1152 };
1153
1154 /* timer1 */
1155 static struct omap_hwmod omap44xx_timer1_hwmod = {
1156         .name           = "timer1",
1157         .class          = &omap44xx_timer_1ms_hwmod_class,
1158         .clkdm_name     = "l4_wkup_clkdm",
1159         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
1160         .main_clk       = "dmt1_clk_mux",
1161         .prcm = {
1162                 .omap4 = {
1163                         .clkctrl_offs = OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
1164                         .context_offs = OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET,
1165                         .modulemode   = MODULEMODE_SWCTRL,
1166                 },
1167         },
1168 };
1169
1170 /*
1171  * 'usb_host_fs' class
1172  * full-speed usb host controller
1173  */
1174
1175 /* The IP is not compliant to type1 / type2 scheme */
1176 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_fs_sysc = {
1177         .rev_offs       = 0x0000,
1178         .sysc_offs      = 0x0210,
1179         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
1180                            SYSC_HAS_SOFTRESET),
1181         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1182                            SIDLE_SMART_WKUP),
1183         .sysc_fields    = &omap_hwmod_sysc_type_usb_host_fs,
1184 };
1185
1186 static struct omap_hwmod_class omap44xx_usb_host_fs_hwmod_class = {
1187         .name   = "usb_host_fs",
1188         .sysc   = &omap44xx_usb_host_fs_sysc,
1189 };
1190
1191 /* usb_host_fs */
1192 static struct omap_hwmod omap44xx_usb_host_fs_hwmod = {
1193         .name           = "usb_host_fs",
1194         .class          = &omap44xx_usb_host_fs_hwmod_class,
1195         .clkdm_name     = "l3_init_clkdm",
1196         .main_clk       = "usb_host_fs_fck",
1197         .prcm = {
1198                 .omap4 = {
1199                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_FS_CLKCTRL_OFFSET,
1200                         .context_offs = OMAP4_RM_L3INIT_USB_HOST_FS_CONTEXT_OFFSET,
1201                         .modulemode   = MODULEMODE_SWCTRL,
1202                 },
1203         },
1204 };
1205
1206 /*
1207  * 'usb_host_hs' class
1208  * high-speed multi-port usb host controller
1209  */
1210
1211 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc = {
1212         .rev_offs       = 0x0000,
1213         .sysc_offs      = 0x0010,
1214         .syss_offs      = 0x0014,
1215         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
1216                            SYSC_HAS_SOFTRESET | SYSC_HAS_RESET_STATUS),
1217         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1218                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1219                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1220         .sysc_fields    = &omap_hwmod_sysc_type2,
1221 };
1222
1223 static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class = {
1224         .name   = "usb_host_hs",
1225         .sysc   = &omap44xx_usb_host_hs_sysc,
1226 };
1227
1228 /* usb_host_hs */
1229 static struct omap_hwmod omap44xx_usb_host_hs_hwmod = {
1230         .name           = "usb_host_hs",
1231         .class          = &omap44xx_usb_host_hs_hwmod_class,
1232         .clkdm_name     = "l3_init_clkdm",
1233         .main_clk       = "usb_host_hs_fck",
1234         .prcm = {
1235                 .omap4 = {
1236                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET,
1237                         .context_offs = OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET,
1238                         .modulemode   = MODULEMODE_SWCTRL,
1239                 },
1240         },
1241
1242         /*
1243          * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
1244          * id: i660
1245          *
1246          * Description:
1247          * In the following configuration :
1248          * - USBHOST module is set to smart-idle mode
1249          * - PRCM asserts idle_req to the USBHOST module ( This typically
1250          *   happens when the system is going to a low power mode : all ports
1251          *   have been suspended, the master part of the USBHOST module has
1252          *   entered the standby state, and SW has cut the functional clocks)
1253          * - an USBHOST interrupt occurs before the module is able to answer
1254          *   idle_ack, typically a remote wakeup IRQ.
1255          * Then the USB HOST module will enter a deadlock situation where it
1256          * is no more accessible nor functional.
1257          *
1258          * Workaround:
1259          * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
1260          */
1261
1262         /*
1263          * Errata: USB host EHCI may stall when entering smart-standby mode
1264          * Id: i571
1265          *
1266          * Description:
1267          * When the USBHOST module is set to smart-standby mode, and when it is
1268          * ready to enter the standby state (i.e. all ports are suspended and
1269          * all attached devices are in suspend mode), then it can wrongly assert
1270          * the Mstandby signal too early while there are still some residual OCP
1271          * transactions ongoing. If this condition occurs, the internal state
1272          * machine may go to an undefined state and the USB link may be stuck
1273          * upon the next resume.
1274          *
1275          * Workaround:
1276          * Don't use smart standby; use only force standby,
1277          * hence HWMOD_SWSUP_MSTANDBY
1278          */
1279
1280         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
1281 };
1282
1283 /*
1284  * 'usb_tll_hs' class
1285  * usb_tll_hs module is the adapter on the usb_host_hs ports
1286  */
1287
1288 static struct omap_hwmod_class_sysconfig omap44xx_usb_tll_hs_sysc = {
1289         .rev_offs       = 0x0000,
1290         .sysc_offs      = 0x0010,
1291         .syss_offs      = 0x0014,
1292         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1293                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1294                            SYSC_HAS_AUTOIDLE),
1295         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1296         .sysc_fields    = &omap_hwmod_sysc_type1,
1297 };
1298
1299 static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class = {
1300         .name   = "usb_tll_hs",
1301         .sysc   = &omap44xx_usb_tll_hs_sysc,
1302 };
1303
1304 static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = {
1305         .name           = "usb_tll_hs",
1306         .class          = &omap44xx_usb_tll_hs_hwmod_class,
1307         .clkdm_name     = "l3_init_clkdm",
1308         .main_clk       = "usb_tll_hs_ick",
1309         .prcm = {
1310                 .omap4 = {
1311                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET,
1312                         .context_offs = OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET,
1313                         .modulemode   = MODULEMODE_HWCTRL,
1314                 },
1315         },
1316 };
1317
1318 /*
1319  * interfaces
1320  */
1321
1322 /* l3_main_1 -> dmm */
1323 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
1324         .master         = &omap44xx_l3_main_1_hwmod,
1325         .slave          = &omap44xx_dmm_hwmod,
1326         .clk            = "l3_div_ck",
1327         .user           = OCP_USER_SDMA,
1328 };
1329
1330 /* mpu -> dmm */
1331 static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
1332         .master         = &omap44xx_mpu_hwmod,
1333         .slave          = &omap44xx_dmm_hwmod,
1334         .clk            = "l3_div_ck",
1335         .user           = OCP_USER_MPU,
1336 };
1337
1338 /* iva -> l3_instr */
1339 static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
1340         .master         = &omap44xx_iva_hwmod,
1341         .slave          = &omap44xx_l3_instr_hwmod,
1342         .clk            = "l3_div_ck",
1343         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1344 };
1345
1346 /* l3_main_3 -> l3_instr */
1347 static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
1348         .master         = &omap44xx_l3_main_3_hwmod,
1349         .slave          = &omap44xx_l3_instr_hwmod,
1350         .clk            = "l3_div_ck",
1351         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1352 };
1353
1354 /* ocp_wp_noc -> l3_instr */
1355 static struct omap_hwmod_ocp_if omap44xx_ocp_wp_noc__l3_instr = {
1356         .master         = &omap44xx_ocp_wp_noc_hwmod,
1357         .slave          = &omap44xx_l3_instr_hwmod,
1358         .clk            = "l3_div_ck",
1359         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1360 };
1361
1362 /* dsp -> l3_main_1 */
1363 static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
1364         .master         = &omap44xx_dsp_hwmod,
1365         .slave          = &omap44xx_l3_main_1_hwmod,
1366         .clk            = "l3_div_ck",
1367         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1368 };
1369
1370 /* dss -> l3_main_1 */
1371 static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = {
1372         .master         = &omap44xx_dss_hwmod,
1373         .slave          = &omap44xx_l3_main_1_hwmod,
1374         .clk            = "l3_div_ck",
1375         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1376 };
1377
1378 /* l3_main_2 -> l3_main_1 */
1379 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
1380         .master         = &omap44xx_l3_main_2_hwmod,
1381         .slave          = &omap44xx_l3_main_1_hwmod,
1382         .clk            = "l3_div_ck",
1383         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1384 };
1385
1386 /* l4_cfg -> l3_main_1 */
1387 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
1388         .master         = &omap44xx_l4_cfg_hwmod,
1389         .slave          = &omap44xx_l3_main_1_hwmod,
1390         .clk            = "l4_div_ck",
1391         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1392 };
1393
1394 /* mpu -> l3_main_1 */
1395 static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
1396         .master         = &omap44xx_mpu_hwmod,
1397         .slave          = &omap44xx_l3_main_1_hwmod,
1398         .clk            = "l3_div_ck",
1399         .user           = OCP_USER_MPU,
1400 };
1401
1402 /* debugss -> l3_main_2 */
1403 static struct omap_hwmod_ocp_if omap44xx_debugss__l3_main_2 = {
1404         .master         = &omap44xx_debugss_hwmod,
1405         .slave          = &omap44xx_l3_main_2_hwmod,
1406         .clk            = "dbgclk_mux_ck",
1407         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1408 };
1409
1410 /* ipu -> l3_main_2 */
1411 static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = {
1412         .master         = &omap44xx_ipu_hwmod,
1413         .slave          = &omap44xx_l3_main_2_hwmod,
1414         .clk            = "l3_div_ck",
1415         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1416 };
1417
1418 /* iss -> l3_main_2 */
1419 static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = {
1420         .master         = &omap44xx_iss_hwmod,
1421         .slave          = &omap44xx_l3_main_2_hwmod,
1422         .clk            = "l3_div_ck",
1423         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1424 };
1425
1426 /* iva -> l3_main_2 */
1427 static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
1428         .master         = &omap44xx_iva_hwmod,
1429         .slave          = &omap44xx_l3_main_2_hwmod,
1430         .clk            = "l3_div_ck",
1431         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1432 };
1433
1434 /* l3_main_1 -> l3_main_2 */
1435 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
1436         .master         = &omap44xx_l3_main_1_hwmod,
1437         .slave          = &omap44xx_l3_main_2_hwmod,
1438         .clk            = "l3_div_ck",
1439         .user           = OCP_USER_MPU,
1440 };
1441
1442 /* l4_cfg -> l3_main_2 */
1443 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
1444         .master         = &omap44xx_l4_cfg_hwmod,
1445         .slave          = &omap44xx_l3_main_2_hwmod,
1446         .clk            = "l4_div_ck",
1447         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1448 };
1449
1450 /* usb_host_fs -> l3_main_2 */
1451 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_usb_host_fs__l3_main_2 = {
1452         .master         = &omap44xx_usb_host_fs_hwmod,
1453         .slave          = &omap44xx_l3_main_2_hwmod,
1454         .clk            = "l3_div_ck",
1455         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1456 };
1457
1458 /* usb_host_hs -> l3_main_2 */
1459 static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2 = {
1460         .master         = &omap44xx_usb_host_hs_hwmod,
1461         .slave          = &omap44xx_l3_main_2_hwmod,
1462         .clk            = "l3_div_ck",
1463         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1464 };
1465
1466 /* l3_main_1 -> l3_main_3 */
1467 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
1468         .master         = &omap44xx_l3_main_1_hwmod,
1469         .slave          = &omap44xx_l3_main_3_hwmod,
1470         .clk            = "l3_div_ck",
1471         .user           = OCP_USER_MPU,
1472 };
1473
1474 /* l3_main_2 -> l3_main_3 */
1475 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
1476         .master         = &omap44xx_l3_main_2_hwmod,
1477         .slave          = &omap44xx_l3_main_3_hwmod,
1478         .clk            = "l3_div_ck",
1479         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1480 };
1481
1482 /* l4_cfg -> l3_main_3 */
1483 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
1484         .master         = &omap44xx_l4_cfg_hwmod,
1485         .slave          = &omap44xx_l3_main_3_hwmod,
1486         .clk            = "l4_div_ck",
1487         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1488 };
1489
1490 /* dsp -> l4_abe */
1491 static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
1492         .master         = &omap44xx_dsp_hwmod,
1493         .slave          = &omap44xx_l4_abe_hwmod,
1494         .clk            = "ocp_abe_iclk",
1495         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1496 };
1497
1498 /* l3_main_1 -> l4_abe */
1499 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
1500         .master         = &omap44xx_l3_main_1_hwmod,
1501         .slave          = &omap44xx_l4_abe_hwmod,
1502         .clk            = "l3_div_ck",
1503         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1504 };
1505
1506 /* mpu -> l4_abe */
1507 static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
1508         .master         = &omap44xx_mpu_hwmod,
1509         .slave          = &omap44xx_l4_abe_hwmod,
1510         .clk            = "ocp_abe_iclk",
1511         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1512 };
1513
1514 /* l3_main_1 -> l4_cfg */
1515 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
1516         .master         = &omap44xx_l3_main_1_hwmod,
1517         .slave          = &omap44xx_l4_cfg_hwmod,
1518         .clk            = "l3_div_ck",
1519         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1520 };
1521
1522 /* l3_main_2 -> l4_per */
1523 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
1524         .master         = &omap44xx_l3_main_2_hwmod,
1525         .slave          = &omap44xx_l4_per_hwmod,
1526         .clk            = "l3_div_ck",
1527         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1528 };
1529
1530 /* l4_cfg -> l4_wkup */
1531 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
1532         .master         = &omap44xx_l4_cfg_hwmod,
1533         .slave          = &omap44xx_l4_wkup_hwmod,
1534         .clk            = "l4_div_ck",
1535         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1536 };
1537
1538 /* mpu -> mpu_private */
1539 static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
1540         .master         = &omap44xx_mpu_hwmod,
1541         .slave          = &omap44xx_mpu_private_hwmod,
1542         .clk            = "l3_div_ck",
1543         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1544 };
1545
1546 /* l4_cfg -> ocp_wp_noc */
1547 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp_wp_noc = {
1548         .master         = &omap44xx_l4_cfg_hwmod,
1549         .slave          = &omap44xx_ocp_wp_noc_hwmod,
1550         .clk            = "l4_div_ck",
1551         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1552 };
1553
1554 /* l4_wkup -> counter_32k */
1555 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
1556         .master         = &omap44xx_l4_wkup_hwmod,
1557         .slave          = &omap44xx_counter_32k_hwmod,
1558         .clk            = "l4_wkup_clk_mux_ck",
1559         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1560 };
1561
1562 /* l4_cfg -> ctrl_module_core */
1563 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_core = {
1564         .master         = &omap44xx_l4_cfg_hwmod,
1565         .slave          = &omap44xx_ctrl_module_core_hwmod,
1566         .clk            = "l4_div_ck",
1567         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1568 };
1569
1570 /* l4_cfg -> ctrl_module_pad_core */
1571 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_pad_core = {
1572         .master         = &omap44xx_l4_cfg_hwmod,
1573         .slave          = &omap44xx_ctrl_module_pad_core_hwmod,
1574         .clk            = "l4_div_ck",
1575         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1576 };
1577
1578 /* l4_wkup -> ctrl_module_wkup */
1579 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_wkup = {
1580         .master         = &omap44xx_l4_wkup_hwmod,
1581         .slave          = &omap44xx_ctrl_module_wkup_hwmod,
1582         .clk            = "l4_wkup_clk_mux_ck",
1583         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1584 };
1585
1586 /* l4_wkup -> ctrl_module_pad_wkup */
1587 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_pad_wkup = {
1588         .master         = &omap44xx_l4_wkup_hwmod,
1589         .slave          = &omap44xx_ctrl_module_pad_wkup_hwmod,
1590         .clk            = "l4_wkup_clk_mux_ck",
1591         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1592 };
1593
1594 /* l3_instr -> debugss */
1595 static struct omap_hwmod_ocp_if omap44xx_l3_instr__debugss = {
1596         .master         = &omap44xx_l3_instr_hwmod,
1597         .slave          = &omap44xx_debugss_hwmod,
1598         .clk            = "l3_div_ck",
1599         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1600 };
1601
1602 /* dsp -> iva */
1603 static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
1604         .master         = &omap44xx_dsp_hwmod,
1605         .slave          = &omap44xx_iva_hwmod,
1606         .clk            = "dpll_iva_m5x2_ck",
1607         .user           = OCP_USER_DSP,
1608 };
1609
1610 /* dsp -> sl2if */
1611 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_dsp__sl2if = {
1612         .master         = &omap44xx_dsp_hwmod,
1613         .slave          = &omap44xx_sl2if_hwmod,
1614         .clk            = "dpll_iva_m5x2_ck",
1615         .user           = OCP_USER_DSP,
1616 };
1617
1618 /* l4_cfg -> dsp */
1619 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
1620         .master         = &omap44xx_l4_cfg_hwmod,
1621         .slave          = &omap44xx_dsp_hwmod,
1622         .clk            = "l4_div_ck",
1623         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1624 };
1625
1626 /* l3_main_2 -> dss */
1627 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
1628         .master         = &omap44xx_l3_main_2_hwmod,
1629         .slave          = &omap44xx_dss_hwmod,
1630         .clk            = "l3_div_ck",
1631         .user           = OCP_USER_SDMA,
1632 };
1633
1634 /* l4_per -> dss */
1635 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
1636         .master         = &omap44xx_l4_per_hwmod,
1637         .slave          = &omap44xx_dss_hwmod,
1638         .clk            = "l4_div_ck",
1639         .user           = OCP_USER_MPU,
1640 };
1641
1642 /* l3_main_2 -> dss_dispc */
1643 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
1644         .master         = &omap44xx_l3_main_2_hwmod,
1645         .slave          = &omap44xx_dss_dispc_hwmod,
1646         .clk            = "l3_div_ck",
1647         .user           = OCP_USER_SDMA,
1648 };
1649
1650 /* l4_per -> dss_dispc */
1651 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
1652         .master         = &omap44xx_l4_per_hwmod,
1653         .slave          = &omap44xx_dss_dispc_hwmod,
1654         .clk            = "l4_div_ck",
1655         .user           = OCP_USER_MPU,
1656 };
1657
1658 /* l3_main_2 -> dss_dsi1 */
1659 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
1660         .master         = &omap44xx_l3_main_2_hwmod,
1661         .slave          = &omap44xx_dss_dsi1_hwmod,
1662         .clk            = "l3_div_ck",
1663         .user           = OCP_USER_SDMA,
1664 };
1665
1666 /* l4_per -> dss_dsi1 */
1667 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
1668         .master         = &omap44xx_l4_per_hwmod,
1669         .slave          = &omap44xx_dss_dsi1_hwmod,
1670         .clk            = "l4_div_ck",
1671         .user           = OCP_USER_MPU,
1672 };
1673
1674 /* l3_main_2 -> dss_dsi2 */
1675 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
1676         .master         = &omap44xx_l3_main_2_hwmod,
1677         .slave          = &omap44xx_dss_dsi2_hwmod,
1678         .clk            = "l3_div_ck",
1679         .user           = OCP_USER_SDMA,
1680 };
1681
1682 /* l4_per -> dss_dsi2 */
1683 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
1684         .master         = &omap44xx_l4_per_hwmod,
1685         .slave          = &omap44xx_dss_dsi2_hwmod,
1686         .clk            = "l4_div_ck",
1687         .user           = OCP_USER_MPU,
1688 };
1689
1690 /* l3_main_2 -> dss_hdmi */
1691 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
1692         .master         = &omap44xx_l3_main_2_hwmod,
1693         .slave          = &omap44xx_dss_hdmi_hwmod,
1694         .clk            = "l3_div_ck",
1695         .user           = OCP_USER_SDMA,
1696 };
1697
1698 /* l4_per -> dss_hdmi */
1699 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
1700         .master         = &omap44xx_l4_per_hwmod,
1701         .slave          = &omap44xx_dss_hdmi_hwmod,
1702         .clk            = "l4_div_ck",
1703         .user           = OCP_USER_MPU,
1704 };
1705
1706 /* l3_main_2 -> dss_rfbi */
1707 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
1708         .master         = &omap44xx_l3_main_2_hwmod,
1709         .slave          = &omap44xx_dss_rfbi_hwmod,
1710         .clk            = "l3_div_ck",
1711         .user           = OCP_USER_SDMA,
1712 };
1713
1714 /* l4_per -> dss_rfbi */
1715 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
1716         .master         = &omap44xx_l4_per_hwmod,
1717         .slave          = &omap44xx_dss_rfbi_hwmod,
1718         .clk            = "l4_div_ck",
1719         .user           = OCP_USER_MPU,
1720 };
1721
1722 /* l3_main_2 -> dss_venc */
1723 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
1724         .master         = &omap44xx_l3_main_2_hwmod,
1725         .slave          = &omap44xx_dss_venc_hwmod,
1726         .clk            = "l3_div_ck",
1727         .user           = OCP_USER_SDMA,
1728 };
1729
1730 /* l4_per -> dss_venc */
1731 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
1732         .master         = &omap44xx_l4_per_hwmod,
1733         .slave          = &omap44xx_dss_venc_hwmod,
1734         .clk            = "l4_div_ck",
1735         .user           = OCP_USER_MPU,
1736 };
1737
1738 /* l3_main_2 -> sham */
1739 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__sha0 = {
1740         .master         = &omap44xx_l3_main_2_hwmod,
1741         .slave          = &omap44xx_sha0_hwmod,
1742         .clk            = "l3_div_ck",
1743         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1744 };
1745
1746 /* l3_main_2 -> gpmc */
1747 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = {
1748         .master         = &omap44xx_l3_main_2_hwmod,
1749         .slave          = &omap44xx_gpmc_hwmod,
1750         .clk            = "l3_div_ck",
1751         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1752 };
1753
1754 /* l3_main_2 -> ipu */
1755 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = {
1756         .master         = &omap44xx_l3_main_2_hwmod,
1757         .slave          = &omap44xx_ipu_hwmod,
1758         .clk            = "l3_div_ck",
1759         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1760 };
1761
1762 /* l3_main_2 -> iss */
1763 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
1764         .master         = &omap44xx_l3_main_2_hwmod,
1765         .slave          = &omap44xx_iss_hwmod,
1766         .clk            = "l3_div_ck",
1767         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1768 };
1769
1770 /* iva -> sl2if */
1771 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_iva__sl2if = {
1772         .master         = &omap44xx_iva_hwmod,
1773         .slave          = &omap44xx_sl2if_hwmod,
1774         .clk            = "dpll_iva_m5x2_ck",
1775         .user           = OCP_USER_IVA,
1776 };
1777
1778 /* l3_main_2 -> iva */
1779 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
1780         .master         = &omap44xx_l3_main_2_hwmod,
1781         .slave          = &omap44xx_iva_hwmod,
1782         .clk            = "l3_div_ck",
1783         .user           = OCP_USER_MPU,
1784 };
1785
1786 /* l3_main_2 -> ocmc_ram */
1787 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ocmc_ram = {
1788         .master         = &omap44xx_l3_main_2_hwmod,
1789         .slave          = &omap44xx_ocmc_ram_hwmod,
1790         .clk            = "l3_div_ck",
1791         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1792 };
1793
1794 /* mpu_private -> prcm_mpu */
1795 static struct omap_hwmod_ocp_if omap44xx_mpu_private__prcm_mpu = {
1796         .master         = &omap44xx_mpu_private_hwmod,
1797         .slave          = &omap44xx_prcm_mpu_hwmod,
1798         .clk            = "l3_div_ck",
1799         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1800 };
1801
1802 /* l4_wkup -> cm_core_aon */
1803 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__cm_core_aon = {
1804         .master         = &omap44xx_l4_wkup_hwmod,
1805         .slave          = &omap44xx_cm_core_aon_hwmod,
1806         .clk            = "l4_wkup_clk_mux_ck",
1807         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1808 };
1809
1810 /* l4_cfg -> cm_core */
1811 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__cm_core = {
1812         .master         = &omap44xx_l4_cfg_hwmod,
1813         .slave          = &omap44xx_cm_core_hwmod,
1814         .clk            = "l4_div_ck",
1815         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1816 };
1817
1818 /* l4_wkup -> prm */
1819 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__prm = {
1820         .master         = &omap44xx_l4_wkup_hwmod,
1821         .slave          = &omap44xx_prm_hwmod,
1822         .clk            = "l4_wkup_clk_mux_ck",
1823         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1824 };
1825
1826 /* l4_wkup -> scrm */
1827 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__scrm = {
1828         .master         = &omap44xx_l4_wkup_hwmod,
1829         .slave          = &omap44xx_scrm_hwmod,
1830         .clk            = "l4_wkup_clk_mux_ck",
1831         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1832 };
1833
1834 /* l3_main_2 -> sl2if */
1835 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l3_main_2__sl2if = {
1836         .master         = &omap44xx_l3_main_2_hwmod,
1837         .slave          = &omap44xx_sl2if_hwmod,
1838         .clk            = "l3_div_ck",
1839         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1840 };
1841
1842 /* l4_wkup -> timer1 */
1843 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
1844         .master         = &omap44xx_l4_wkup_hwmod,
1845         .slave          = &omap44xx_timer1_hwmod,
1846         .clk            = "l4_wkup_clk_mux_ck",
1847         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1848 };
1849
1850 /* l4_cfg -> usb_host_fs */
1851 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_cfg__usb_host_fs = {
1852         .master         = &omap44xx_l4_cfg_hwmod,
1853         .slave          = &omap44xx_usb_host_fs_hwmod,
1854         .clk            = "l4_div_ck",
1855         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1856 };
1857
1858 /* l4_cfg -> usb_host_hs */
1859 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = {
1860         .master         = &omap44xx_l4_cfg_hwmod,
1861         .slave          = &omap44xx_usb_host_hs_hwmod,
1862         .clk            = "l4_div_ck",
1863         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1864 };
1865
1866 /* l4_cfg -> usb_tll_hs */
1867 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = {
1868         .master         = &omap44xx_l4_cfg_hwmod,
1869         .slave          = &omap44xx_usb_tll_hs_hwmod,
1870         .clk            = "l4_div_ck",
1871         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1872 };
1873
1874 /* mpu -> emif1 */
1875 static struct omap_hwmod_ocp_if omap44xx_mpu__emif1 = {
1876         .master         = &omap44xx_mpu_hwmod,
1877         .slave          = &omap44xx_emif1_hwmod,
1878         .clk            = "l3_div_ck",
1879         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1880 };
1881
1882 /* mpu -> emif2 */
1883 static struct omap_hwmod_ocp_if omap44xx_mpu__emif2 = {
1884         .master         = &omap44xx_mpu_hwmod,
1885         .slave          = &omap44xx_emif2_hwmod,
1886         .clk            = "l3_div_ck",
1887         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1888 };
1889
1890 static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
1891         &omap44xx_l3_main_1__dmm,
1892         &omap44xx_mpu__dmm,
1893         &omap44xx_iva__l3_instr,
1894         &omap44xx_l3_main_3__l3_instr,
1895         &omap44xx_ocp_wp_noc__l3_instr,
1896         &omap44xx_dsp__l3_main_1,
1897         &omap44xx_dss__l3_main_1,
1898         &omap44xx_l3_main_2__l3_main_1,
1899         &omap44xx_l4_cfg__l3_main_1,
1900         &omap44xx_mpu__l3_main_1,
1901         &omap44xx_debugss__l3_main_2,
1902         &omap44xx_ipu__l3_main_2,
1903         &omap44xx_iss__l3_main_2,
1904         &omap44xx_iva__l3_main_2,
1905         &omap44xx_l3_main_1__l3_main_2,
1906         &omap44xx_l4_cfg__l3_main_2,
1907         /* &omap44xx_usb_host_fs__l3_main_2, */
1908         &omap44xx_usb_host_hs__l3_main_2,
1909         &omap44xx_l3_main_1__l3_main_3,
1910         &omap44xx_l3_main_2__l3_main_3,
1911         &omap44xx_l4_cfg__l3_main_3,
1912         &omap44xx_dsp__l4_abe,
1913         &omap44xx_l3_main_1__l4_abe,
1914         &omap44xx_mpu__l4_abe,
1915         &omap44xx_l3_main_1__l4_cfg,
1916         &omap44xx_l3_main_2__l4_per,
1917         &omap44xx_l4_cfg__l4_wkup,
1918         &omap44xx_mpu__mpu_private,
1919         &omap44xx_l4_cfg__ocp_wp_noc,
1920         &omap44xx_l4_wkup__counter_32k,
1921         &omap44xx_l4_cfg__ctrl_module_core,
1922         &omap44xx_l4_cfg__ctrl_module_pad_core,
1923         &omap44xx_l4_wkup__ctrl_module_wkup,
1924         &omap44xx_l4_wkup__ctrl_module_pad_wkup,
1925         &omap44xx_l3_instr__debugss,
1926         &omap44xx_dsp__iva,
1927         /* &omap44xx_dsp__sl2if, */
1928         &omap44xx_l4_cfg__dsp,
1929         &omap44xx_l3_main_2__dss,
1930         &omap44xx_l4_per__dss,
1931         &omap44xx_l3_main_2__dss_dispc,
1932         &omap44xx_l4_per__dss_dispc,
1933         &omap44xx_l3_main_2__dss_dsi1,
1934         &omap44xx_l4_per__dss_dsi1,
1935         &omap44xx_l3_main_2__dss_dsi2,
1936         &omap44xx_l4_per__dss_dsi2,
1937         &omap44xx_l3_main_2__dss_hdmi,
1938         &omap44xx_l4_per__dss_hdmi,
1939         &omap44xx_l3_main_2__dss_rfbi,
1940         &omap44xx_l4_per__dss_rfbi,
1941         &omap44xx_l3_main_2__dss_venc,
1942         &omap44xx_l4_per__dss_venc,
1943         &omap44xx_l3_main_2__gpmc,
1944         &omap44xx_l3_main_2__ipu,
1945         &omap44xx_l3_main_2__iss,
1946         /* &omap44xx_iva__sl2if, */
1947         &omap44xx_l3_main_2__iva,
1948         &omap44xx_l3_main_2__ocmc_ram,
1949         &omap44xx_mpu_private__prcm_mpu,
1950         &omap44xx_l4_wkup__cm_core_aon,
1951         &omap44xx_l4_cfg__cm_core,
1952         &omap44xx_l4_wkup__prm,
1953         &omap44xx_l4_wkup__scrm,
1954         /* &omap44xx_l3_main_2__sl2if, */
1955         &omap44xx_l4_wkup__timer1,
1956         /* &omap44xx_l4_cfg__usb_host_fs, */
1957         &omap44xx_l4_cfg__usb_host_hs,
1958         &omap44xx_l4_cfg__usb_tll_hs,
1959         &omap44xx_mpu__emif1,
1960         &omap44xx_mpu__emif2,
1961         &omap44xx_l3_main_2__aes1,
1962         &omap44xx_l3_main_2__aes2,
1963         &omap44xx_l3_main_2__des,
1964         &omap44xx_l3_main_2__sha0,
1965         NULL,
1966 };
1967
1968 int __init omap44xx_hwmod_init(void)
1969 {
1970         omap_hwmod_init();
1971         return omap_hwmod_register_links(omap44xx_hwmod_ocp_ifs);
1972 }
1973