1 // SPDX-License-Identifier: GPL-2.0-only
3 * Hardware modules present on the OMAP54xx chips
5 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
10 * This file is automatically generated from the OMAP hardware databases.
11 * We respectfully ask that any modifications to this file be coordinated
12 * with the public linux-omap@vger.kernel.org mailing list and the
13 * authors above to ensure that the autogeneration scripts are kept
14 * up-to-date with the file contents.
18 #include <linux/power/smartreflex.h>
20 #include "omap_hwmod.h"
21 #include "omap_hwmod_common_data.h"
26 /* Base offset for all OMAP5 interrupts external to MPUSS */
27 #define OMAP54XX_IRQ_GIC_START 32
37 static struct omap_hwmod_class omap54xx_dmm_hwmod_class = {
42 static struct omap_hwmod omap54xx_dmm_hwmod = {
44 .class = &omap54xx_dmm_hwmod_class,
45 .clkdm_name = "emif_clkdm",
48 .clkctrl_offs = OMAP54XX_CM_EMIF_DMM_CLKCTRL_OFFSET,
49 .context_offs = OMAP54XX_RM_EMIF_DMM_CONTEXT_OFFSET,
56 * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
58 static struct omap_hwmod_class omap54xx_l3_hwmod_class = {
63 static struct omap_hwmod omap54xx_l3_instr_hwmod = {
65 .class = &omap54xx_l3_hwmod_class,
66 .clkdm_name = "l3instr_clkdm",
69 .clkctrl_offs = OMAP54XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
70 .context_offs = OMAP54XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
71 .modulemode = MODULEMODE_HWCTRL,
77 static struct omap_hwmod omap54xx_l3_main_1_hwmod = {
79 .class = &omap54xx_l3_hwmod_class,
80 .clkdm_name = "l3main1_clkdm",
83 .clkctrl_offs = OMAP54XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET,
84 .context_offs = OMAP54XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET,
90 static struct omap_hwmod omap54xx_l3_main_2_hwmod = {
92 .class = &omap54xx_l3_hwmod_class,
93 .clkdm_name = "l3main2_clkdm",
96 .clkctrl_offs = OMAP54XX_CM_L3MAIN2_L3_MAIN_2_CLKCTRL_OFFSET,
97 .context_offs = OMAP54XX_RM_L3MAIN2_L3_MAIN_2_CONTEXT_OFFSET,
103 static struct omap_hwmod omap54xx_l3_main_3_hwmod = {
105 .class = &omap54xx_l3_hwmod_class,
106 .clkdm_name = "l3instr_clkdm",
109 .clkctrl_offs = OMAP54XX_CM_L3INSTR_L3_MAIN_3_CLKCTRL_OFFSET,
110 .context_offs = OMAP54XX_RM_L3INSTR_L3_MAIN_3_CONTEXT_OFFSET,
111 .modulemode = MODULEMODE_HWCTRL,
118 * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
120 static struct omap_hwmod_class omap54xx_l4_hwmod_class = {
125 static struct omap_hwmod omap54xx_l4_abe_hwmod = {
127 .class = &omap54xx_l4_hwmod_class,
128 .clkdm_name = "abe_clkdm",
131 .clkctrl_offs = OMAP54XX_CM_ABE_L4_ABE_CLKCTRL_OFFSET,
132 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
138 static struct omap_hwmod omap54xx_l4_cfg_hwmod = {
140 .class = &omap54xx_l4_hwmod_class,
141 .clkdm_name = "l4cfg_clkdm",
144 .clkctrl_offs = OMAP54XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
145 .context_offs = OMAP54XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
151 static struct omap_hwmod omap54xx_l4_per_hwmod = {
153 .class = &omap54xx_l4_hwmod_class,
154 .clkdm_name = "l4per_clkdm",
157 .clkctrl_offs = OMAP54XX_CM_L4PER_L4_PER_CLKCTRL_OFFSET,
158 .context_offs = OMAP54XX_RM_L4PER_L4_PER_CONTEXT_OFFSET,
164 static struct omap_hwmod omap54xx_l4_wkup_hwmod = {
166 .class = &omap54xx_l4_hwmod_class,
167 .clkdm_name = "wkupaon_clkdm",
170 .clkctrl_offs = OMAP54XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET,
171 .context_offs = OMAP54XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET,
178 * instance(s): mpu_private
180 static struct omap_hwmod_class omap54xx_mpu_bus_hwmod_class = {
185 static struct omap_hwmod omap54xx_mpu_private_hwmod = {
186 .name = "mpu_private",
187 .class = &omap54xx_mpu_bus_hwmod_class,
188 .clkdm_name = "mpu_clkdm",
191 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
198 * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
201 static struct omap_hwmod_class_sysconfig omap54xx_counter_sysc = {
204 .sysc_flags = SYSC_HAS_SIDLEMODE,
205 .idlemodes = (SIDLE_FORCE | SIDLE_NO),
206 .sysc_fields = &omap_hwmod_sysc_type1,
209 static struct omap_hwmod_class omap54xx_counter_hwmod_class = {
211 .sysc = &omap54xx_counter_sysc,
215 static struct omap_hwmod omap54xx_counter_32k_hwmod = {
216 .name = "counter_32k",
217 .class = &omap54xx_counter_hwmod_class,
218 .clkdm_name = "wkupaon_clkdm",
219 .flags = HWMOD_SWSUP_SIDLE,
220 .main_clk = "wkupaon_iclk_mux",
223 .clkctrl_offs = OMAP54XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET,
224 .context_offs = OMAP54XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET,
233 static struct omap_hwmod_class_sysconfig omap54xx_dss_sysc = {
236 .sysc_flags = SYSS_HAS_RESET_STATUS,
239 static struct omap_hwmod_class omap54xx_dss_hwmod_class = {
241 .sysc = &omap54xx_dss_sysc,
242 .reset = omap_dss_reset,
246 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
247 { .role = "32khz_clk", .clk = "dss_32khz_clk" },
248 { .role = "sys_clk", .clk = "dss_sys_clk" },
249 { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
252 static struct omap_hwmod omap54xx_dss_hwmod = {
254 .class = &omap54xx_dss_hwmod_class,
255 .clkdm_name = "dss_clkdm",
256 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
257 .main_clk = "dss_dss_clk",
260 .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
261 .context_offs = OMAP54XX_RM_DSS_DSS_CONTEXT_OFFSET,
262 .modulemode = MODULEMODE_SWCTRL,
265 .opt_clks = dss_opt_clks,
266 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
274 static struct omap_hwmod_class_sysconfig omap54xx_dispc_sysc = {
278 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
279 SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
280 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
281 SYSS_HAS_RESET_STATUS),
282 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
283 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
284 .sysc_fields = &omap_hwmod_sysc_type1,
287 static struct omap_hwmod_class omap54xx_dispc_hwmod_class = {
289 .sysc = &omap54xx_dispc_sysc,
293 static struct omap_hwmod_opt_clk dss_dispc_opt_clks[] = {
294 { .role = "sys_clk", .clk = "dss_sys_clk" },
297 /* dss_dispc dev_attr */
298 static struct omap_dss_dispc_dev_attr dss_dispc_dev_attr = {
299 .has_framedonetv_irq = 1,
303 static struct omap_hwmod omap54xx_dss_dispc_hwmod = {
305 .class = &omap54xx_dispc_hwmod_class,
306 .clkdm_name = "dss_clkdm",
307 .main_clk = "dss_dss_clk",
310 .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
311 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
314 .opt_clks = dss_dispc_opt_clks,
315 .opt_clks_cnt = ARRAY_SIZE(dss_dispc_opt_clks),
316 .dev_attr = &dss_dispc_dev_attr,
317 .parent_hwmod = &omap54xx_dss_hwmod,
322 * display serial interface controller
325 static struct omap_hwmod_class_sysconfig omap54xx_dsi1_sysc = {
329 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
330 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
331 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
332 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
333 .sysc_fields = &omap_hwmod_sysc_type1,
336 static struct omap_hwmod_class omap54xx_dsi1_hwmod_class = {
338 .sysc = &omap54xx_dsi1_sysc,
342 static struct omap_hwmod_opt_clk dss_dsi1_a_opt_clks[] = {
343 { .role = "sys_clk", .clk = "dss_sys_clk" },
346 static struct omap_hwmod omap54xx_dss_dsi1_a_hwmod = {
348 .class = &omap54xx_dsi1_hwmod_class,
349 .clkdm_name = "dss_clkdm",
350 .main_clk = "dss_dss_clk",
353 .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
354 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
357 .opt_clks = dss_dsi1_a_opt_clks,
358 .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_a_opt_clks),
359 .parent_hwmod = &omap54xx_dss_hwmod,
363 static struct omap_hwmod_opt_clk dss_dsi1_c_opt_clks[] = {
364 { .role = "sys_clk", .clk = "dss_sys_clk" },
367 static struct omap_hwmod omap54xx_dss_dsi1_c_hwmod = {
369 .class = &omap54xx_dsi1_hwmod_class,
370 .clkdm_name = "dss_clkdm",
371 .main_clk = "dss_dss_clk",
374 .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
375 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
378 .opt_clks = dss_dsi1_c_opt_clks,
379 .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_c_opt_clks),
380 .parent_hwmod = &omap54xx_dss_hwmod,
388 static struct omap_hwmod_class_sysconfig omap54xx_hdmi_sysc = {
391 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
393 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
395 .sysc_fields = &omap_hwmod_sysc_type2,
398 static struct omap_hwmod_class omap54xx_hdmi_hwmod_class = {
400 .sysc = &omap54xx_hdmi_sysc,
403 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
404 { .role = "sys_clk", .clk = "dss_sys_clk" },
407 static struct omap_hwmod omap54xx_dss_hdmi_hwmod = {
409 .class = &omap54xx_hdmi_hwmod_class,
410 .clkdm_name = "dss_clkdm",
411 .main_clk = "dss_48mhz_clk",
414 .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
415 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
418 .opt_clks = dss_hdmi_opt_clks,
419 .opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks),
420 .parent_hwmod = &omap54xx_dss_hwmod,
425 * remote frame buffer interface
428 static struct omap_hwmod_class_sysconfig omap54xx_rfbi_sysc = {
432 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
433 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
434 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
435 .sysc_fields = &omap_hwmod_sysc_type1,
438 static struct omap_hwmod_class omap54xx_rfbi_hwmod_class = {
440 .sysc = &omap54xx_rfbi_sysc,
444 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
445 { .role = "ick", .clk = "l3_iclk_div" },
448 static struct omap_hwmod omap54xx_dss_rfbi_hwmod = {
450 .class = &omap54xx_rfbi_hwmod_class,
451 .clkdm_name = "dss_clkdm",
454 .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
455 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
458 .opt_clks = dss_rfbi_opt_clks,
459 .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
460 .parent_hwmod = &omap54xx_dss_hwmod,
465 * external memory interface no1 (wrapper)
468 static struct omap_hwmod_class_sysconfig omap54xx_emif_sysc = {
472 static struct omap_hwmod_class omap54xx_emif_hwmod_class = {
474 .sysc = &omap54xx_emif_sysc,
478 static struct omap_hwmod omap54xx_emif1_hwmod = {
480 .class = &omap54xx_emif_hwmod_class,
481 .clkdm_name = "emif_clkdm",
482 .flags = HWMOD_INIT_NO_IDLE,
483 .main_clk = "dpll_core_h11x2_ck",
486 .clkctrl_offs = OMAP54XX_CM_EMIF_EMIF1_CLKCTRL_OFFSET,
487 .context_offs = OMAP54XX_RM_EMIF_EMIF1_CONTEXT_OFFSET,
488 .modulemode = MODULEMODE_HWCTRL,
494 static struct omap_hwmod omap54xx_emif2_hwmod = {
496 .class = &omap54xx_emif_hwmod_class,
497 .clkdm_name = "emif_clkdm",
498 .flags = HWMOD_INIT_NO_IDLE,
499 .main_clk = "dpll_core_h11x2_ck",
502 .clkctrl_offs = OMAP54XX_CM_EMIF_EMIF2_CLKCTRL_OFFSET,
503 .context_offs = OMAP54XX_RM_EMIF_EMIF2_CONTEXT_OFFSET,
504 .modulemode = MODULEMODE_HWCTRL,
517 static struct omap_hwmod_class omap54xx_mpu_hwmod_class = {
522 static struct omap_hwmod omap54xx_mpu_hwmod = {
524 .class = &omap54xx_mpu_hwmod_class,
525 .clkdm_name = "mpu_clkdm",
526 .flags = HWMOD_INIT_NO_IDLE,
527 .main_clk = "dpll_mpu_m2_ck",
530 .clkctrl_offs = OMAP54XX_CM_MPU_MPU_CLKCTRL_OFFSET,
531 .context_offs = OMAP54XX_RM_MPU_MPU_CONTEXT_OFFSET,
539 * general purpose timer module with accurate 1ms tick
540 * This class contains several variants: ['timer_1ms', 'timer']
543 static struct omap_hwmod_class_sysconfig omap54xx_timer_1ms_sysc = {
546 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
547 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
548 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
550 .sysc_fields = &omap_hwmod_sysc_type2,
553 static struct omap_hwmod_class omap54xx_timer_1ms_hwmod_class = {
555 .sysc = &omap54xx_timer_1ms_sysc,
559 static struct omap_hwmod omap54xx_timer1_hwmod = {
561 .class = &omap54xx_timer_1ms_hwmod_class,
562 .clkdm_name = "wkupaon_clkdm",
563 .main_clk = "timer1_gfclk_mux",
564 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
567 .clkctrl_offs = OMAP54XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET,
568 .context_offs = OMAP54XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET,
569 .modulemode = MODULEMODE_SWCTRL,
575 * 'usb_host_hs' class
576 * high-speed multi-port usb host controller
579 static struct omap_hwmod_class_sysconfig omap54xx_usb_host_hs_sysc = {
582 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
583 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
584 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
585 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
586 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
587 .sysc_fields = &omap_hwmod_sysc_type2,
590 static struct omap_hwmod_class omap54xx_usb_host_hs_hwmod_class = {
591 .name = "usb_host_hs",
592 .sysc = &omap54xx_usb_host_hs_sysc,
595 static struct omap_hwmod omap54xx_usb_host_hs_hwmod = {
596 .name = "usb_host_hs",
597 .class = &omap54xx_usb_host_hs_hwmod_class,
598 .clkdm_name = "l3init_clkdm",
600 * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
604 * In the following configuration :
605 * - USBHOST module is set to smart-idle mode
606 * - PRCM asserts idle_req to the USBHOST module ( This typically
607 * happens when the system is going to a low power mode : all ports
608 * have been suspended, the master part of the USBHOST module has
609 * entered the standby state, and SW has cut the functional clocks)
610 * - an USBHOST interrupt occurs before the module is able to answer
611 * idle_ack, typically a remote wakeup IRQ.
612 * Then the USB HOST module will enter a deadlock situation where it
613 * is no more accessible nor functional.
616 * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
620 * Errata: USB host EHCI may stall when entering smart-standby mode
624 * When the USBHOST module is set to smart-standby mode, and when it is
625 * ready to enter the standby state (i.e. all ports are suspended and
626 * all attached devices are in suspend mode), then it can wrongly assert
627 * the Mstandby signal too early while there are still some residual OCP
628 * transactions ongoing. If this condition occurs, the internal state
629 * machine may go to an undefined state and the USB link may be stuck
630 * upon the next resume.
633 * Don't use smart standby; use only force standby,
634 * hence HWMOD_SWSUP_MSTANDBY
637 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
638 .main_clk = "l3init_60m_fclk",
641 .clkctrl_offs = OMAP54XX_CM_L3INIT_USB_HOST_HS_CLKCTRL_OFFSET,
642 .context_offs = OMAP54XX_RM_L3INIT_USB_HOST_HS_CONTEXT_OFFSET,
643 .modulemode = MODULEMODE_SWCTRL,
650 * usb_tll_hs module is the adapter on the usb_host_hs ports
653 static struct omap_hwmod_class_sysconfig omap54xx_usb_tll_hs_sysc = {
657 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
658 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
659 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
660 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
661 .sysc_fields = &omap_hwmod_sysc_type1,
664 static struct omap_hwmod_class omap54xx_usb_tll_hs_hwmod_class = {
665 .name = "usb_tll_hs",
666 .sysc = &omap54xx_usb_tll_hs_sysc,
669 static struct omap_hwmod omap54xx_usb_tll_hs_hwmod = {
670 .name = "usb_tll_hs",
671 .class = &omap54xx_usb_tll_hs_hwmod_class,
672 .clkdm_name = "l3init_clkdm",
673 .main_clk = "l4_root_clk_div",
676 .clkctrl_offs = OMAP54XX_CM_L3INIT_USB_TLL_HS_CLKCTRL_OFFSET,
677 .context_offs = OMAP54XX_RM_L3INIT_USB_TLL_HS_CONTEXT_OFFSET,
678 .modulemode = MODULEMODE_HWCTRL,
685 * 2.0 super speed (usb_otg_ss) controller
688 static struct omap_hwmod_class_sysconfig omap54xx_usb_otg_ss_sysc = {
691 .sysc_flags = (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE |
693 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
694 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
695 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
696 .sysc_fields = &omap_hwmod_sysc_type2,
699 static struct omap_hwmod_class omap54xx_usb_otg_ss_hwmod_class = {
700 .name = "usb_otg_ss",
701 .sysc = &omap54xx_usb_otg_ss_sysc,
705 static struct omap_hwmod_opt_clk usb_otg_ss_opt_clks[] = {
706 { .role = "refclk960m", .clk = "usb_otg_ss_refclk960m" },
709 static struct omap_hwmod omap54xx_usb_otg_ss_hwmod = {
710 .name = "usb_otg_ss",
711 .class = &omap54xx_usb_otg_ss_hwmod_class,
712 .clkdm_name = "l3init_clkdm",
713 .flags = HWMOD_SWSUP_SIDLE,
714 .main_clk = "dpll_core_h13x2_ck",
717 .clkctrl_offs = OMAP54XX_CM_L3INIT_USB_OTG_SS_CLKCTRL_OFFSET,
718 .context_offs = OMAP54XX_RM_L3INIT_USB_OTG_SS_CONTEXT_OFFSET,
719 .modulemode = MODULEMODE_HWCTRL,
722 .opt_clks = usb_otg_ss_opt_clks,
723 .opt_clks_cnt = ARRAY_SIZE(usb_otg_ss_opt_clks),
728 * sata: serial ata interface gen2 compliant ( 1 rx/ 1 tx)
731 static struct omap_hwmod_class_sysconfig omap54xx_sata_sysc = {
734 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
735 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
736 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
737 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
738 .sysc_fields = &omap_hwmod_sysc_type2,
741 static struct omap_hwmod_class omap54xx_sata_hwmod_class = {
743 .sysc = &omap54xx_sata_sysc,
747 static struct omap_hwmod omap54xx_sata_hwmod = {
749 .class = &omap54xx_sata_hwmod_class,
750 .clkdm_name = "l3init_clkdm",
751 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
752 .main_clk = "func_48m_fclk",
756 .clkctrl_offs = OMAP54XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
757 .context_offs = OMAP54XX_RM_L3INIT_SATA_CONTEXT_OFFSET,
758 .modulemode = MODULEMODE_SWCTRL,
764 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__sata = {
765 .master = &omap54xx_l4_cfg_hwmod,
766 .slave = &omap54xx_sata_hwmod,
767 .clk = "l3_iclk_div",
768 .user = OCP_USER_MPU | OCP_USER_SDMA,
775 /* l3_main_1 -> dmm */
776 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__dmm = {
777 .master = &omap54xx_l3_main_1_hwmod,
778 .slave = &omap54xx_dmm_hwmod,
779 .clk = "l3_iclk_div",
780 .user = OCP_USER_SDMA,
783 /* l3_main_3 -> l3_instr */
784 static struct omap_hwmod_ocp_if omap54xx_l3_main_3__l3_instr = {
785 .master = &omap54xx_l3_main_3_hwmod,
786 .slave = &omap54xx_l3_instr_hwmod,
787 .clk = "l3_iclk_div",
788 .user = OCP_USER_MPU | OCP_USER_SDMA,
791 /* l3_main_2 -> l3_main_1 */
792 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l3_main_1 = {
793 .master = &omap54xx_l3_main_2_hwmod,
794 .slave = &omap54xx_l3_main_1_hwmod,
795 .clk = "l3_iclk_div",
796 .user = OCP_USER_MPU | OCP_USER_SDMA,
799 /* l4_cfg -> l3_main_1 */
800 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_1 = {
801 .master = &omap54xx_l4_cfg_hwmod,
802 .slave = &omap54xx_l3_main_1_hwmod,
803 .clk = "l3_iclk_div",
804 .user = OCP_USER_MPU | OCP_USER_SDMA,
807 /* mpu -> l3_main_1 */
808 static struct omap_hwmod_ocp_if omap54xx_mpu__l3_main_1 = {
809 .master = &omap54xx_mpu_hwmod,
810 .slave = &omap54xx_l3_main_1_hwmod,
811 .clk = "l3_iclk_div",
812 .user = OCP_USER_MPU,
815 /* l3_main_1 -> l3_main_2 */
816 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l3_main_2 = {
817 .master = &omap54xx_l3_main_1_hwmod,
818 .slave = &omap54xx_l3_main_2_hwmod,
819 .clk = "l3_iclk_div",
820 .user = OCP_USER_MPU,
823 /* l4_cfg -> l3_main_2 */
824 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_2 = {
825 .master = &omap54xx_l4_cfg_hwmod,
826 .slave = &omap54xx_l3_main_2_hwmod,
827 .clk = "l3_iclk_div",
828 .user = OCP_USER_MPU | OCP_USER_SDMA,
831 /* l3_main_1 -> l3_main_3 */
832 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l3_main_3 = {
833 .master = &omap54xx_l3_main_1_hwmod,
834 .slave = &omap54xx_l3_main_3_hwmod,
835 .clk = "l3_iclk_div",
836 .user = OCP_USER_MPU,
839 /* l3_main_2 -> l3_main_3 */
840 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l3_main_3 = {
841 .master = &omap54xx_l3_main_2_hwmod,
842 .slave = &omap54xx_l3_main_3_hwmod,
843 .clk = "l3_iclk_div",
844 .user = OCP_USER_MPU | OCP_USER_SDMA,
847 /* l4_cfg -> l3_main_3 */
848 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_3 = {
849 .master = &omap54xx_l4_cfg_hwmod,
850 .slave = &omap54xx_l3_main_3_hwmod,
851 .clk = "l3_iclk_div",
852 .user = OCP_USER_MPU | OCP_USER_SDMA,
855 /* l3_main_1 -> l4_abe */
856 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_abe = {
857 .master = &omap54xx_l3_main_1_hwmod,
858 .slave = &omap54xx_l4_abe_hwmod,
860 .user = OCP_USER_MPU | OCP_USER_SDMA,
864 static struct omap_hwmod_ocp_if omap54xx_mpu__l4_abe = {
865 .master = &omap54xx_mpu_hwmod,
866 .slave = &omap54xx_l4_abe_hwmod,
868 .user = OCP_USER_MPU | OCP_USER_SDMA,
871 /* l3_main_1 -> l4_cfg */
872 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_cfg = {
873 .master = &omap54xx_l3_main_1_hwmod,
874 .slave = &omap54xx_l4_cfg_hwmod,
875 .clk = "l4_root_clk_div",
876 .user = OCP_USER_MPU | OCP_USER_SDMA,
879 /* l3_main_2 -> l4_per */
880 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l4_per = {
881 .master = &omap54xx_l3_main_2_hwmod,
882 .slave = &omap54xx_l4_per_hwmod,
883 .clk = "l4_root_clk_div",
884 .user = OCP_USER_MPU | OCP_USER_SDMA,
887 /* l3_main_1 -> l4_wkup */
888 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_wkup = {
889 .master = &omap54xx_l3_main_1_hwmod,
890 .slave = &omap54xx_l4_wkup_hwmod,
891 .clk = "wkupaon_iclk_mux",
892 .user = OCP_USER_MPU | OCP_USER_SDMA,
895 /* mpu -> mpu_private */
896 static struct omap_hwmod_ocp_if omap54xx_mpu__mpu_private = {
897 .master = &omap54xx_mpu_hwmod,
898 .slave = &omap54xx_mpu_private_hwmod,
899 .clk = "l3_iclk_div",
900 .user = OCP_USER_MPU | OCP_USER_SDMA,
903 /* l4_wkup -> counter_32k */
904 static struct omap_hwmod_ocp_if omap54xx_l4_wkup__counter_32k = {
905 .master = &omap54xx_l4_wkup_hwmod,
906 .slave = &omap54xx_counter_32k_hwmod,
907 .clk = "wkupaon_iclk_mux",
908 .user = OCP_USER_MPU | OCP_USER_SDMA,
911 /* l3_main_2 -> dss */
912 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss = {
913 .master = &omap54xx_l3_main_2_hwmod,
914 .slave = &omap54xx_dss_hwmod,
915 .clk = "l3_iclk_div",
916 .user = OCP_USER_MPU | OCP_USER_SDMA,
919 /* l3_main_2 -> dss_dispc */
920 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss_dispc = {
921 .master = &omap54xx_l3_main_2_hwmod,
922 .slave = &omap54xx_dss_dispc_hwmod,
923 .clk = "l3_iclk_div",
924 .user = OCP_USER_MPU | OCP_USER_SDMA,
927 /* l3_main_2 -> dss_dsi1_a */
928 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss_dsi1_a = {
929 .master = &omap54xx_l3_main_2_hwmod,
930 .slave = &omap54xx_dss_dsi1_a_hwmod,
931 .clk = "l3_iclk_div",
932 .user = OCP_USER_MPU | OCP_USER_SDMA,
935 /* l3_main_2 -> dss_dsi1_c */
936 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss_dsi1_c = {
937 .master = &omap54xx_l3_main_2_hwmod,
938 .slave = &omap54xx_dss_dsi1_c_hwmod,
939 .clk = "l3_iclk_div",
940 .user = OCP_USER_MPU | OCP_USER_SDMA,
943 /* l3_main_2 -> dss_hdmi */
944 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss_hdmi = {
945 .master = &omap54xx_l3_main_2_hwmod,
946 .slave = &omap54xx_dss_hdmi_hwmod,
947 .clk = "l3_iclk_div",
948 .user = OCP_USER_MPU | OCP_USER_SDMA,
951 /* l3_main_2 -> dss_rfbi */
952 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss_rfbi = {
953 .master = &omap54xx_l3_main_2_hwmod,
954 .slave = &omap54xx_dss_rfbi_hwmod,
955 .clk = "l3_iclk_div",
956 .user = OCP_USER_MPU | OCP_USER_SDMA,
960 static struct omap_hwmod_ocp_if omap54xx_mpu__emif1 = {
961 .master = &omap54xx_mpu_hwmod,
962 .slave = &omap54xx_emif1_hwmod,
963 .clk = "dpll_core_h11x2_ck",
964 .user = OCP_USER_MPU | OCP_USER_SDMA,
968 static struct omap_hwmod_ocp_if omap54xx_mpu__emif2 = {
969 .master = &omap54xx_mpu_hwmod,
970 .slave = &omap54xx_emif2_hwmod,
971 .clk = "dpll_core_h11x2_ck",
972 .user = OCP_USER_MPU | OCP_USER_SDMA,
976 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__mpu = {
977 .master = &omap54xx_l4_cfg_hwmod,
978 .slave = &omap54xx_mpu_hwmod,
979 .clk = "l4_root_clk_div",
980 .user = OCP_USER_MPU | OCP_USER_SDMA,
983 /* l4_wkup -> timer1 */
984 static struct omap_hwmod_ocp_if omap54xx_l4_wkup__timer1 = {
985 .master = &omap54xx_l4_wkup_hwmod,
986 .slave = &omap54xx_timer1_hwmod,
987 .clk = "wkupaon_iclk_mux",
988 .user = OCP_USER_MPU | OCP_USER_SDMA,
991 /* l4_cfg -> usb_host_hs */
992 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__usb_host_hs = {
993 .master = &omap54xx_l4_cfg_hwmod,
994 .slave = &omap54xx_usb_host_hs_hwmod,
995 .clk = "l3_iclk_div",
996 .user = OCP_USER_MPU | OCP_USER_SDMA,
999 /* l4_cfg -> usb_tll_hs */
1000 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__usb_tll_hs = {
1001 .master = &omap54xx_l4_cfg_hwmod,
1002 .slave = &omap54xx_usb_tll_hs_hwmod,
1003 .clk = "l4_root_clk_div",
1004 .user = OCP_USER_MPU | OCP_USER_SDMA,
1007 /* l4_cfg -> usb_otg_ss */
1008 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__usb_otg_ss = {
1009 .master = &omap54xx_l4_cfg_hwmod,
1010 .slave = &omap54xx_usb_otg_ss_hwmod,
1011 .clk = "dpll_core_h13x2_ck",
1012 .user = OCP_USER_MPU | OCP_USER_SDMA,
1015 static struct omap_hwmod_ocp_if *omap54xx_hwmod_ocp_ifs[] __initdata = {
1016 &omap54xx_l3_main_1__dmm,
1017 &omap54xx_l3_main_3__l3_instr,
1018 &omap54xx_l3_main_2__l3_main_1,
1019 &omap54xx_l4_cfg__l3_main_1,
1020 &omap54xx_mpu__l3_main_1,
1021 &omap54xx_l3_main_1__l3_main_2,
1022 &omap54xx_l4_cfg__l3_main_2,
1023 &omap54xx_l3_main_1__l3_main_3,
1024 &omap54xx_l3_main_2__l3_main_3,
1025 &omap54xx_l4_cfg__l3_main_3,
1026 &omap54xx_l3_main_1__l4_abe,
1027 &omap54xx_mpu__l4_abe,
1028 &omap54xx_l3_main_1__l4_cfg,
1029 &omap54xx_l3_main_2__l4_per,
1030 &omap54xx_l3_main_1__l4_wkup,
1031 &omap54xx_mpu__mpu_private,
1032 &omap54xx_l4_wkup__counter_32k,
1033 &omap54xx_l3_main_2__dss,
1034 &omap54xx_l3_main_2__dss_dispc,
1035 &omap54xx_l3_main_2__dss_dsi1_a,
1036 &omap54xx_l3_main_2__dss_dsi1_c,
1037 &omap54xx_l3_main_2__dss_hdmi,
1038 &omap54xx_l3_main_2__dss_rfbi,
1039 &omap54xx_mpu__emif1,
1040 &omap54xx_mpu__emif2,
1041 &omap54xx_l4_cfg__mpu,
1042 &omap54xx_l4_wkup__timer1,
1043 &omap54xx_l4_cfg__usb_host_hs,
1044 &omap54xx_l4_cfg__usb_tll_hs,
1045 &omap54xx_l4_cfg__usb_otg_ss,
1046 &omap54xx_l4_cfg__sata,
1050 int __init omap54xx_hwmod_init(void)
1053 return omap_hwmod_register_links(omap54xx_hwmod_ocp_ifs);