arch/arm/mach-omap2/omap_hwmod_7xx_data.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Hardware modules present on the DRA7xx chips
   4  *
   5  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
   6  *
   7  * Paul Walmsley
   8  * Benoit Cousson
   9  *
  10  * This file is automatically generated from the OMAP hardware databases.
  11  * We respectfully ask that any modifications to this file be coordinated
  12  * with the public linux-omap@vger.kernel.org mailing list and the
  13  * authors above to ensure that the autogeneration scripts are kept
  14  * up-to-date with the file contents.
  15  */
  16
  17 #include <linux/io.h>
  18
  19 #include "omap_hwmod.h"
  20 #include "omap_hwmod_common_data.h"
  21 #include "cm1_7xx.h"
  22 #include "cm2_7xx.h"
  23 #include "prm7xx.h"
  24 #include "soc.h"
  25
  26 /* Base offset for all DRA7XX interrupts external to MPUSS */
  27 #define DRA7XX_IRQ_GIC_START    32
  28
  29 /*
  30  * IP blocks
  31  */
  32
  33 /*
  34  * 'dmm' class
  35  * instance(s): dmm
  36  */
  37 static struct omap_hwmod_class dra7xx_dmm_hwmod_class = {
  38         .name   = "dmm",
  39 };
  40
  41 /* dmm */
  42 static struct omap_hwmod dra7xx_dmm_hwmod = {
  43         .name           = "dmm",
  44         .class          = &dra7xx_dmm_hwmod_class,
  45         .clkdm_name     = "emif_clkdm",
  46         .prcm = {
  47                 .omap4 = {
  48                         .clkctrl_offs = DRA7XX_CM_EMIF_DMM_CLKCTRL_OFFSET,
  49                         .context_offs = DRA7XX_RM_EMIF_DMM_CONTEXT_OFFSET,
  50                 },
  51         },
  52 };
  53
  54 /*
  55  * 'l3' class
  56  * instance(s): l3_instr, l3_main_1, l3_main_2
  57  */
  58 static struct omap_hwmod_class dra7xx_l3_hwmod_class = {
  59         .name   = "l3",
  60 };
  61
  62 /* l3_instr */
  63 static struct omap_hwmod dra7xx_l3_instr_hwmod = {
  64         .name           = "l3_instr",
  65         .class          = &dra7xx_l3_hwmod_class,
  66         .clkdm_name     = "l3instr_clkdm",
  67         .prcm = {
  68                 .omap4 = {
  69                         .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
  70                         .context_offs = DRA7XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
  71                         .modulemode   = MODULEMODE_HWCTRL,
  72                 },
  73         },
  74 };
  75
  76 /* l3_main_1 */
  77 static struct omap_hwmod dra7xx_l3_main_1_hwmod = {
  78         .name           = "l3_main_1",
  79         .class          = &dra7xx_l3_hwmod_class,
  80         .clkdm_name     = "l3main1_clkdm",
  81         .prcm = {
  82                 .omap4 = {
  83                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET,
  84                         .context_offs = DRA7XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET,
  85                 },
  86         },
  87 };
  88
  89 /* l3_main_2 */
  90 static struct omap_hwmod dra7xx_l3_main_2_hwmod = {
  91         .name           = "l3_main_2",
  92         .class          = &dra7xx_l3_hwmod_class,
  93         .clkdm_name     = "l3instr_clkdm",
  94         .prcm = {
  95                 .omap4 = {
  96                         .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_MAIN_2_CLKCTRL_OFFSET,
  97                         .context_offs = DRA7XX_RM_L3INSTR_L3_MAIN_2_CONTEXT_OFFSET,
  98                         .modulemode   = MODULEMODE_HWCTRL,
  99                 },
 100         },
 101 };
 102
 103 /*
 104  * 'l4' class
 105  * instance(s): l4_cfg, l4_per1, l4_per2, l4_per3, l4_wkup
 106  */
 107 static struct omap_hwmod_class dra7xx_l4_hwmod_class = {
 108         .name   = "l4",
 109 };
 110
 111 /* l4_cfg */
 112 static struct omap_hwmod dra7xx_l4_cfg_hwmod = {
 113         .name           = "l4_cfg",
 114         .class          = &dra7xx_l4_hwmod_class,
 115         .clkdm_name     = "l4cfg_clkdm",
 116         .prcm = {
 117                 .omap4 = {
 118                         .clkctrl_offs = DRA7XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
 119                         .context_offs = DRA7XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
 120                 },
 121         },
 122 };
 123
 124 /* l4_per1 */
 125 static struct omap_hwmod dra7xx_l4_per1_hwmod = {
 126         .name           = "l4_per1",
 127         .class          = &dra7xx_l4_hwmod_class,
 128         .clkdm_name     = "l4per_clkdm",
 129         .prcm = {
 130                 .omap4 = {
 131                         .clkctrl_offs = DRA7XX_CM_L4PER_L4_PER1_CLKCTRL_OFFSET,
 132                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 133                 },
 134         },
 135 };
 136
 137 /* l4_per2 */
 138 static struct omap_hwmod dra7xx_l4_per2_hwmod = {
 139         .name           = "l4_per2",
 140         .class          = &dra7xx_l4_hwmod_class,
 141         .clkdm_name     = "l4per2_clkdm",
 142         .prcm = {
 143                 .omap4 = {
 144                         .clkctrl_offs = DRA7XX_CM_L4PER2_L4_PER2_CLKCTRL_OFFSET,
 145                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 146                 },
 147         },
 148 };
 149
 150 /* l4_per3 */
 151 static struct omap_hwmod dra7xx_l4_per3_hwmod = {
 152         .name           = "l4_per3",
 153         .class          = &dra7xx_l4_hwmod_class,
 154         .clkdm_name     = "l4per3_clkdm",
 155         .prcm = {
 156                 .omap4 = {
 157                         .clkctrl_offs = DRA7XX_CM_L4PER3_L4_PER3_CLKCTRL_OFFSET,
 158                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 159                 },
 160         },
 161 };
 162
 163 /* l4_wkup */
 164 static struct omap_hwmod dra7xx_l4_wkup_hwmod = {
 165         .name           = "l4_wkup",
 166         .class          = &dra7xx_l4_hwmod_class,
 167         .clkdm_name     = "wkupaon_clkdm",
 168         .prcm = {
 169                 .omap4 = {
 170                         .clkctrl_offs = DRA7XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET,
 171                         .context_offs = DRA7XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET,
 172                 },
 173         },
 174 };
 175
 176 /*
 177  * 'atl' class
 178  *
 179  */
 180
 181 static struct omap_hwmod_class dra7xx_atl_hwmod_class = {
 182         .name   = "atl",
 183 };
 184
 185 /* atl */
 186 static struct omap_hwmod dra7xx_atl_hwmod = {
 187         .name           = "atl",
 188         .class          = &dra7xx_atl_hwmod_class,
 189         .clkdm_name     = "atl_clkdm",
 190         .main_clk       = "atl_gfclk_mux",
 191         .prcm = {
 192                 .omap4 = {
 193                         .clkctrl_offs = DRA7XX_CM_ATL_ATL_CLKCTRL_OFFSET,
 194                         .context_offs = DRA7XX_RM_ATL_ATL_CONTEXT_OFFSET,
 195                         .modulemode   = MODULEMODE_SWCTRL,
 196                 },
 197         },
 198 };
 199
 200 /*
 201  * 'bb2d' class
 202  *
 203  */
 204
 205 static struct omap_hwmod_class dra7xx_bb2d_hwmod_class = {
 206         .name   = "bb2d",
 207 };
 208
 209 /* bb2d */
 210 static struct omap_hwmod dra7xx_bb2d_hwmod = {
 211         .name           = "bb2d",
 212         .class          = &dra7xx_bb2d_hwmod_class,
 213         .clkdm_name     = "dss_clkdm",
 214         .main_clk       = "dpll_core_h24x2_ck",
 215         .prcm = {
 216                 .omap4 = {
 217                         .clkctrl_offs = DRA7XX_CM_DSS_BB2D_CLKCTRL_OFFSET,
 218                         .context_offs = DRA7XX_RM_DSS_BB2D_CONTEXT_OFFSET,
 219                         .modulemode   = MODULEMODE_SWCTRL,
 220                 },
 221         },
 222 };
 223
 224 /*
 225  * 'counter' class
 226  *
 227  */
 228
 229 static struct omap_hwmod_class_sysconfig dra7xx_counter_sysc = {
 230         .rev_offs       = 0x0000,
 231         .sysc_offs      = 0x0010,
 232         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 233         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 234                            SIDLE_SMART_WKUP),
 235         .sysc_fields    = &omap_hwmod_sysc_type1,
 236 };
 237
 238 static struct omap_hwmod_class dra7xx_counter_hwmod_class = {
 239         .name   = "counter",
 240         .sysc   = &dra7xx_counter_sysc,
 241 };
 242
 243 /* counter_32k */
 244 static struct omap_hwmod dra7xx_counter_32k_hwmod = {
 245         .name           = "counter_32k",
 246         .class          = &dra7xx_counter_hwmod_class,
 247         .clkdm_name     = "wkupaon_clkdm",
 248         .flags          = HWMOD_SWSUP_SIDLE,
 249         .main_clk       = "wkupaon_iclk_mux",
 250         .prcm = {
 251                 .omap4 = {
 252                         .clkctrl_offs = DRA7XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET,
 253                         .context_offs = DRA7XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET,
 254                 },
 255         },
 256 };
 257
 258 /*
 259  * 'ctrl_module' class
 260  *
 261  */
 262
 263 static struct omap_hwmod_class dra7xx_ctrl_module_hwmod_class = {
 264         .name   = "ctrl_module",
 265 };
 266
 267 /* ctrl_module_wkup */
 268 static struct omap_hwmod dra7xx_ctrl_module_wkup_hwmod = {
 269         .name           = "ctrl_module_wkup",
 270         .class          = &dra7xx_ctrl_module_hwmod_class,
 271         .clkdm_name     = "wkupaon_clkdm",
 272         .prcm = {
 273                 .omap4 = {
 274                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 275                 },
 276         },
 277 };
 278
 279 /*
 280  * 'tpcc' class
 281  *
 282  */
 283 static struct omap_hwmod_class dra7xx_tpcc_hwmod_class = {
 284         .name           = "tpcc",
 285 };
 286
 287 static struct omap_hwmod dra7xx_tpcc_hwmod = {
 288         .name           = "tpcc",
 289         .class          = &dra7xx_tpcc_hwmod_class,
 290         .clkdm_name     = "l3main1_clkdm",
 291         .main_clk       = "l3_iclk_div",
 292         .prcm           = {
 293                 .omap4  = {
 294                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_TPCC_CLKCTRL_OFFSET,
 295                         .context_offs = DRA7XX_RM_L3MAIN1_TPCC_CONTEXT_OFFSET,
 296                 },
 297         },
 298 };
 299
 300 /*
 301  * 'tptc' class
 302  *
 303  */
 304 static struct omap_hwmod_class dra7xx_tptc_hwmod_class = {
 305         .name           = "tptc",
 306 };
 307
 308 /* tptc0 */
 309 static struct omap_hwmod dra7xx_tptc0_hwmod = {
 310         .name           = "tptc0",
 311         .class          = &dra7xx_tptc_hwmod_class,
 312         .clkdm_name     = "l3main1_clkdm",
 313         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
 314         .main_clk       = "l3_iclk_div",
 315         .prcm           = {
 316                 .omap4  = {
 317                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_TPTC1_CLKCTRL_OFFSET,
 318                         .context_offs = DRA7XX_RM_L3MAIN1_TPTC1_CONTEXT_OFFSET,
 319                         .modulemode   = MODULEMODE_HWCTRL,
 320                 },
 321         },
 322 };
 323
 324 /* tptc1 */
 325 static struct omap_hwmod dra7xx_tptc1_hwmod = {
 326         .name           = "tptc1",
 327         .class          = &dra7xx_tptc_hwmod_class,
 328         .clkdm_name     = "l3main1_clkdm",
 329         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
 330         .main_clk       = "l3_iclk_div",
 331         .prcm           = {
 332                 .omap4  = {
 333                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_TPTC2_CLKCTRL_OFFSET,
 334                         .context_offs = DRA7XX_RM_L3MAIN1_TPTC2_CONTEXT_OFFSET,
 335                         .modulemode   = MODULEMODE_HWCTRL,
 336                 },
 337         },
 338 };
 339
 340 /*
 341  * 'dss' class
 342  *
 343  */
 344
 345 static struct omap_hwmod_class_sysconfig dra7xx_dss_sysc = {
 346         .rev_offs       = 0x0000,
 347         .syss_offs      = 0x0014,
 348         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 349 };
 350
 351 static struct omap_hwmod_class dra7xx_dss_hwmod_class = {
 352         .name   = "dss",
 353         .sysc   = &dra7xx_dss_sysc,
 354         .reset  = omap_dss_reset,
 355 };
 356
 357 /* dss */
 358 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
 359         { .role = "dss_clk", .clk = "dss_dss_clk" },
 360         { .role = "hdmi_phy_clk", .clk = "dss_48mhz_clk" },
 361         { .role = "32khz_clk", .clk = "dss_32khz_clk" },
 362         { .role = "video2_clk", .clk = "dss_video2_clk" },
 363         { .role = "video1_clk", .clk = "dss_video1_clk" },
 364         { .role = "hdmi_clk", .clk = "dss_hdmi_clk" },
 365         { .role = "hdcp_clk", .clk = "dss_deshdcp_clk" },
 366 };
 367
 368 static struct omap_hwmod dra7xx_dss_hwmod = {
 369         .name           = "dss_core",
 370         .class          = &dra7xx_dss_hwmod_class,
 371         .clkdm_name     = "dss_clkdm",
 372         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 373         .main_clk       = "dss_dss_clk",
 374         .prcm = {
 375                 .omap4 = {
 376                         .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
 377                         .context_offs = DRA7XX_RM_DSS_DSS_CONTEXT_OFFSET,
 378                         .modulemode   = MODULEMODE_SWCTRL,
 379                 },
 380         },
 381         .opt_clks       = dss_opt_clks,
 382         .opt_clks_cnt   = ARRAY_SIZE(dss_opt_clks),
 383 };
 384
 385 /*
 386  * 'dispc' class
 387  * display controller
 388  */
 389
 390 static struct omap_hwmod_class_sysconfig dra7xx_dispc_sysc = {
 391         .rev_offs       = 0x0000,
 392         .sysc_offs      = 0x0010,
 393         .syss_offs      = 0x0014,
 394         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 395                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
 396                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 397                            SYSS_HAS_RESET_STATUS),
 398         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 399                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 400         .sysc_fields    = &omap_hwmod_sysc_type1,
 401 };
 402
 403 static struct omap_hwmod_class dra7xx_dispc_hwmod_class = {
 404         .name   = "dispc",
 405         .sysc   = &dra7xx_dispc_sysc,
 406 };
 407
 408 /* dss_dispc */
 409 /* dss_dispc dev_attr */
 410 static struct omap_dss_dispc_dev_attr dss_dispc_dev_attr = {
 411         .has_framedonetv_irq    = 1,
 412         .manager_count          = 4,
 413 };
 414
 415 static struct omap_hwmod dra7xx_dss_dispc_hwmod = {
 416         .name           = "dss_dispc",
 417         .class          = &dra7xx_dispc_hwmod_class,
 418         .clkdm_name     = "dss_clkdm",
 419         .main_clk       = "dss_dss_clk",
 420         .prcm = {
 421                 .omap4 = {
 422                         .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
 423                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 424                 },
 425         },
 426         .dev_attr       = &dss_dispc_dev_attr,
 427         .parent_hwmod   = &dra7xx_dss_hwmod,
 428 };
 429
 430 /*
 431  * 'hdmi' class
 432  * hdmi controller
 433  */
 434
 435 static struct omap_hwmod_class_sysconfig dra7xx_hdmi_sysc = {
 436         .rev_offs       = 0x0000,
 437         .sysc_offs      = 0x0010,
 438         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
 439                            SYSC_HAS_SOFTRESET),
 440         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 441                            SIDLE_SMART_WKUP),
 442         .sysc_fields    = &omap_hwmod_sysc_type2,
 443 };
 444
 445 static struct omap_hwmod_class dra7xx_hdmi_hwmod_class = {
 446         .name   = "hdmi",
 447         .sysc   = &dra7xx_hdmi_sysc,
 448 };
 449
 450 /* dss_hdmi */
 451
 452 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
 453         { .role = "sys_clk", .clk = "dss_hdmi_clk" },
 454 };
 455
 456 static struct omap_hwmod dra7xx_dss_hdmi_hwmod = {
 457         .name           = "dss_hdmi",
 458         .class          = &dra7xx_hdmi_hwmod_class,
 459         .clkdm_name     = "dss_clkdm",
 460         .main_clk       = "dss_48mhz_clk",
 461         .prcm = {
 462                 .omap4 = {
 463                         .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
 464                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 465                 },
 466         },
 467         .opt_clks       = dss_hdmi_opt_clks,
 468         .opt_clks_cnt   = ARRAY_SIZE(dss_hdmi_opt_clks),
 469         .parent_hwmod   = &dra7xx_dss_hwmod,
 470 };
 471
 472
 473
 474
 475
 476 /*
 477  * 'gpmc' class
 478  *
 479  */
 480
 481 static struct omap_hwmod_class_sysconfig dra7xx_gpmc_sysc = {
 482         .rev_offs       = 0x0000,
 483         .sysc_offs      = 0x0010,
 484         .syss_offs      = 0x0014,
 485         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
 486                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 487         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 488         .sysc_fields    = &omap_hwmod_sysc_type1,
 489 };
 490
 491 static struct omap_hwmod_class dra7xx_gpmc_hwmod_class = {
 492         .name   = "gpmc",
 493         .sysc   = &dra7xx_gpmc_sysc,
 494 };
 495
 496 /* gpmc */
 497
 498 static struct omap_hwmod dra7xx_gpmc_hwmod = {
 499         .name           = "gpmc",
 500         .class          = &dra7xx_gpmc_hwmod_class,
 501         .clkdm_name     = "l3main1_clkdm",
 502         /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
 503         .flags          = DEBUG_OMAP_GPMC_HWMOD_FLAGS,
 504         .main_clk       = "l3_iclk_div",
 505         .prcm = {
 506                 .omap4 = {
 507                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_GPMC_CLKCTRL_OFFSET,
 508                         .context_offs = DRA7XX_RM_L3MAIN1_GPMC_CONTEXT_OFFSET,
 509                         .modulemode   = MODULEMODE_HWCTRL,
 510                 },
 511         },
 512 };
 513
 514
 515
 516 /*
 517  * 'mpu' class
 518  *
 519  */
 520
 521 static struct omap_hwmod_class dra7xx_mpu_hwmod_class = {
 522         .name   = "mpu",
 523 };
 524
 525 /* mpu */
 526 static struct omap_hwmod dra7xx_mpu_hwmod = {
 527         .name           = "mpu",
 528         .class          = &dra7xx_mpu_hwmod_class,
 529         .clkdm_name     = "mpu_clkdm",
 530         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
 531         .main_clk       = "dpll_mpu_m2_ck",
 532         .prcm = {
 533                 .omap4 = {
 534                         .clkctrl_offs = DRA7XX_CM_MPU_MPU_CLKCTRL_OFFSET,
 535                         .context_offs = DRA7XX_RM_MPU_MPU_CONTEXT_OFFSET,
 536                 },
 537         },
 538 };
 539
 540
 541 /*
 542  * 'PCIE' class
 543  *
 544  */
 545
 546 /*
 547  * As noted in documentation for _reset() in omap_hwmod.c, the stock reset
 548  * functionality of OMAP HWMOD layer does not deassert the hardreset lines
 549  * associated with an IP automatically leaving the driver to handle that
 550  * by itself. This does not work for PCIeSS which needs the reset lines
 551  * deasserted for the driver to start accessing registers.
 552  *
 553  * We use a PCIeSS HWMOD class specific reset handler to deassert the hardreset
 554  * lines after asserting them.
 555  */
 556 int dra7xx_pciess_reset(struct omap_hwmod *oh)
 557 {
 558         int i;
 559
 560         for (i = 0; i < oh->rst_lines_cnt; i++) {
 561                 omap_hwmod_assert_hardreset(oh, oh->rst_lines[i].name);
 562                 omap_hwmod_deassert_hardreset(oh, oh->rst_lines[i].name);
 563         }
 564
 565         return 0;
 566 }
 567
 568 static struct omap_hwmod_class dra7xx_pciess_hwmod_class = {
 569         .name   = "pcie",
 570         .reset  = dra7xx_pciess_reset,
 571 };
 572
 573 /* pcie1 */
 574 static struct omap_hwmod_rst_info dra7xx_pciess1_resets[] = {
 575         { .name = "pcie", .rst_shift = 0 },
 576 };
 577
 578 static struct omap_hwmod dra7xx_pciess1_hwmod = {
 579         .name           = "pcie1",
 580         .class          = &dra7xx_pciess_hwmod_class,
 581         .clkdm_name     = "pcie_clkdm",
 582         .rst_lines      = dra7xx_pciess1_resets,
 583         .rst_lines_cnt  = ARRAY_SIZE(dra7xx_pciess1_resets),
 584         .main_clk       = "l4_root_clk_div",
 585         .prcm = {
 586                 .omap4 = {
 587                         .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET,
 588                         .rstctrl_offs = DRA7XX_RM_L3INIT_PCIESS_RSTCTRL_OFFSET,
 589                         .context_offs = DRA7XX_RM_L3INIT_PCIESS1_CONTEXT_OFFSET,
 590                         .modulemode   = MODULEMODE_SWCTRL,
 591                 },
 592         },
 593 };
 594
 595 /* pcie2 */
 596 static struct omap_hwmod_rst_info dra7xx_pciess2_resets[] = {
 597         { .name = "pcie", .rst_shift = 1 },
 598 };
 599
 600 /* pcie2 */
 601 static struct omap_hwmod dra7xx_pciess2_hwmod = {
 602         .name           = "pcie2",
 603         .class          = &dra7xx_pciess_hwmod_class,
 604         .clkdm_name     = "pcie_clkdm",
 605         .rst_lines      = dra7xx_pciess2_resets,
 606         .rst_lines_cnt  = ARRAY_SIZE(dra7xx_pciess2_resets),
 607         .main_clk       = "l4_root_clk_div",
 608         .prcm = {
 609                 .omap4 = {
 610                         .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL_OFFSET,
 611                         .rstctrl_offs = DRA7XX_RM_L3INIT_PCIESS_RSTCTRL_OFFSET,
 612                         .context_offs = DRA7XX_RM_L3INIT_PCIESS2_CONTEXT_OFFSET,
 613                         .modulemode   = MODULEMODE_SWCTRL,
 614                 },
 615         },
 616 };
 617
 618 /*
 619  * 'qspi' class
 620  *
 621  */
 622
 623 static struct omap_hwmod_class_sysconfig dra7xx_qspi_sysc = {
 624         .rev_offs       = 0,
 625         .sysc_offs      = 0x0010,
 626         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 627         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 628                            SIDLE_SMART_WKUP),
 629         .sysc_fields    = &omap_hwmod_sysc_type2,
 630 };
 631
 632 static struct omap_hwmod_class dra7xx_qspi_hwmod_class = {
 633         .name   = "qspi",
 634         .sysc   = &dra7xx_qspi_sysc,
 635 };
 636
 637 /* qspi */
 638 static struct omap_hwmod dra7xx_qspi_hwmod = {
 639         .name           = "qspi",
 640         .class          = &dra7xx_qspi_hwmod_class,
 641         .clkdm_name     = "l4per2_clkdm",
 642         .main_clk       = "qspi_gfclk_div",
 643         .prcm = {
 644                 .omap4 = {
 645                         .clkctrl_offs = DRA7XX_CM_L4PER2_QSPI_CLKCTRL_OFFSET,
 646                         .context_offs = DRA7XX_RM_L4PER2_QSPI_CONTEXT_OFFSET,
 647                         .modulemode   = MODULEMODE_SWCTRL,
 648                 },
 649         },
 650 };
 651
 652 /*
 653  * 'rtcss' class
 654  *
 655  */
 656 static struct omap_hwmod_class_sysconfig dra7xx_rtcss_sysc = {
 657         .rev_offs       = 0x0074,
 658         .sysc_offs      = 0x0078,
 659         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 660         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 661                            SIDLE_SMART_WKUP),
 662         .sysc_fields    = &omap_hwmod_sysc_type3,
 663 };
 664
 665 static struct omap_hwmod_class dra7xx_rtcss_hwmod_class = {
 666         .name   = "rtcss",
 667         .sysc   = &dra7xx_rtcss_sysc,
 668         .unlock = &omap_hwmod_rtc_unlock,
 669         .lock   = &omap_hwmod_rtc_lock,
 670 };
 671
 672 /* rtcss */
 673 static struct omap_hwmod dra7xx_rtcss_hwmod = {
 674         .name           = "rtcss",
 675         .class          = &dra7xx_rtcss_hwmod_class,
 676         .clkdm_name     = "rtc_clkdm",
 677         .main_clk       = "sys_32k_ck",
 678         .prcm = {
 679                 .omap4 = {
 680                         .clkctrl_offs = DRA7XX_CM_RTC_RTCSS_CLKCTRL_OFFSET,
 681                         .context_offs = DRA7XX_RM_RTC_RTCSS_CONTEXT_OFFSET,
 682                         .modulemode   = MODULEMODE_SWCTRL,
 683                 },
 684         },
 685 };
 686
 687 /*
 688  * 'sata' class
 689  *
 690  */
 691
 692 static struct omap_hwmod_class_sysconfig dra7xx_sata_sysc = {
 693         .rev_offs       = 0x00fc,
 694         .sysc_offs      = 0x0000,
 695         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
 696         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 697                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
 698                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
 699         .sysc_fields    = &omap_hwmod_sysc_type2,
 700 };
 701
 702 static struct omap_hwmod_class dra7xx_sata_hwmod_class = {
 703         .name   = "sata",
 704         .sysc   = &dra7xx_sata_sysc,
 705 };
 706
 707 /* sata */
 708
 709 static struct omap_hwmod dra7xx_sata_hwmod = {
 710         .name           = "sata",
 711         .class          = &dra7xx_sata_hwmod_class,
 712         .clkdm_name     = "l3init_clkdm",
 713         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
 714         .main_clk       = "func_48m_fclk",
 715         .mpu_rt_idx     = 1,
 716         .prcm = {
 717                 .omap4 = {
 718                         .clkctrl_offs = DRA7XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
 719                         .context_offs = DRA7XX_RM_L3INIT_SATA_CONTEXT_OFFSET,
 720                         .modulemode   = MODULEMODE_SWCTRL,
 721                 },
 722         },
 723 };
 724
 725 /*
 726  * 'timer' class
 727  *
 728  * This class contains several variants: ['timer_1ms', 'timer_secure',
 729  * 'timer']
 730  */
 731
 732 static struct omap_hwmod_class_sysconfig dra7xx_timer_1ms_sysc = {
 733         .rev_offs       = 0x0000,
 734         .sysc_offs      = 0x0010,
 735         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
 736                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
 737         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 738                            SIDLE_SMART_WKUP),
 739         .sysc_fields    = &omap_hwmod_sysc_type2,
 740 };
 741
 742 static struct omap_hwmod_class dra7xx_timer_1ms_hwmod_class = {
 743         .name   = "timer",
 744         .sysc   = &dra7xx_timer_1ms_sysc,
 745 };
 746
 747 static struct omap_hwmod_class_sysconfig dra7xx_timer_sysc = {
 748         .rev_offs       = 0x0000,
 749         .sysc_offs      = 0x0010,
 750         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
 751                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
 752         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 753                            SIDLE_SMART_WKUP),
 754         .sysc_fields    = &omap_hwmod_sysc_type2,
 755 };
 756
 757 static struct omap_hwmod_class dra7xx_timer_hwmod_class = {
 758         .name   = "timer",
 759         .sysc   = &dra7xx_timer_sysc,
 760 };
 761
 762 /* timer1 */
 763 static struct omap_hwmod dra7xx_timer1_hwmod = {
 764         .name           = "timer1",
 765         .class          = &dra7xx_timer_1ms_hwmod_class,
 766         .clkdm_name     = "wkupaon_clkdm",
 767         .main_clk       = "timer1_gfclk_mux",
 768         .prcm = {
 769                 .omap4 = {
 770                         .clkctrl_offs = DRA7XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET,
 771                         .context_offs = DRA7XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET,
 772                         .modulemode   = MODULEMODE_SWCTRL,
 773                 },
 774         },
 775 };
 776
 777 /* timer2 */
 778 static struct omap_hwmod dra7xx_timer2_hwmod = {
 779         .name           = "timer2",
 780         .class          = &dra7xx_timer_1ms_hwmod_class,
 781         .clkdm_name     = "l4per_clkdm",
 782         .main_clk       = "timer2_gfclk_mux",
 783         .prcm = {
 784                 .omap4 = {
 785                         .clkctrl_offs = DRA7XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET,
 786                         .context_offs = DRA7XX_RM_L4PER_TIMER2_CONTEXT_OFFSET,
 787                         .modulemode   = MODULEMODE_SWCTRL,
 788                 },
 789         },
 790 };
 791
 792 /* timer3 */
 793 static struct omap_hwmod dra7xx_timer3_hwmod = {
 794         .name           = "timer3",
 795         .class          = &dra7xx_timer_hwmod_class,
 796         .clkdm_name     = "l4per_clkdm",
 797         .main_clk       = "timer3_gfclk_mux",
 798         .prcm = {
 799                 .omap4 = {
 800                         .clkctrl_offs = DRA7XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET,
 801                         .context_offs = DRA7XX_RM_L4PER_TIMER3_CONTEXT_OFFSET,
 802                         .modulemode   = MODULEMODE_SWCTRL,
 803                 },
 804         },
 805 };
 806
 807 /* timer4 */
 808 static struct omap_hwmod dra7xx_timer4_hwmod = {
 809         .name           = "timer4",
 810         .class          = &dra7xx_timer_hwmod_class,
 811         .clkdm_name     = "l4per_clkdm",
 812         .main_clk       = "timer4_gfclk_mux",
 813         .prcm = {
 814                 .omap4 = {
 815                         .clkctrl_offs = DRA7XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET,
 816                         .context_offs = DRA7XX_RM_L4PER_TIMER4_CONTEXT_OFFSET,
 817                         .modulemode   = MODULEMODE_SWCTRL,
 818                 },
 819         },
 820 };
 821
 822 /*
 823  * 'usb_otg_ss' class
 824  *
 825  */
 826
 827 static struct omap_hwmod_class_sysconfig dra7xx_usb_otg_ss_sysc = {
 828         .rev_offs       = 0x0000,
 829         .sysc_offs      = 0x0010,
 830         .sysc_flags     = (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE |
 831                            SYSC_HAS_SIDLEMODE),
 832         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 833                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
 834                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
 835         .sysc_fields    = &omap_hwmod_sysc_type2,
 836 };
 837
 838 static struct omap_hwmod_class dra7xx_usb_otg_ss_hwmod_class = {
 839         .name   = "usb_otg_ss",
 840         .sysc   = &dra7xx_usb_otg_ss_sysc,
 841 };
 842
 843 /* usb_otg_ss1 */
 844 static struct omap_hwmod_opt_clk usb_otg_ss1_opt_clks[] = {
 845         { .role = "refclk960m", .clk = "usb_otg_ss1_refclk960m" },
 846 };
 847
 848 static struct omap_hwmod dra7xx_usb_otg_ss1_hwmod = {
 849         .name           = "usb_otg_ss1",
 850         .class          = &dra7xx_usb_otg_ss_hwmod_class,
 851         .clkdm_name     = "l3init_clkdm",
 852         .main_clk       = "dpll_core_h13x2_ck",
 853         .flags          = HWMOD_CLKDM_NOAUTO,
 854         .prcm = {
 855                 .omap4 = {
 856                         .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS1_CLKCTRL_OFFSET,
 857                         .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS1_CONTEXT_OFFSET,
 858                         .modulemode   = MODULEMODE_HWCTRL,
 859                 },
 860         },
 861         .opt_clks       = usb_otg_ss1_opt_clks,
 862         .opt_clks_cnt   = ARRAY_SIZE(usb_otg_ss1_opt_clks),
 863 };
 864
 865 /* usb_otg_ss2 */
 866 static struct omap_hwmod_opt_clk usb_otg_ss2_opt_clks[] = {
 867         { .role = "refclk960m", .clk = "usb_otg_ss2_refclk960m" },
 868 };
 869
 870 static struct omap_hwmod dra7xx_usb_otg_ss2_hwmod = {
 871         .name           = "usb_otg_ss2",
 872         .class          = &dra7xx_usb_otg_ss_hwmod_class,
 873         .clkdm_name     = "l3init_clkdm",
 874         .main_clk       = "dpll_core_h13x2_ck",
 875         .flags          = HWMOD_CLKDM_NOAUTO,
 876         .prcm = {
 877                 .omap4 = {
 878                         .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS2_CLKCTRL_OFFSET,
 879                         .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS2_CONTEXT_OFFSET,
 880                         .modulemode   = MODULEMODE_HWCTRL,
 881                 },
 882         },
 883         .opt_clks       = usb_otg_ss2_opt_clks,
 884         .opt_clks_cnt   = ARRAY_SIZE(usb_otg_ss2_opt_clks),
 885 };
 886
 887 /* usb_otg_ss3 */
 888 static struct omap_hwmod dra7xx_usb_otg_ss3_hwmod = {
 889         .name           = "usb_otg_ss3",
 890         .class          = &dra7xx_usb_otg_ss_hwmod_class,
 891         .clkdm_name     = "l3init_clkdm",
 892         .main_clk       = "dpll_core_h13x2_ck",
 893         .prcm = {
 894                 .omap4 = {
 895                         .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS3_CLKCTRL_OFFSET,
 896                         .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS3_CONTEXT_OFFSET,
 897                         .modulemode   = MODULEMODE_HWCTRL,
 898                 },
 899         },
 900 };
 901
 902 /* usb_otg_ss4 */
 903 static struct omap_hwmod dra7xx_usb_otg_ss4_hwmod = {
 904         .name           = "usb_otg_ss4",
 905         .class          = &dra7xx_usb_otg_ss_hwmod_class,
 906         .clkdm_name     = "l3init_clkdm",
 907         .main_clk       = "dpll_core_h13x2_ck",
 908         .prcm = {
 909                 .omap4 = {
 910                         .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS4_CLKCTRL_OFFSET,
 911                         .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS4_CONTEXT_OFFSET,
 912                         .modulemode   = MODULEMODE_HWCTRL,
 913                 },
 914         },
 915 };
 916
 917 /*
 918  * 'vcp' class
 919  *
 920  */
 921
 922 static struct omap_hwmod_class dra7xx_vcp_hwmod_class = {
 923         .name   = "vcp",
 924 };
 925
 926 /* vcp1 */
 927 static struct omap_hwmod dra7xx_vcp1_hwmod = {
 928         .name           = "vcp1",
 929         .class          = &dra7xx_vcp_hwmod_class,
 930         .clkdm_name     = "l3main1_clkdm",
 931         .main_clk       = "l3_iclk_div",
 932         .prcm = {
 933                 .omap4 = {
 934                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP1_CLKCTRL_OFFSET,
 935                         .context_offs = DRA7XX_RM_L3MAIN1_VCP1_CONTEXT_OFFSET,
 936                 },
 937         },
 938 };
 939
 940 /* vcp2 */
 941 static struct omap_hwmod dra7xx_vcp2_hwmod = {
 942         .name           = "vcp2",
 943         .class          = &dra7xx_vcp_hwmod_class,
 944         .clkdm_name     = "l3main1_clkdm",
 945         .main_clk       = "l3_iclk_div",
 946         .prcm = {
 947                 .omap4 = {
 948                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP2_CLKCTRL_OFFSET,
 949                         .context_offs = DRA7XX_RM_L3MAIN1_VCP2_CONTEXT_OFFSET,
 950                 },
 951         },
 952 };
 953
 954
 955
 956 /*
 957  * Interfaces
 958  */
 959
 960 /* l3_main_1 -> dmm */
 961 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dmm = {
 962         .master         = &dra7xx_l3_main_1_hwmod,
 963         .slave          = &dra7xx_dmm_hwmod,
 964         .clk            = "l3_iclk_div",
 965         .user           = OCP_USER_SDMA,
 966 };
 967
 968 /* l3_main_2 -> l3_instr */
 969 static struct omap_hwmod_ocp_if dra7xx_l3_main_2__l3_instr = {
 970         .master         = &dra7xx_l3_main_2_hwmod,
 971         .slave          = &dra7xx_l3_instr_hwmod,
 972         .clk            = "l3_iclk_div",
 973         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 974 };
 975
 976 /* l4_cfg -> l3_main_1 */
 977 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_1 = {
 978         .master         = &dra7xx_l4_cfg_hwmod,
 979         .slave          = &dra7xx_l3_main_1_hwmod,
 980         .clk            = "l3_iclk_div",
 981         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 982 };
 983
 984 /* mpu -> l3_main_1 */
 985 static struct omap_hwmod_ocp_if dra7xx_mpu__l3_main_1 = {
 986         .master         = &dra7xx_mpu_hwmod,
 987         .slave          = &dra7xx_l3_main_1_hwmod,
 988         .clk            = "l3_iclk_div",
 989         .user           = OCP_USER_MPU,
 990 };
 991
 992 /* l3_main_1 -> l3_main_2 */
 993 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l3_main_2 = {
 994         .master         = &dra7xx_l3_main_1_hwmod,
 995         .slave          = &dra7xx_l3_main_2_hwmod,
 996         .clk            = "l3_iclk_div",
 997         .user           = OCP_USER_MPU,
 998 };
 999
1000 /* l4_cfg -> l3_main_2 */
1001 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_2 = {
1002         .master         = &dra7xx_l4_cfg_hwmod,
1003         .slave          = &dra7xx_l3_main_2_hwmod,
1004         .clk            = "l3_iclk_div",
1005         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1006 };
1007
1008 /* l3_main_1 -> l4_cfg */
1009 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_cfg = {
1010         .master         = &dra7xx_l3_main_1_hwmod,
1011         .slave          = &dra7xx_l4_cfg_hwmod,
1012         .clk            = "l3_iclk_div",
1013         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1014 };
1015
1016 /* l3_main_1 -> l4_per1 */
1017 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per1 = {
1018         .master         = &dra7xx_l3_main_1_hwmod,
1019         .slave          = &dra7xx_l4_per1_hwmod,
1020         .clk            = "l3_iclk_div",
1021         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1022 };
1023
1024 /* l3_main_1 -> l4_per2 */
1025 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per2 = {
1026         .master         = &dra7xx_l3_main_1_hwmod,
1027         .slave          = &dra7xx_l4_per2_hwmod,
1028         .clk            = "l3_iclk_div",
1029         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1030 };
1031
1032 /* l3_main_1 -> l4_per3 */
1033 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per3 = {
1034         .master         = &dra7xx_l3_main_1_hwmod,
1035         .slave          = &dra7xx_l4_per3_hwmod,
1036         .clk            = "l3_iclk_div",
1037         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1038 };
1039
1040 /* l3_main_1 -> l4_wkup */
1041 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_wkup = {
1042         .master         = &dra7xx_l3_main_1_hwmod,
1043         .slave          = &dra7xx_l4_wkup_hwmod,
1044         .clk            = "wkupaon_iclk_mux",
1045         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1046 };
1047
1048 /* l4_per2 -> atl */
1049 static struct omap_hwmod_ocp_if dra7xx_l4_per2__atl = {
1050         .master         = &dra7xx_l4_per2_hwmod,
1051         .slave          = &dra7xx_atl_hwmod,
1052         .clk            = "l3_iclk_div",
1053         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1054 };
1055
1056 /* l3_main_1 -> bb2d */
1057 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__bb2d = {
1058         .master         = &dra7xx_l3_main_1_hwmod,
1059         .slave          = &dra7xx_bb2d_hwmod,
1060         .clk            = "l3_iclk_div",
1061         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1062 };
1063
1064 /* l4_wkup -> counter_32k */
1065 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__counter_32k = {
1066         .master         = &dra7xx_l4_wkup_hwmod,
1067         .slave          = &dra7xx_counter_32k_hwmod,
1068         .clk            = "wkupaon_iclk_mux",
1069         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1070 };
1071
1072 /* l4_wkup -> ctrl_module_wkup */
1073 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__ctrl_module_wkup = {
1074         .master         = &dra7xx_l4_wkup_hwmod,
1075         .slave          = &dra7xx_ctrl_module_wkup_hwmod,
1076         .clk            = "wkupaon_iclk_mux",
1077         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1078 };
1079
1080 /* l3_main_1 -> tpcc */
1081 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__tpcc = {
1082         .master         = &dra7xx_l3_main_1_hwmod,
1083         .slave          = &dra7xx_tpcc_hwmod,
1084         .clk            = "l3_iclk_div",
1085         .user           = OCP_USER_MPU,
1086 };
1087
1088 /* l3_main_1 -> tptc0 */
1089 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__tptc0 = {
1090         .master         = &dra7xx_l3_main_1_hwmod,
1091         .slave          = &dra7xx_tptc0_hwmod,
1092         .clk            = "l3_iclk_div",
1093         .user           = OCP_USER_MPU,
1094 };
1095
1096 /* l3_main_1 -> tptc1 */
1097 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__tptc1 = {
1098         .master         = &dra7xx_l3_main_1_hwmod,
1099         .slave          = &dra7xx_tptc1_hwmod,
1100         .clk            = "l3_iclk_div",
1101         .user           = OCP_USER_MPU,
1102 };
1103
1104 /* l3_main_1 -> dss */
1105 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dss = {
1106         .master         = &dra7xx_l3_main_1_hwmod,
1107         .slave          = &dra7xx_dss_hwmod,
1108         .clk            = "l3_iclk_div",
1109         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1110 };
1111
1112 /* l3_main_1 -> dispc */
1113 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dispc = {
1114         .master         = &dra7xx_l3_main_1_hwmod,
1115         .slave          = &dra7xx_dss_dispc_hwmod,
1116         .clk            = "l3_iclk_div",
1117         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1118 };
1119
1120 /* l3_main_1 -> dispc */
1121 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__hdmi = {
1122         .master         = &dra7xx_l3_main_1_hwmod,
1123         .slave          = &dra7xx_dss_hdmi_hwmod,
1124         .clk            = "l3_iclk_div",
1125         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1126 };
1127
1128 /* l3_main_1 -> gpmc */
1129 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__gpmc = {
1130         .master         = &dra7xx_l3_main_1_hwmod,
1131         .slave          = &dra7xx_gpmc_hwmod,
1132         .clk            = "l3_iclk_div",
1133         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1134 };
1135
1136 /* l4_cfg -> mpu */
1137 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mpu = {
1138         .master         = &dra7xx_l4_cfg_hwmod,
1139         .slave          = &dra7xx_mpu_hwmod,
1140         .clk            = "l3_iclk_div",
1141         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1142 };
1143
1144 /* l3_main_1 -> pciess1 */
1145 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pciess1 = {
1146         .master         = &dra7xx_l3_main_1_hwmod,
1147         .slave          = &dra7xx_pciess1_hwmod,
1148         .clk            = "l3_iclk_div",
1149         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1150 };
1151
1152 /* l4_cfg -> pciess1 */
1153 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pciess1 = {
1154         .master         = &dra7xx_l4_cfg_hwmod,
1155         .slave          = &dra7xx_pciess1_hwmod,
1156         .clk            = "l4_root_clk_div",
1157         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1158 };
1159
1160 /* l3_main_1 -> pciess2 */
1161 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pciess2 = {
1162         .master         = &dra7xx_l3_main_1_hwmod,
1163         .slave          = &dra7xx_pciess2_hwmod,
1164         .clk            = "l3_iclk_div",
1165         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1166 };
1167
1168 /* l4_cfg -> pciess2 */
1169 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pciess2 = {
1170         .master         = &dra7xx_l4_cfg_hwmod,
1171         .slave          = &dra7xx_pciess2_hwmod,
1172         .clk            = "l4_root_clk_div",
1173         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1174 };
1175
1176 /* l3_main_1 -> qspi */
1177 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__qspi = {
1178         .master         = &dra7xx_l3_main_1_hwmod,
1179         .slave          = &dra7xx_qspi_hwmod,
1180         .clk            = "l3_iclk_div",
1181         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1182 };
1183
1184 /* l4_per3 -> rtcss */
1185 static struct omap_hwmod_ocp_if dra7xx_l4_per3__rtcss = {
1186         .master         = &dra7xx_l4_per3_hwmod,
1187         .slave          = &dra7xx_rtcss_hwmod,
1188         .clk            = "l4_root_clk_div",
1189         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1190 };
1191
1192 /* l4_cfg -> sata */
1193 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__sata = {
1194         .master         = &dra7xx_l4_cfg_hwmod,
1195         .slave          = &dra7xx_sata_hwmod,
1196         .clk            = "l3_iclk_div",
1197         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1198 };
1199
1200 /* l4_wkup -> timer1 */
1201 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__timer1 = {
1202         .master         = &dra7xx_l4_wkup_hwmod,
1203         .slave          = &dra7xx_timer1_hwmod,
1204         .clk            = "wkupaon_iclk_mux",
1205         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1206 };
1207
1208 /* l4_per1 -> timer2 */
1209 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer2 = {
1210         .master         = &dra7xx_l4_per1_hwmod,
1211         .slave          = &dra7xx_timer2_hwmod,
1212         .clk            = "l3_iclk_div",
1213         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1214 };
1215
1216 /* l4_per1 -> timer3 */
1217 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer3 = {
1218         .master         = &dra7xx_l4_per1_hwmod,
1219         .slave          = &dra7xx_timer3_hwmod,
1220         .clk            = "l3_iclk_div",
1221         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1222 };
1223
1224 /* l4_per1 -> timer4 */
1225 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer4 = {
1226         .master         = &dra7xx_l4_per1_hwmod,
1227         .slave          = &dra7xx_timer4_hwmod,
1228         .clk            = "l3_iclk_div",
1229         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1230 };
1231
1232 /* l4_per3 -> usb_otg_ss1 */
1233 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss1 = {
1234         .master         = &dra7xx_l4_per3_hwmod,
1235         .slave          = &dra7xx_usb_otg_ss1_hwmod,
1236         .clk            = "dpll_core_h13x2_ck",
1237         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1238 };
1239
1240 /* l4_per3 -> usb_otg_ss2 */
1241 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss2 = {
1242         .master         = &dra7xx_l4_per3_hwmod,
1243         .slave          = &dra7xx_usb_otg_ss2_hwmod,
1244         .clk            = "dpll_core_h13x2_ck",
1245         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1246 };
1247
1248 /* l4_per3 -> usb_otg_ss3 */
1249 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss3 = {
1250         .master         = &dra7xx_l4_per3_hwmod,
1251         .slave          = &dra7xx_usb_otg_ss3_hwmod,
1252         .clk            = "dpll_core_h13x2_ck",
1253         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1254 };
1255
1256 /* l4_per3 -> usb_otg_ss4 */
1257 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss4 = {
1258         .master         = &dra7xx_l4_per3_hwmod,
1259         .slave          = &dra7xx_usb_otg_ss4_hwmod,
1260         .clk            = "dpll_core_h13x2_ck",
1261         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1262 };
1263
1264 /* l3_main_1 -> vcp1 */
1265 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp1 = {
1266         .master         = &dra7xx_l3_main_1_hwmod,
1267         .slave          = &dra7xx_vcp1_hwmod,
1268         .clk            = "l3_iclk_div",
1269         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1270 };
1271
1272 /* l4_per2 -> vcp1 */
1273 static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp1 = {
1274         .master         = &dra7xx_l4_per2_hwmod,
1275         .slave          = &dra7xx_vcp1_hwmod,
1276         .clk            = "l3_iclk_div",
1277         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1278 };
1279
1280 /* l3_main_1 -> vcp2 */
1281 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp2 = {
1282         .master         = &dra7xx_l3_main_1_hwmod,
1283         .slave          = &dra7xx_vcp2_hwmod,
1284         .clk            = "l3_iclk_div",
1285         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1286 };
1287
1288 /* l4_per2 -> vcp2 */
1289 static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp2 = {
1290         .master         = &dra7xx_l4_per2_hwmod,
1291         .slave          = &dra7xx_vcp2_hwmod,
1292         .clk            = "l3_iclk_div",
1293         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1294 };
1295
1296 static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
1297         &dra7xx_l3_main_1__dmm,
1298         &dra7xx_l3_main_2__l3_instr,
1299         &dra7xx_l4_cfg__l3_main_1,
1300         &dra7xx_mpu__l3_main_1,
1301         &dra7xx_l3_main_1__l3_main_2,
1302         &dra7xx_l4_cfg__l3_main_2,
1303         &dra7xx_l3_main_1__l4_cfg,
1304         &dra7xx_l3_main_1__l4_per1,
1305         &dra7xx_l3_main_1__l4_per2,
1306         &dra7xx_l3_main_1__l4_per3,
1307         &dra7xx_l3_main_1__l4_wkup,
1308         &dra7xx_l4_per2__atl,
1309         &dra7xx_l3_main_1__bb2d,
1310         &dra7xx_l4_wkup__counter_32k,
1311         &dra7xx_l4_wkup__ctrl_module_wkup,
1312         &dra7xx_l3_main_1__tpcc,
1313         &dra7xx_l3_main_1__tptc0,
1314         &dra7xx_l3_main_1__tptc1,
1315         &dra7xx_l3_main_1__dss,
1316         &dra7xx_l3_main_1__dispc,
1317         &dra7xx_l3_main_1__hdmi,
1318         &dra7xx_l3_main_1__gpmc,
1319         &dra7xx_l4_cfg__mpu,
1320         &dra7xx_l3_main_1__pciess1,
1321         &dra7xx_l4_cfg__pciess1,
1322         &dra7xx_l3_main_1__pciess2,
1323         &dra7xx_l4_cfg__pciess2,
1324         &dra7xx_l3_main_1__qspi,
1325         &dra7xx_l4_cfg__sata,
1326         &dra7xx_l4_wkup__timer1,
1327         &dra7xx_l4_per1__timer2,
1328         &dra7xx_l4_per1__timer3,
1329         &dra7xx_l4_per1__timer4,
1330         &dra7xx_l4_per3__usb_otg_ss1,
1331         &dra7xx_l4_per3__usb_otg_ss2,
1332         &dra7xx_l4_per3__usb_otg_ss3,
1333         &dra7xx_l3_main_1__vcp1,
1334         &dra7xx_l4_per2__vcp1,
1335         &dra7xx_l3_main_1__vcp2,
1336         &dra7xx_l4_per2__vcp2,
1337         NULL,
1338 };
1339
1340 /* SoC variant specific hwmod links */
1341 static struct omap_hwmod_ocp_if *dra76x_hwmod_ocp_ifs[] __initdata = {
1342         &dra7xx_l4_per3__usb_otg_ss4,
1343         NULL,
1344 };
1345
1346 static struct omap_hwmod_ocp_if *acd_76x_hwmod_ocp_ifs[] __initdata = {
1347         NULL,
1348 };
1349
1350 static struct omap_hwmod_ocp_if *dra74x_hwmod_ocp_ifs[] __initdata = {
1351         &dra7xx_l4_per3__usb_otg_ss4,
1352         NULL,
1353 };
1354
1355 static struct omap_hwmod_ocp_if *dra72x_hwmod_ocp_ifs[] __initdata = {
1356         NULL,
1357 };
1358
1359 static struct omap_hwmod_ocp_if *rtc_hwmod_ocp_ifs[] __initdata = {
1360         &dra7xx_l4_per3__rtcss,
1361         NULL,
1362 };
1363
1364 int __init dra7xx_hwmod_init(void)
1365 {
1366         int ret;
1367
1368         omap_hwmod_init();
1369         ret = omap_hwmod_register_links(dra7xx_hwmod_ocp_ifs);
1370
1371         if (!ret && soc_is_dra74x()) {
1372                 ret = omap_hwmod_register_links(dra74x_hwmod_ocp_ifs);
1373                 if (!ret)
1374                         ret = omap_hwmod_register_links(rtc_hwmod_ocp_ifs);
1375         } else if (!ret && soc_is_dra72x()) {
1376                 ret = omap_hwmod_register_links(dra72x_hwmod_ocp_ifs);
1377                 if (!ret && !of_machine_is_compatible("ti,dra718"))
1378                         ret = omap_hwmod_register_links(rtc_hwmod_ocp_ifs);
1379         } else if (!ret && soc_is_dra76x()) {
1380                 ret = omap_hwmod_register_links(dra76x_hwmod_ocp_ifs);
1381
1382                 if (!ret && soc_is_dra76x_acd()) {
1383                         ret = omap_hwmod_register_links(acd_76x_hwmod_ocp_ifs);
1384                 } else if (!ret && soc_is_dra76x_abz()) {
1385                         ret = omap_hwmod_register_links(rtc_hwmod_ocp_ifs);
1386                 }
1387         }
1388
1389         return ret;
1390 }