4 * Copyright (C) 2010 Texas Instruments, Inc. - http://www.ti.com/
5 * Copyright (C) 2013 SKTB SKiT, http://www.skitlab.ru/
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation version 2.
11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12 * kind, whether express or implied; without even the implied warranty
13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
18 #include <linux/platform_data/gpio-omap.h>
19 #include <linux/platform_data/hsmmc-omap.h>
20 #include <linux/platform_data/spi-omap2-mcspi.h>
21 #include <plat/dmtimer.h>
23 #include "omap_hwmod_common_data.h"
29 * DM816X hardware modules integration data
31 * Note: This is incomplete and at present, not generated from h/w database.
35 * Common alwon .clkctrl_offs from dm814x TRM "Table 2-278. CM_ALWON REGISTERS"
36 * also dm816x TRM 18.7.17 CM_ALWON device register values minus 0x1400.
38 #define DM81XX_CM_ALWON_MCASP0_CLKCTRL 0x140
39 #define DM81XX_CM_ALWON_MCASP1_CLKCTRL 0x144
40 #define DM81XX_CM_ALWON_MCASP2_CLKCTRL 0x148
41 #define DM81XX_CM_ALWON_MCBSP_CLKCTRL 0x14c
42 #define DM81XX_CM_ALWON_UART_0_CLKCTRL 0x150
43 #define DM81XX_CM_ALWON_UART_1_CLKCTRL 0x154
44 #define DM81XX_CM_ALWON_UART_2_CLKCTRL 0x158
45 #define DM81XX_CM_ALWON_GPIO_0_CLKCTRL 0x15c
46 #define DM81XX_CM_ALWON_GPIO_1_CLKCTRL 0x160
47 #define DM81XX_CM_ALWON_I2C_0_CLKCTRL 0x164
48 #define DM81XX_CM_ALWON_I2C_1_CLKCTRL 0x168
49 #define DM81XX_CM_ALWON_WDTIMER_CLKCTRL 0x18c
50 #define DM81XX_CM_ALWON_SPI_CLKCTRL 0x190
51 #define DM81XX_CM_ALWON_MAILBOX_CLKCTRL 0x194
52 #define DM81XX_CM_ALWON_SPINBOX_CLKCTRL 0x198
53 #define DM81XX_CM_ALWON_MMUDATA_CLKCTRL 0x19c
54 #define DM81XX_CM_ALWON_MMUCFG_CLKCTRL 0x1a8
55 #define DM81XX_CM_ALWON_CONTROL_CLKCTRL 0x1c4
56 #define DM81XX_CM_ALWON_GPMC_CLKCTRL 0x1d0
57 #define DM81XX_CM_ALWON_ETHERNET_0_CLKCTRL 0x1d4
58 #define DM81XX_CM_ALWON_L3_CLKCTRL 0x1e4
59 #define DM81XX_CM_ALWON_L4HS_CLKCTRL 0x1e8
60 #define DM81XX_CM_ALWON_L4LS_CLKCTRL 0x1ec
61 #define DM81XX_CM_ALWON_RTC_CLKCTRL 0x1f0
62 #define DM81XX_CM_ALWON_TPCC_CLKCTRL 0x1f4
63 #define DM81XX_CM_ALWON_TPTC0_CLKCTRL 0x1f8
64 #define DM81XX_CM_ALWON_TPTC1_CLKCTRL 0x1fc
65 #define DM81XX_CM_ALWON_TPTC2_CLKCTRL 0x200
66 #define DM81XX_CM_ALWON_TPTC3_CLKCTRL 0x204
68 /* Registers specific to dm814x */
69 #define DM814X_CM_ALWON_MCASP_3_4_5_CLKCTRL 0x16c
70 #define DM814X_CM_ALWON_ATL_CLKCTRL 0x170
71 #define DM814X_CM_ALWON_MLB_CLKCTRL 0x174
72 #define DM814X_CM_ALWON_PATA_CLKCTRL 0x178
73 #define DM814X_CM_ALWON_UART_3_CLKCTRL 0x180
74 #define DM814X_CM_ALWON_UART_4_CLKCTRL 0x184
75 #define DM814X_CM_ALWON_UART_5_CLKCTRL 0x188
76 #define DM814X_CM_ALWON_OCM_0_CLKCTRL 0x1b4
77 #define DM814X_CM_ALWON_VCP_CLKCTRL 0x1b8
78 #define DM814X_CM_ALWON_MPU_CLKCTRL 0x1dc
79 #define DM814X_CM_ALWON_DEBUGSS_CLKCTRL 0x1e0
80 #define DM814X_CM_ALWON_DCAN_0_1_CLKCTRL 0x218
81 #define DM814X_CM_ALWON_MMCHS_0_CLKCTRL 0x21c
82 #define DM814X_CM_ALWON_MMCHS_1_CLKCTRL 0x220
83 #define DM814X_CM_ALWON_MMCHS_2_CLKCTRL 0x224
84 #define DM814X_CM_ALWON_CUST_EFUSE_CLKCTRL 0x228
86 /* Registers specific to dm816x */
87 #define DM816X_DM_ALWON_BASE 0x1400
88 #define DM816X_CM_ALWON_TIMER_1_CLKCTRL (0x1570 - DM816X_DM_ALWON_BASE)
89 #define DM816X_CM_ALWON_TIMER_2_CLKCTRL (0x1574 - DM816X_DM_ALWON_BASE)
90 #define DM816X_CM_ALWON_TIMER_3_CLKCTRL (0x1578 - DM816X_DM_ALWON_BASE)
91 #define DM816X_CM_ALWON_TIMER_4_CLKCTRL (0x157c - DM816X_DM_ALWON_BASE)
92 #define DM816X_CM_ALWON_TIMER_5_CLKCTRL (0x1580 - DM816X_DM_ALWON_BASE)
93 #define DM816X_CM_ALWON_TIMER_6_CLKCTRL (0x1584 - DM816X_DM_ALWON_BASE)
94 #define DM816X_CM_ALWON_TIMER_7_CLKCTRL (0x1588 - DM816X_DM_ALWON_BASE)
95 #define DM816X_CM_ALWON_SDIO_CLKCTRL (0x15b0 - DM816X_DM_ALWON_BASE)
96 #define DM816X_CM_ALWON_OCMC_0_CLKCTRL (0x15b4 - DM816X_DM_ALWON_BASE)
97 #define DM816X_CM_ALWON_OCMC_1_CLKCTRL (0x15b8 - DM816X_DM_ALWON_BASE)
98 #define DM816X_CM_ALWON_ETHERNET_1_CLKCTRL (0x15d8 - DM816X_DM_ALWON_BASE)
99 #define DM816X_CM_ALWON_MPU_CLKCTRL (0x15dc - DM816X_DM_ALWON_BASE)
100 #define DM816X_CM_ALWON_SR_0_CLKCTRL (0x1608 - DM816X_DM_ALWON_BASE)
101 #define DM816X_CM_ALWON_SR_1_CLKCTRL (0x160c - DM816X_DM_ALWON_BASE)
104 * The default .clkctrl_offs field is offset from CM_DEFAULT, that's
105 * TRM 18.7.6 CM_DEFAULT device register values minus 0x500
107 #define DM816X_CM_DEFAULT_OFFSET 0x500
108 #define DM816X_CM_DEFAULT_USB_CLKCTRL (0x558 - DM816X_CM_DEFAULT_OFFSET)
110 /* L3 Interconnect entries clocked at 125, 250 and 500MHz */
111 static struct omap_hwmod dm81xx_alwon_l3_slow_hwmod = {
112 .name = "alwon_l3_slow",
113 .clkdm_name = "alwon_l3s_clkdm",
114 .class = &l3_hwmod_class,
115 .flags = HWMOD_NO_IDLEST,
118 static struct omap_hwmod dm81xx_default_l3_slow_hwmod = {
119 .name = "default_l3_slow",
120 .clkdm_name = "default_l3_slow_clkdm",
121 .class = &l3_hwmod_class,
122 .flags = HWMOD_NO_IDLEST,
125 static struct omap_hwmod dm81xx_alwon_l3_med_hwmod = {
127 .clkdm_name = "alwon_l3_med_clkdm",
128 .class = &l3_hwmod_class,
129 .flags = HWMOD_NO_IDLEST,
132 static struct omap_hwmod dm81xx_alwon_l3_fast_hwmod = {
134 .clkdm_name = "alwon_l3_fast_clkdm",
135 .class = &l3_hwmod_class,
136 .flags = HWMOD_NO_IDLEST,
140 * L4 standard peripherals, see TRM table 1-12 for devices using this.
141 * See TRM table 1-73 for devices using the 125MHz SYSCLK6 clock.
143 static struct omap_hwmod dm81xx_l4_ls_hwmod = {
145 .clkdm_name = "alwon_l3s_clkdm",
146 .class = &l4_hwmod_class,
147 .flags = HWMOD_NO_IDLEST,
151 * L4 high-speed peripherals. For devices using this, please see the TRM
152 * table 1-13. On dm816x, only EMAC, MDIO and SATA use this. See also TRM
153 * table 1-73 for devices using 250MHz SYSCLK5 clock.
155 static struct omap_hwmod dm81xx_l4_hs_hwmod = {
157 .clkdm_name = "alwon_l3_med_clkdm",
158 .class = &l4_hwmod_class,
159 .flags = HWMOD_NO_IDLEST,
162 /* L3 slow -> L4 ls peripheral interface running at 125MHz */
163 static struct omap_hwmod_ocp_if dm81xx_alwon_l3_slow__l4_ls = {
164 .master = &dm81xx_alwon_l3_slow_hwmod,
165 .slave = &dm81xx_l4_ls_hwmod,
166 .user = OCP_USER_MPU,
169 /* L3 med -> L4 fast peripheral interface running at 250MHz */
170 static struct omap_hwmod_ocp_if dm81xx_alwon_l3_slow__l4_hs = {
171 .master = &dm81xx_alwon_l3_med_hwmod,
172 .slave = &dm81xx_l4_hs_hwmod,
173 .user = OCP_USER_MPU,
177 static struct omap_hwmod dm814x_mpu_hwmod = {
179 .clkdm_name = "alwon_l3s_clkdm",
180 .class = &mpu_hwmod_class,
181 .flags = HWMOD_INIT_NO_IDLE,
182 .main_clk = "mpu_ck",
185 .clkctrl_offs = DM814X_CM_ALWON_MPU_CLKCTRL,
186 .modulemode = MODULEMODE_SWCTRL,
191 static struct omap_hwmod_ocp_if dm814x_mpu__alwon_l3_slow = {
192 .master = &dm814x_mpu_hwmod,
193 .slave = &dm81xx_alwon_l3_slow_hwmod,
194 .user = OCP_USER_MPU,
197 /* L3 med peripheral interface running at 200MHz */
198 static struct omap_hwmod_ocp_if dm814x_mpu__alwon_l3_med = {
199 .master = &dm814x_mpu_hwmod,
200 .slave = &dm81xx_alwon_l3_med_hwmod,
201 .user = OCP_USER_MPU,
204 static struct omap_hwmod dm816x_mpu_hwmod = {
206 .clkdm_name = "alwon_mpu_clkdm",
207 .class = &mpu_hwmod_class,
208 .flags = HWMOD_INIT_NO_IDLE,
209 .main_clk = "mpu_ck",
212 .clkctrl_offs = DM816X_CM_ALWON_MPU_CLKCTRL,
213 .modulemode = MODULEMODE_SWCTRL,
218 static struct omap_hwmod_ocp_if dm816x_mpu__alwon_l3_slow = {
219 .master = &dm816x_mpu_hwmod,
220 .slave = &dm81xx_alwon_l3_slow_hwmod,
221 .user = OCP_USER_MPU,
224 /* L3 med peripheral interface running at 250MHz */
225 static struct omap_hwmod_ocp_if dm816x_mpu__alwon_l3_med = {
226 .master = &dm816x_mpu_hwmod,
227 .slave = &dm81xx_alwon_l3_med_hwmod,
228 .user = OCP_USER_MPU,
232 static struct omap_hwmod_class_sysconfig uart_sysc = {
236 .sysc_flags = SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
237 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
238 SYSS_HAS_RESET_STATUS,
239 .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
241 .sysc_fields = &omap_hwmod_sysc_type1,
244 static struct omap_hwmod_class uart_class = {
249 static struct omap_hwmod dm81xx_uart1_hwmod = {
251 .clkdm_name = "alwon_l3s_clkdm",
252 .main_clk = "sysclk10_ck",
255 .clkctrl_offs = DM81XX_CM_ALWON_UART_0_CLKCTRL,
256 .modulemode = MODULEMODE_SWCTRL,
259 .class = &uart_class,
260 .flags = DEBUG_TI81XXUART1_FLAGS,
263 static struct omap_hwmod_ocp_if dm81xx_l4_ls__uart1 = {
264 .master = &dm81xx_l4_ls_hwmod,
265 .slave = &dm81xx_uart1_hwmod,
267 .user = OCP_USER_MPU,
270 static struct omap_hwmod dm81xx_uart2_hwmod = {
272 .clkdm_name = "alwon_l3s_clkdm",
273 .main_clk = "sysclk10_ck",
276 .clkctrl_offs = DM81XX_CM_ALWON_UART_1_CLKCTRL,
277 .modulemode = MODULEMODE_SWCTRL,
280 .class = &uart_class,
281 .flags = DEBUG_TI81XXUART2_FLAGS,
284 static struct omap_hwmod_ocp_if dm81xx_l4_ls__uart2 = {
285 .master = &dm81xx_l4_ls_hwmod,
286 .slave = &dm81xx_uart2_hwmod,
288 .user = OCP_USER_MPU,
291 static struct omap_hwmod dm81xx_uart3_hwmod = {
293 .clkdm_name = "alwon_l3s_clkdm",
294 .main_clk = "sysclk10_ck",
297 .clkctrl_offs = DM81XX_CM_ALWON_UART_2_CLKCTRL,
298 .modulemode = MODULEMODE_SWCTRL,
301 .class = &uart_class,
302 .flags = DEBUG_TI81XXUART3_FLAGS,
305 static struct omap_hwmod_ocp_if dm81xx_l4_ls__uart3 = {
306 .master = &dm81xx_l4_ls_hwmod,
307 .slave = &dm81xx_uart3_hwmod,
309 .user = OCP_USER_MPU,
312 static struct omap_hwmod_class_sysconfig wd_timer_sysc = {
316 .sysc_flags = SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET |
317 SYSS_HAS_RESET_STATUS,
318 .sysc_fields = &omap_hwmod_sysc_type1,
321 static struct omap_hwmod_class wd_timer_class = {
323 .sysc = &wd_timer_sysc,
324 .pre_shutdown = &omap2_wd_timer_disable,
325 .reset = &omap2_wd_timer_reset,
328 static struct omap_hwmod dm81xx_wd_timer_hwmod = {
330 .clkdm_name = "alwon_l3s_clkdm",
331 .main_clk = "sysclk18_ck",
332 .flags = HWMOD_NO_IDLEST,
335 .clkctrl_offs = DM81XX_CM_ALWON_WDTIMER_CLKCTRL,
336 .modulemode = MODULEMODE_SWCTRL,
339 .class = &wd_timer_class,
342 static struct omap_hwmod_ocp_if dm81xx_l4_ls__wd_timer1 = {
343 .master = &dm81xx_l4_ls_hwmod,
344 .slave = &dm81xx_wd_timer_hwmod,
346 .user = OCP_USER_MPU,
350 static struct omap_hwmod_class_sysconfig i2c_sysc = {
354 .sysc_flags = SYSC_HAS_SIDLEMODE |
355 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
357 .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART,
358 .sysc_fields = &omap_hwmod_sysc_type1,
361 static struct omap_hwmod_class i2c_class = {
366 static struct omap_hwmod dm81xx_i2c1_hwmod = {
368 .clkdm_name = "alwon_l3s_clkdm",
369 .main_clk = "sysclk10_ck",
372 .clkctrl_offs = DM81XX_CM_ALWON_I2C_0_CLKCTRL,
373 .modulemode = MODULEMODE_SWCTRL,
379 static struct omap_hwmod_ocp_if dm81xx_l4_ls__i2c1 = {
380 .master = &dm81xx_l4_ls_hwmod,
381 .slave = &dm81xx_i2c1_hwmod,
383 .user = OCP_USER_MPU,
386 static struct omap_hwmod dm81xx_i2c2_hwmod = {
388 .clkdm_name = "alwon_l3s_clkdm",
389 .main_clk = "sysclk10_ck",
392 .clkctrl_offs = DM81XX_CM_ALWON_I2C_1_CLKCTRL,
393 .modulemode = MODULEMODE_SWCTRL,
399 static struct omap_hwmod_class_sysconfig dm81xx_elm_sysc = {
403 .sysc_flags = SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
405 SYSS_HAS_RESET_STATUS,
406 .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART,
407 .sysc_fields = &omap_hwmod_sysc_type1,
410 static struct omap_hwmod_ocp_if dm81xx_l4_ls__i2c2 = {
411 .master = &dm81xx_l4_ls_hwmod,
412 .slave = &dm81xx_i2c2_hwmod,
414 .user = OCP_USER_MPU,
417 static struct omap_hwmod_class dm81xx_elm_hwmod_class = {
419 .sysc = &dm81xx_elm_sysc,
422 static struct omap_hwmod dm81xx_elm_hwmod = {
424 .clkdm_name = "alwon_l3s_clkdm",
425 .class = &dm81xx_elm_hwmod_class,
426 .main_clk = "sysclk6_ck",
429 static struct omap_hwmod_ocp_if dm81xx_l4_ls__elm = {
430 .master = &dm81xx_l4_ls_hwmod,
431 .slave = &dm81xx_elm_hwmod,
432 .user = OCP_USER_MPU,
435 static struct omap_hwmod_class_sysconfig dm81xx_gpio_sysc = {
439 .sysc_flags = SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
440 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
441 SYSS_HAS_RESET_STATUS,
442 .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
444 .sysc_fields = &omap_hwmod_sysc_type1,
447 static struct omap_hwmod_class dm81xx_gpio_hwmod_class = {
449 .sysc = &dm81xx_gpio_sysc,
453 static struct omap_gpio_dev_attr gpio_dev_attr = {
458 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
459 { .role = "dbclk", .clk = "sysclk18_ck" },
462 static struct omap_hwmod dm81xx_gpio1_hwmod = {
464 .clkdm_name = "alwon_l3s_clkdm",
465 .class = &dm81xx_gpio_hwmod_class,
466 .main_clk = "sysclk6_ck",
469 .clkctrl_offs = DM81XX_CM_ALWON_GPIO_0_CLKCTRL,
470 .modulemode = MODULEMODE_SWCTRL,
473 .opt_clks = gpio1_opt_clks,
474 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
475 .dev_attr = &gpio_dev_attr,
478 static struct omap_hwmod_ocp_if dm81xx_l4_ls__gpio1 = {
479 .master = &dm81xx_l4_ls_hwmod,
480 .slave = &dm81xx_gpio1_hwmod,
481 .user = OCP_USER_MPU,
484 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
485 { .role = "dbclk", .clk = "sysclk18_ck" },
488 static struct omap_hwmod dm81xx_gpio2_hwmod = {
490 .clkdm_name = "alwon_l3s_clkdm",
491 .class = &dm81xx_gpio_hwmod_class,
492 .main_clk = "sysclk6_ck",
495 .clkctrl_offs = DM81XX_CM_ALWON_GPIO_1_CLKCTRL,
496 .modulemode = MODULEMODE_SWCTRL,
499 .opt_clks = gpio2_opt_clks,
500 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
501 .dev_attr = &gpio_dev_attr,
504 static struct omap_hwmod_ocp_if dm81xx_l4_ls__gpio2 = {
505 .master = &dm81xx_l4_ls_hwmod,
506 .slave = &dm81xx_gpio2_hwmod,
507 .user = OCP_USER_MPU,
510 static struct omap_hwmod_class_sysconfig dm81xx_gpmc_sysc = {
514 .sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
515 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS,
516 .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART,
517 .sysc_fields = &omap_hwmod_sysc_type1,
520 static struct omap_hwmod_class dm81xx_gpmc_hwmod_class = {
522 .sysc = &dm81xx_gpmc_sysc,
525 static struct omap_hwmod dm81xx_gpmc_hwmod = {
527 .clkdm_name = "alwon_l3s_clkdm",
528 .class = &dm81xx_gpmc_hwmod_class,
529 .main_clk = "sysclk6_ck",
530 /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
531 .flags = DEBUG_OMAP_GPMC_HWMOD_FLAGS,
534 .clkctrl_offs = DM81XX_CM_ALWON_GPMC_CLKCTRL,
535 .modulemode = MODULEMODE_SWCTRL,
540 static struct omap_hwmod_ocp_if dm81xx_alwon_l3_slow__gpmc = {
541 .master = &dm81xx_alwon_l3_slow_hwmod,
542 .slave = &dm81xx_gpmc_hwmod,
543 .user = OCP_USER_MPU,
546 static struct omap_hwmod_class_sysconfig dm81xx_usbhsotg_sysc = {
549 .sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
551 .idlemodes = SIDLE_SMART | MSTANDBY_FORCE | MSTANDBY_SMART,
552 .sysc_fields = &omap_hwmod_sysc_type2,
555 static struct omap_hwmod_class dm81xx_usbotg_class = {
557 .sysc = &dm81xx_usbhsotg_sysc,
560 static struct omap_hwmod dm81xx_usbss_hwmod = {
561 .name = "usb_otg_hs",
562 .clkdm_name = "default_l3_slow_clkdm",
563 .main_clk = "sysclk6_ck",
566 .clkctrl_offs = DM816X_CM_DEFAULT_USB_CLKCTRL,
567 .modulemode = MODULEMODE_SWCTRL,
570 .class = &dm81xx_usbotg_class,
573 static struct omap_hwmod_ocp_if dm81xx_default_l3_slow__usbss = {
574 .master = &dm81xx_default_l3_slow_hwmod,
575 .slave = &dm81xx_usbss_hwmod,
577 .user = OCP_USER_MPU,
580 static struct omap_hwmod_class_sysconfig dm816x_timer_sysc = {
584 .sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET,
585 .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
587 .sysc_fields = &omap_hwmod_sysc_type2,
590 static struct omap_hwmod_class dm816x_timer_hwmod_class = {
592 .sysc = &dm816x_timer_sysc,
595 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
596 .timer_capability = OMAP_TIMER_ALWON,
599 static struct omap_hwmod dm814x_timer1_hwmod = {
601 .clkdm_name = "alwon_l3s_clkdm",
602 .main_clk = "timer_sys_ck",
603 .dev_attr = &capability_alwon_dev_attr,
604 .class = &dm816x_timer_hwmod_class,
605 .flags = HWMOD_NO_IDLEST,
608 static struct omap_hwmod_ocp_if dm814x_l4_ls__timer1 = {
609 .master = &dm81xx_l4_ls_hwmod,
610 .slave = &dm814x_timer1_hwmod,
611 .clk = "timer_sys_ck",
612 .user = OCP_USER_MPU,
615 static struct omap_hwmod dm816x_timer1_hwmod = {
617 .clkdm_name = "alwon_l3s_clkdm",
618 .main_clk = "timer1_fck",
621 .clkctrl_offs = DM816X_CM_ALWON_TIMER_1_CLKCTRL,
622 .modulemode = MODULEMODE_SWCTRL,
625 .dev_attr = &capability_alwon_dev_attr,
626 .class = &dm816x_timer_hwmod_class,
629 static struct omap_hwmod_ocp_if dm816x_l4_ls__timer1 = {
630 .master = &dm81xx_l4_ls_hwmod,
631 .slave = &dm816x_timer1_hwmod,
633 .user = OCP_USER_MPU,
636 static struct omap_hwmod dm814x_timer2_hwmod = {
638 .clkdm_name = "alwon_l3s_clkdm",
639 .main_clk = "timer_sys_ck",
640 .dev_attr = &capability_alwon_dev_attr,
641 .class = &dm816x_timer_hwmod_class,
642 .flags = HWMOD_NO_IDLEST,
645 static struct omap_hwmod_ocp_if dm814x_l4_ls__timer2 = {
646 .master = &dm81xx_l4_ls_hwmod,
647 .slave = &dm814x_timer2_hwmod,
648 .clk = "timer_sys_ck",
649 .user = OCP_USER_MPU,
652 static struct omap_hwmod dm816x_timer2_hwmod = {
654 .clkdm_name = "alwon_l3s_clkdm",
655 .main_clk = "timer2_fck",
658 .clkctrl_offs = DM816X_CM_ALWON_TIMER_2_CLKCTRL,
659 .modulemode = MODULEMODE_SWCTRL,
662 .dev_attr = &capability_alwon_dev_attr,
663 .class = &dm816x_timer_hwmod_class,
666 static struct omap_hwmod_ocp_if dm816x_l4_ls__timer2 = {
667 .master = &dm81xx_l4_ls_hwmod,
668 .slave = &dm816x_timer2_hwmod,
670 .user = OCP_USER_MPU,
673 static struct omap_hwmod dm816x_timer3_hwmod = {
675 .clkdm_name = "alwon_l3s_clkdm",
676 .main_clk = "timer3_fck",
679 .clkctrl_offs = DM816X_CM_ALWON_TIMER_3_CLKCTRL,
680 .modulemode = MODULEMODE_SWCTRL,
683 .dev_attr = &capability_alwon_dev_attr,
684 .class = &dm816x_timer_hwmod_class,
687 static struct omap_hwmod_ocp_if dm816x_l4_ls__timer3 = {
688 .master = &dm81xx_l4_ls_hwmod,
689 .slave = &dm816x_timer3_hwmod,
691 .user = OCP_USER_MPU,
694 static struct omap_hwmod dm816x_timer4_hwmod = {
696 .clkdm_name = "alwon_l3s_clkdm",
697 .main_clk = "timer4_fck",
700 .clkctrl_offs = DM816X_CM_ALWON_TIMER_4_CLKCTRL,
701 .modulemode = MODULEMODE_SWCTRL,
704 .dev_attr = &capability_alwon_dev_attr,
705 .class = &dm816x_timer_hwmod_class,
708 static struct omap_hwmod_ocp_if dm816x_l4_ls__timer4 = {
709 .master = &dm81xx_l4_ls_hwmod,
710 .slave = &dm816x_timer4_hwmod,
712 .user = OCP_USER_MPU,
715 static struct omap_hwmod dm816x_timer5_hwmod = {
717 .clkdm_name = "alwon_l3s_clkdm",
718 .main_clk = "timer5_fck",
721 .clkctrl_offs = DM816X_CM_ALWON_TIMER_5_CLKCTRL,
722 .modulemode = MODULEMODE_SWCTRL,
725 .dev_attr = &capability_alwon_dev_attr,
726 .class = &dm816x_timer_hwmod_class,
729 static struct omap_hwmod_ocp_if dm816x_l4_ls__timer5 = {
730 .master = &dm81xx_l4_ls_hwmod,
731 .slave = &dm816x_timer5_hwmod,
733 .user = OCP_USER_MPU,
736 static struct omap_hwmod dm816x_timer6_hwmod = {
738 .clkdm_name = "alwon_l3s_clkdm",
739 .main_clk = "timer6_fck",
742 .clkctrl_offs = DM816X_CM_ALWON_TIMER_6_CLKCTRL,
743 .modulemode = MODULEMODE_SWCTRL,
746 .dev_attr = &capability_alwon_dev_attr,
747 .class = &dm816x_timer_hwmod_class,
750 static struct omap_hwmod_ocp_if dm816x_l4_ls__timer6 = {
751 .master = &dm81xx_l4_ls_hwmod,
752 .slave = &dm816x_timer6_hwmod,
754 .user = OCP_USER_MPU,
757 static struct omap_hwmod dm816x_timer7_hwmod = {
759 .clkdm_name = "alwon_l3s_clkdm",
760 .main_clk = "timer7_fck",
763 .clkctrl_offs = DM816X_CM_ALWON_TIMER_7_CLKCTRL,
764 .modulemode = MODULEMODE_SWCTRL,
767 .dev_attr = &capability_alwon_dev_attr,
768 .class = &dm816x_timer_hwmod_class,
771 static struct omap_hwmod_ocp_if dm816x_l4_ls__timer7 = {
772 .master = &dm81xx_l4_ls_hwmod,
773 .slave = &dm816x_timer7_hwmod,
775 .user = OCP_USER_MPU,
779 static struct omap_hwmod_class_sysconfig dm814x_cpgmac_sysc = {
783 .sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
784 SYSS_HAS_RESET_STATUS,
785 .idlemodes = SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
787 .sysc_fields = &omap_hwmod_sysc_type3,
790 static struct omap_hwmod_class dm814x_cpgmac0_hwmod_class = {
792 .sysc = &dm814x_cpgmac_sysc,
795 static struct omap_hwmod dm814x_cpgmac0_hwmod = {
797 .class = &dm814x_cpgmac0_hwmod_class,
798 .clkdm_name = "alwon_ethernet_clkdm",
799 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
800 .main_clk = "cpsw_125mhz_gclk",
803 .clkctrl_offs = DM81XX_CM_ALWON_ETHERNET_0_CLKCTRL,
804 .modulemode = MODULEMODE_SWCTRL,
809 static struct omap_hwmod_class dm814x_mdio_hwmod_class = {
810 .name = "davinci_mdio",
813 static struct omap_hwmod dm814x_mdio_hwmod = {
814 .name = "davinci_mdio",
815 .class = &dm814x_mdio_hwmod_class,
816 .clkdm_name = "alwon_ethernet_clkdm",
817 .main_clk = "cpsw_125mhz_gclk",
820 static struct omap_hwmod_ocp_if dm814x_l4_hs__cpgmac0 = {
821 .master = &dm81xx_l4_hs_hwmod,
822 .slave = &dm814x_cpgmac0_hwmod,
823 .clk = "cpsw_125mhz_gclk",
824 .user = OCP_USER_MPU,
827 static struct omap_hwmod_ocp_if dm814x_cpgmac0__mdio = {
828 .master = &dm814x_cpgmac0_hwmod,
829 .slave = &dm814x_mdio_hwmod,
830 .user = OCP_USER_MPU,
831 .flags = HWMOD_NO_IDLEST,
835 static struct omap_hwmod_class_sysconfig dm816x_emac_sysc = {
838 .sysc_flags = SYSC_HAS_SOFTRESET,
839 .sysc_fields = &omap_hwmod_sysc_type2,
842 static struct omap_hwmod_class dm816x_emac_hwmod_class = {
844 .sysc = &dm816x_emac_sysc,
848 * On dm816x the MDIO is within EMAC0. As the MDIO driver is a separate
849 * driver probed before EMAC0, we let MDIO do the clock idling.
851 static struct omap_hwmod dm816x_emac0_hwmod = {
853 .clkdm_name = "alwon_ethernet_clkdm",
854 .class = &dm816x_emac_hwmod_class,
855 .flags = HWMOD_NO_IDLEST,
858 static struct omap_hwmod_ocp_if dm81xx_l4_hs__emac0 = {
859 .master = &dm81xx_l4_hs_hwmod,
860 .slave = &dm816x_emac0_hwmod,
862 .user = OCP_USER_MPU,
865 static struct omap_hwmod_class dm81xx_mdio_hwmod_class = {
866 .name = "davinci_mdio",
867 .sysc = &dm816x_emac_sysc,
870 static struct omap_hwmod dm81xx_emac0_mdio_hwmod = {
871 .name = "davinci_mdio",
872 .class = &dm81xx_mdio_hwmod_class,
873 .clkdm_name = "alwon_ethernet_clkdm",
874 .main_clk = "sysclk24_ck",
875 .flags = HWMOD_NO_IDLEST,
877 * REVISIT: This should be moved to the emac0_hwmod
878 * once we have a better way to handle device slaves.
882 .clkctrl_offs = DM81XX_CM_ALWON_ETHERNET_0_CLKCTRL,
883 .modulemode = MODULEMODE_SWCTRL,
888 static struct omap_hwmod_ocp_if dm81xx_emac0__mdio = {
889 .master = &dm81xx_l4_hs_hwmod,
890 .slave = &dm81xx_emac0_mdio_hwmod,
891 .user = OCP_USER_MPU,
894 static struct omap_hwmod dm816x_emac1_hwmod = {
896 .clkdm_name = "alwon_ethernet_clkdm",
897 .main_clk = "sysclk24_ck",
898 .flags = HWMOD_NO_IDLEST,
901 .clkctrl_offs = DM816X_CM_ALWON_ETHERNET_1_CLKCTRL,
902 .modulemode = MODULEMODE_SWCTRL,
905 .class = &dm816x_emac_hwmod_class,
908 static struct omap_hwmod_ocp_if dm816x_l4_hs__emac1 = {
909 .master = &dm81xx_l4_hs_hwmod,
910 .slave = &dm816x_emac1_hwmod,
912 .user = OCP_USER_MPU,
915 static struct omap_hwmod_class_sysconfig dm816x_mmc_sysc = {
919 .sysc_flags = SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
920 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
921 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS,
922 .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART,
923 .sysc_fields = &omap_hwmod_sysc_type1,
926 static struct omap_hwmod_class dm816x_mmc_class = {
928 .sysc = &dm816x_mmc_sysc,
931 static struct omap_hwmod_opt_clk dm816x_mmc1_opt_clks[] = {
932 { .role = "dbck", .clk = "sysclk18_ck", },
935 static struct omap_hsmmc_dev_attr mmc1_dev_attr = {
936 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
939 static struct omap_hwmod dm816x_mmc1_hwmod = {
941 .clkdm_name = "alwon_l3s_clkdm",
942 .opt_clks = dm816x_mmc1_opt_clks,
943 .opt_clks_cnt = ARRAY_SIZE(dm816x_mmc1_opt_clks),
944 .main_clk = "sysclk10_ck",
947 .clkctrl_offs = DM816X_CM_ALWON_SDIO_CLKCTRL,
948 .modulemode = MODULEMODE_SWCTRL,
951 .dev_attr = &mmc1_dev_attr,
952 .class = &dm816x_mmc_class,
955 static struct omap_hwmod_ocp_if dm816x_l4_ls__mmc1 = {
956 .master = &dm81xx_l4_ls_hwmod,
957 .slave = &dm816x_mmc1_hwmod,
959 .user = OCP_USER_MPU,
960 .flags = OMAP_FIREWALL_L4
963 static struct omap_hwmod_class_sysconfig dm816x_mcspi_sysc = {
967 .sysc_flags = SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
968 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
969 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS,
970 .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART,
971 .sysc_fields = &omap_hwmod_sysc_type1,
974 static struct omap_hwmod_class dm816x_mcspi_class = {
976 .sysc = &dm816x_mcspi_sysc,
977 .rev = OMAP3_MCSPI_REV,
980 static struct omap2_mcspi_dev_attr dm816x_mcspi1_dev_attr = {
984 static struct omap_hwmod dm81xx_mcspi1_hwmod = {
986 .clkdm_name = "alwon_l3s_clkdm",
987 .main_clk = "sysclk10_ck",
990 .clkctrl_offs = DM81XX_CM_ALWON_SPI_CLKCTRL,
991 .modulemode = MODULEMODE_SWCTRL,
994 .class = &dm816x_mcspi_class,
995 .dev_attr = &dm816x_mcspi1_dev_attr,
998 static struct omap_hwmod_ocp_if dm81xx_l4_ls__mcspi1 = {
999 .master = &dm81xx_l4_ls_hwmod,
1000 .slave = &dm81xx_mcspi1_hwmod,
1001 .clk = "sysclk6_ck",
1002 .user = OCP_USER_MPU,
1005 static struct omap_hwmod_class_sysconfig dm81xx_mailbox_sysc = {
1009 .sysc_flags = SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1010 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE,
1011 .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART,
1012 .sysc_fields = &omap_hwmod_sysc_type1,
1015 static struct omap_hwmod_class dm81xx_mailbox_hwmod_class = {
1017 .sysc = &dm81xx_mailbox_sysc,
1020 static struct omap_hwmod dm81xx_mailbox_hwmod = {
1022 .clkdm_name = "alwon_l3s_clkdm",
1023 .class = &dm81xx_mailbox_hwmod_class,
1024 .main_clk = "sysclk6_ck",
1027 .clkctrl_offs = DM81XX_CM_ALWON_MAILBOX_CLKCTRL,
1028 .modulemode = MODULEMODE_SWCTRL,
1033 static struct omap_hwmod_ocp_if dm81xx_l4_ls__mailbox = {
1034 .master = &dm81xx_l4_ls_hwmod,
1035 .slave = &dm81xx_mailbox_hwmod,
1036 .user = OCP_USER_MPU,
1039 static struct omap_hwmod_class dm81xx_tpcc_hwmod_class = {
1043 static struct omap_hwmod dm81xx_tpcc_hwmod = {
1045 .class = &dm81xx_tpcc_hwmod_class,
1046 .clkdm_name = "alwon_l3s_clkdm",
1047 .main_clk = "sysclk4_ck",
1050 .clkctrl_offs = DM81XX_CM_ALWON_TPCC_CLKCTRL,
1051 .modulemode = MODULEMODE_SWCTRL,
1056 static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tpcc = {
1057 .master = &dm81xx_alwon_l3_fast_hwmod,
1058 .slave = &dm81xx_tpcc_hwmod,
1059 .clk = "sysclk4_ck",
1060 .user = OCP_USER_MPU,
1063 static struct omap_hwmod_addr_space dm81xx_tptc0_addr_space[] = {
1065 .pa_start = 0x49800000,
1066 .pa_end = 0x49800000 + SZ_8K - 1,
1067 .flags = ADDR_TYPE_RT,
1072 static struct omap_hwmod_class dm81xx_tptc0_hwmod_class = {
1076 static struct omap_hwmod dm81xx_tptc0_hwmod = {
1078 .class = &dm81xx_tptc0_hwmod_class,
1079 .clkdm_name = "alwon_l3s_clkdm",
1080 .main_clk = "sysclk4_ck",
1083 .clkctrl_offs = DM81XX_CM_ALWON_TPTC0_CLKCTRL,
1084 .modulemode = MODULEMODE_SWCTRL,
1089 static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tptc0 = {
1090 .master = &dm81xx_alwon_l3_fast_hwmod,
1091 .slave = &dm81xx_tptc0_hwmod,
1092 .clk = "sysclk4_ck",
1093 .addr = dm81xx_tptc0_addr_space,
1094 .user = OCP_USER_MPU,
1097 static struct omap_hwmod_ocp_if dm81xx_tptc0__alwon_l3_fast = {
1098 .master = &dm81xx_tptc0_hwmod,
1099 .slave = &dm81xx_alwon_l3_fast_hwmod,
1100 .clk = "sysclk4_ck",
1101 .addr = dm81xx_tptc0_addr_space,
1102 .user = OCP_USER_MPU,
1105 static struct omap_hwmod_addr_space dm81xx_tptc1_addr_space[] = {
1107 .pa_start = 0x49900000,
1108 .pa_end = 0x49900000 + SZ_8K - 1,
1109 .flags = ADDR_TYPE_RT,
1114 static struct omap_hwmod_class dm81xx_tptc1_hwmod_class = {
1118 static struct omap_hwmod dm81xx_tptc1_hwmod = {
1120 .class = &dm81xx_tptc1_hwmod_class,
1121 .clkdm_name = "alwon_l3s_clkdm",
1122 .main_clk = "sysclk4_ck",
1125 .clkctrl_offs = DM81XX_CM_ALWON_TPTC1_CLKCTRL,
1126 .modulemode = MODULEMODE_SWCTRL,
1131 static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tptc1 = {
1132 .master = &dm81xx_alwon_l3_fast_hwmod,
1133 .slave = &dm81xx_tptc1_hwmod,
1134 .clk = "sysclk4_ck",
1135 .addr = dm81xx_tptc1_addr_space,
1136 .user = OCP_USER_MPU,
1139 static struct omap_hwmod_ocp_if dm81xx_tptc1__alwon_l3_fast = {
1140 .master = &dm81xx_tptc1_hwmod,
1141 .slave = &dm81xx_alwon_l3_fast_hwmod,
1142 .clk = "sysclk4_ck",
1143 .addr = dm81xx_tptc1_addr_space,
1144 .user = OCP_USER_MPU,
1147 static struct omap_hwmod_addr_space dm81xx_tptc2_addr_space[] = {
1149 .pa_start = 0x49a00000,
1150 .pa_end = 0x49a00000 + SZ_8K - 1,
1151 .flags = ADDR_TYPE_RT,
1156 static struct omap_hwmod_class dm81xx_tptc2_hwmod_class = {
1160 static struct omap_hwmod dm81xx_tptc2_hwmod = {
1162 .class = &dm81xx_tptc2_hwmod_class,
1163 .clkdm_name = "alwon_l3s_clkdm",
1164 .main_clk = "sysclk4_ck",
1167 .clkctrl_offs = DM81XX_CM_ALWON_TPTC2_CLKCTRL,
1168 .modulemode = MODULEMODE_SWCTRL,
1173 static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tptc2 = {
1174 .master = &dm81xx_alwon_l3_fast_hwmod,
1175 .slave = &dm81xx_tptc2_hwmod,
1176 .clk = "sysclk4_ck",
1177 .addr = dm81xx_tptc2_addr_space,
1178 .user = OCP_USER_MPU,
1181 static struct omap_hwmod_ocp_if dm81xx_tptc2__alwon_l3_fast = {
1182 .master = &dm81xx_tptc2_hwmod,
1183 .slave = &dm81xx_alwon_l3_fast_hwmod,
1184 .clk = "sysclk4_ck",
1185 .addr = dm81xx_tptc2_addr_space,
1186 .user = OCP_USER_MPU,
1189 static struct omap_hwmod_addr_space dm81xx_tptc3_addr_space[] = {
1191 .pa_start = 0x49b00000,
1192 .pa_end = 0x49b00000 + SZ_8K - 1,
1193 .flags = ADDR_TYPE_RT,
1198 static struct omap_hwmod_class dm81xx_tptc3_hwmod_class = {
1202 static struct omap_hwmod dm81xx_tptc3_hwmod = {
1204 .class = &dm81xx_tptc3_hwmod_class,
1205 .clkdm_name = "alwon_l3s_clkdm",
1206 .main_clk = "sysclk4_ck",
1209 .clkctrl_offs = DM81XX_CM_ALWON_TPTC3_CLKCTRL,
1210 .modulemode = MODULEMODE_SWCTRL,
1215 static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tptc3 = {
1216 .master = &dm81xx_alwon_l3_fast_hwmod,
1217 .slave = &dm81xx_tptc3_hwmod,
1218 .clk = "sysclk4_ck",
1219 .addr = dm81xx_tptc3_addr_space,
1220 .user = OCP_USER_MPU,
1223 static struct omap_hwmod_ocp_if dm81xx_tptc3__alwon_l3_fast = {
1224 .master = &dm81xx_tptc3_hwmod,
1225 .slave = &dm81xx_alwon_l3_fast_hwmod,
1226 .clk = "sysclk4_ck",
1227 .addr = dm81xx_tptc3_addr_space,
1228 .user = OCP_USER_MPU,
1232 * REVISIT: Test and enable the following once clocks work:
1233 * dm81xx_l4_ls__gpio1
1234 * dm81xx_l4_ls__gpio2
1235 * dm81xx_l4_ls__mailbox
1236 * dm81xx_alwon_l3_slow__gpmc
1237 * dm81xx_default_l3_slow__usbss
1239 * Also note that some devices share a single clkctrl_offs..
1240 * For example, i2c1 and 3 share one, and i2c2 and 4 share one.
1242 static struct omap_hwmod_ocp_if *dm814x_hwmod_ocp_ifs[] __initdata = {
1243 &dm814x_mpu__alwon_l3_slow,
1244 &dm814x_mpu__alwon_l3_med,
1245 &dm81xx_alwon_l3_slow__l4_ls,
1246 &dm81xx_alwon_l3_slow__l4_hs,
1247 &dm81xx_l4_ls__uart1,
1248 &dm81xx_l4_ls__uart2,
1249 &dm81xx_l4_ls__uart3,
1250 &dm81xx_l4_ls__wd_timer1,
1251 &dm81xx_l4_ls__i2c1,
1252 &dm81xx_l4_ls__i2c2,
1254 &dm81xx_l4_ls__mcspi1,
1255 &dm81xx_alwon_l3_fast__tpcc,
1256 &dm81xx_alwon_l3_fast__tptc0,
1257 &dm81xx_alwon_l3_fast__tptc1,
1258 &dm81xx_alwon_l3_fast__tptc2,
1259 &dm81xx_alwon_l3_fast__tptc3,
1260 &dm81xx_tptc0__alwon_l3_fast,
1261 &dm81xx_tptc1__alwon_l3_fast,
1262 &dm81xx_tptc2__alwon_l3_fast,
1263 &dm81xx_tptc3__alwon_l3_fast,
1264 &dm814x_l4_ls__timer1,
1265 &dm814x_l4_ls__timer2,
1266 &dm814x_l4_hs__cpgmac0,
1267 &dm814x_cpgmac0__mdio,
1271 int __init dm814x_hwmod_init(void)
1274 return omap_hwmod_register_links(dm814x_hwmod_ocp_ifs);
1277 static struct omap_hwmod_ocp_if *dm816x_hwmod_ocp_ifs[] __initdata = {
1278 &dm816x_mpu__alwon_l3_slow,
1279 &dm816x_mpu__alwon_l3_med,
1280 &dm81xx_alwon_l3_slow__l4_ls,
1281 &dm81xx_alwon_l3_slow__l4_hs,
1282 &dm81xx_l4_ls__uart1,
1283 &dm81xx_l4_ls__uart2,
1284 &dm81xx_l4_ls__uart3,
1285 &dm81xx_l4_ls__wd_timer1,
1286 &dm81xx_l4_ls__i2c1,
1287 &dm81xx_l4_ls__i2c2,
1288 &dm81xx_l4_ls__gpio1,
1289 &dm81xx_l4_ls__gpio2,
1291 &dm816x_l4_ls__mmc1,
1292 &dm816x_l4_ls__timer1,
1293 &dm816x_l4_ls__timer2,
1294 &dm816x_l4_ls__timer3,
1295 &dm816x_l4_ls__timer4,
1296 &dm816x_l4_ls__timer5,
1297 &dm816x_l4_ls__timer6,
1298 &dm816x_l4_ls__timer7,
1299 &dm81xx_l4_ls__mcspi1,
1300 &dm81xx_l4_ls__mailbox,
1301 &dm81xx_l4_hs__emac0,
1302 &dm81xx_emac0__mdio,
1303 &dm816x_l4_hs__emac1,
1304 &dm81xx_alwon_l3_fast__tpcc,
1305 &dm81xx_alwon_l3_fast__tptc0,
1306 &dm81xx_alwon_l3_fast__tptc1,
1307 &dm81xx_alwon_l3_fast__tptc2,
1308 &dm81xx_alwon_l3_fast__tptc3,
1309 &dm81xx_tptc0__alwon_l3_fast,
1310 &dm81xx_tptc1__alwon_l3_fast,
1311 &dm81xx_tptc2__alwon_l3_fast,
1312 &dm81xx_tptc3__alwon_l3_fast,
1313 &dm81xx_alwon_l3_slow__gpmc,
1314 &dm81xx_default_l3_slow__usbss,
1318 int __init dm816x_hwmod_init(void)
1321 return omap_hwmod_register_links(dm816x_hwmod_ocp_ifs);