1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2002 ARM Ltd.
5 * Copyright (c) 2010, Code Aurora Forum. All rights reserved.
6 * Copyright (c) 2014 The Linux Foundation. All rights reserved.
9 #include <linux/init.h>
10 #include <linux/errno.h>
11 #include <linux/delay.h>
12 #include <linux/device.h>
14 #include <linux/of_address.h>
15 #include <linux/smp.h>
17 #include <linux/qcom_scm.h>
19 #include <asm/smp_plat.h>
22 #define VDD_SC1_ARRAY_CLAMP_GFS_CTL 0x35a0
23 #define SCSS_CPU1CORE_RESET 0x2d80
24 #define SCSS_DBG_STATUS_CORE_PWRDUP 0x2e64
26 #define APCS_CPU_PWR_CTL 0x04
27 #define PLL_CLAMP BIT(8)
28 #define CORE_PWRD_UP BIT(7)
29 #define COREPOR_RST BIT(5)
30 #define CORE_RST BIT(4)
31 #define L2DT_SLP BIT(3)
34 #define APC_PWR_GATE_CTL 0x14
35 #define BHS_CNT_SHIFT 24
36 #define LDO_PWR_DWN_SHIFT 16
37 #define LDO_BYP_SHIFT 8
38 #define BHS_SEG_SHIFT 1
41 #define APCS_SAW2_VCTL 0x14
42 #define APCS_SAW2_2_VCTL 0x1c
44 extern void secondary_startup_arm(void);
46 #ifdef CONFIG_HOTPLUG_CPU
47 static void qcom_cpu_die(unsigned int cpu)
53 static int scss_release_secondary(unsigned int cpu)
55 struct device_node *node;
58 node = of_find_compatible_node(NULL, NULL, "qcom,gcc-msm8660");
60 pr_err("%s: can't find node\n", __func__);
64 base = of_iomap(node, 0);
69 writel_relaxed(0, base + VDD_SC1_ARRAY_CLAMP_GFS_CTL);
70 writel_relaxed(0, base + SCSS_CPU1CORE_RESET);
71 writel_relaxed(3, base + SCSS_DBG_STATUS_CORE_PWRDUP);
78 static int kpssv1_release_secondary(unsigned int cpu)
81 void __iomem *reg, *saw_reg;
82 struct device_node *cpu_node, *acc_node, *saw_node;
85 cpu_node = of_get_cpu_node(cpu, NULL);
89 acc_node = of_parse_phandle(cpu_node, "qcom,acc", 0);
95 saw_node = of_parse_phandle(cpu_node, "qcom,saw", 0);
101 reg = of_iomap(acc_node, 0);
107 saw_reg = of_iomap(saw_node, 0);
113 /* Turn on CPU rail */
114 writel_relaxed(0xA4, saw_reg + APCS_SAW2_VCTL);
118 /* Krait bring-up sequence */
119 val = PLL_CLAMP | L2DT_SLP | CLAMP;
120 writel_relaxed(val, reg + APCS_CPU_PWR_CTL);
122 writel_relaxed(val, reg + APCS_CPU_PWR_CTL);
127 writel_relaxed(val, reg + APCS_CPU_PWR_CTL);
132 writel_relaxed(val, reg + APCS_CPU_PWR_CTL);
137 writel_relaxed(val, reg + APCS_CPU_PWR_CTL);
142 writel_relaxed(val, reg + APCS_CPU_PWR_CTL);
149 of_node_put(saw_node);
151 of_node_put(acc_node);
153 of_node_put(cpu_node);
157 static int kpssv2_release_secondary(unsigned int cpu)
160 struct device_node *cpu_node, *l2_node, *acc_node, *saw_node;
161 void __iomem *l2_saw_base;
165 cpu_node = of_get_cpu_node(cpu, NULL);
169 acc_node = of_parse_phandle(cpu_node, "qcom,acc", 0);
175 l2_node = of_parse_phandle(cpu_node, "next-level-cache", 0);
181 saw_node = of_parse_phandle(l2_node, "qcom,saw", 0);
187 reg = of_iomap(acc_node, 0);
193 l2_saw_base = of_iomap(saw_node, 0);
199 /* Turn on the BHS, turn off LDO Bypass and power down LDO */
200 reg_val = (64 << BHS_CNT_SHIFT) | (0x3f << LDO_PWR_DWN_SHIFT) | BHS_EN;
201 writel_relaxed(reg_val, reg + APC_PWR_GATE_CTL);
203 /* wait for the BHS to settle */
206 /* Turn on BHS segments */
207 reg_val |= 0x3f << BHS_SEG_SHIFT;
208 writel_relaxed(reg_val, reg + APC_PWR_GATE_CTL);
210 /* wait for the BHS to settle */
213 /* Finally turn on the bypass so that BHS supplies power */
214 reg_val |= 0x3f << LDO_BYP_SHIFT;
215 writel_relaxed(reg_val, reg + APC_PWR_GATE_CTL);
217 /* enable max phases */
218 writel_relaxed(0x10003, l2_saw_base + APCS_SAW2_2_VCTL);
222 reg_val = COREPOR_RST | CLAMP;
223 writel_relaxed(reg_val, reg + APCS_CPU_PWR_CTL);
228 writel_relaxed(reg_val, reg + APCS_CPU_PWR_CTL);
232 reg_val &= ~COREPOR_RST;
233 writel_relaxed(reg_val, reg + APCS_CPU_PWR_CTL);
236 reg_val |= CORE_PWRD_UP;
237 writel_relaxed(reg_val, reg + APCS_CPU_PWR_CTL);
242 iounmap(l2_saw_base);
246 of_node_put(saw_node);
248 of_node_put(l2_node);
250 of_node_put(acc_node);
252 of_node_put(cpu_node);
257 static DEFINE_PER_CPU(int, cold_boot_done);
259 static int qcom_boot_secondary(unsigned int cpu, int (*func)(unsigned int))
263 if (!per_cpu(cold_boot_done, cpu)) {
266 per_cpu(cold_boot_done, cpu) = true;
270 * Send the secondary CPU a soft interrupt, thereby causing
271 * the boot monitor to read the system wide flags register,
272 * and branch to the address found there.
274 arch_send_wakeup_ipi_mask(cpumask_of(cpu));
279 static int msm8660_boot_secondary(unsigned int cpu, struct task_struct *idle)
281 return qcom_boot_secondary(cpu, scss_release_secondary);
284 static int kpssv1_boot_secondary(unsigned int cpu, struct task_struct *idle)
286 return qcom_boot_secondary(cpu, kpssv1_release_secondary);
289 static int kpssv2_boot_secondary(unsigned int cpu, struct task_struct *idle)
291 return qcom_boot_secondary(cpu, kpssv2_release_secondary);
294 static void __init qcom_smp_prepare_cpus(unsigned int max_cpus)
298 if (qcom_scm_set_cold_boot_addr(secondary_startup_arm,
300 for_each_present_cpu(cpu) {
301 if (cpu == smp_processor_id())
303 set_cpu_present(cpu, false);
305 pr_warn("Failed to set CPU boot address, disabling SMP\n");
309 static const struct smp_operations smp_msm8660_ops __initconst = {
310 .smp_prepare_cpus = qcom_smp_prepare_cpus,
311 .smp_boot_secondary = msm8660_boot_secondary,
312 #ifdef CONFIG_HOTPLUG_CPU
313 .cpu_die = qcom_cpu_die,
316 CPU_METHOD_OF_DECLARE(qcom_smp, "qcom,gcc-msm8660", &smp_msm8660_ops);
318 static const struct smp_operations qcom_smp_kpssv1_ops __initconst = {
319 .smp_prepare_cpus = qcom_smp_prepare_cpus,
320 .smp_boot_secondary = kpssv1_boot_secondary,
321 #ifdef CONFIG_HOTPLUG_CPU
322 .cpu_die = qcom_cpu_die,
325 CPU_METHOD_OF_DECLARE(qcom_smp_kpssv1, "qcom,kpss-acc-v1", &qcom_smp_kpssv1_ops);
327 static const struct smp_operations qcom_smp_kpssv2_ops __initconst = {
328 .smp_prepare_cpus = qcom_smp_prepare_cpus,
329 .smp_boot_secondary = kpssv2_boot_secondary,
330 #ifdef CONFIG_HOTPLUG_CPU
331 .cpu_die = qcom_cpu_die,
334 CPU_METHOD_OF_DECLARE(qcom_smp_kpssv2, "qcom,kpss-acc-v2", &qcom_smp_kpssv2_ops);