2 * linux/arch/arm/mach-rpc/dma.c
4 * Copyright (C) 1998 Russell King
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * DMA functions specific to RiscPC architecture
12 #include <linux/mman.h>
13 #include <linux/init.h>
14 #include <linux/interrupt.h>
15 #include <linux/dma-mapping.h>
22 #include <mach/hardware.h>
23 #include <linux/uaccess.h>
25 #include <asm/mach/dma.h>
26 #include <asm/hardware/iomd.h>
29 struct dma_struct dma;
31 unsigned long base; /* Controller base address */
32 int irq; /* Controller IRQ */
33 struct scatterlist cur_sg; /* Current controller buffer */
47 #define TRANSFER_SIZE 2
50 #define ENDA (IOMD_IO0ENDA - IOMD_IO0CURA)
51 #define CURB (IOMD_IO0CURB - IOMD_IO0CURA)
52 #define ENDB (IOMD_IO0ENDB - IOMD_IO0CURA)
53 #define CR (IOMD_IO0CR - IOMD_IO0CURA)
54 #define ST (IOMD_IO0ST - IOMD_IO0CURA)
56 static void iomd_get_next_sg(struct scatterlist *sg, struct iomd_dma *idma)
58 unsigned long end, offset, flags = 0;
61 sg->dma_address = idma->dma_addr;
62 offset = sg->dma_address & ~PAGE_MASK;
64 end = offset + idma->dma_len;
69 if (offset + TRANSFER_SIZE >= end)
72 sg->length = end - TRANSFER_SIZE;
74 idma->dma_len -= end - offset;
75 idma->dma_addr += end - offset;
77 if (idma->dma_len == 0) {
78 if (idma->dma.sgcount > 1) {
79 idma->dma.sg = sg_next(idma->dma.sg);
80 idma->dma_addr = idma->dma.sg->dma_address;
81 idma->dma_len = idma->dma.sg->length;
89 flags = DMA_END_S | DMA_END_L;
97 static irqreturn_t iomd_dma_handle(int irq, void *dev_id)
99 struct iomd_dma *idma = dev_id;
100 unsigned long base = idma->base;
105 status = iomd_readb(base + ST);
106 if (!(status & DMA_ST_INT))
109 if ((idma->state ^ status) & DMA_ST_AB)
110 iomd_get_next_sg(&idma->cur_sg, idma);
112 switch (status & (DMA_ST_OFL | DMA_ST_AB)) {
113 case DMA_ST_OFL: /* OIA */
114 case DMA_ST_AB: /* .IB */
115 iomd_writel(idma->cur_sg.dma_address, base + CURA);
116 iomd_writel(idma->cur_sg.length, base + ENDA);
117 idma->state = DMA_ST_AB;
120 case DMA_ST_OFL | DMA_ST_AB: /* OIB */
122 iomd_writel(idma->cur_sg.dma_address, base + CURB);
123 iomd_writel(idma->cur_sg.length, base + ENDB);
128 if (status & DMA_ST_OFL &&
129 idma->cur_sg.length == (DMA_END_S|DMA_END_L))
133 idma->state = ~DMA_ST_AB;
139 static int iomd_request_dma(unsigned int chan, dma_t *dma)
141 struct iomd_dma *idma = container_of(dma, struct iomd_dma, dma);
143 return request_irq(idma->irq, iomd_dma_handle,
144 0, idma->dma.device_id, idma);
147 static void iomd_free_dma(unsigned int chan, dma_t *dma)
149 struct iomd_dma *idma = container_of(dma, struct iomd_dma, dma);
151 free_irq(idma->irq, idma);
154 static struct device isa_dma_dev = {
155 .init_name = "fallback device",
156 .coherent_dma_mask = ~(dma_addr_t)0,
157 .dma_mask = &isa_dma_dev.coherent_dma_mask,
160 static void iomd_enable_dma(unsigned int chan, dma_t *dma)
162 struct iomd_dma *idma = container_of(dma, struct iomd_dma, dma);
163 unsigned long dma_base = idma->base;
164 unsigned int ctrl = TRANSFER_SIZE | DMA_CR_E;
166 if (idma->dma.invalid) {
167 idma->dma.invalid = 0;
170 * Cope with ISA-style drivers which expect cache
174 idma->dma.sg = &idma->dma.buf;
175 idma->dma.sgcount = 1;
176 idma->dma.buf.length = idma->dma.count;
177 idma->dma.buf.dma_address = dma_map_single(&isa_dma_dev,
178 idma->dma.addr, idma->dma.count,
179 idma->dma.dma_mode == DMA_MODE_READ ?
180 DMA_FROM_DEVICE : DMA_TO_DEVICE);
183 iomd_writeb(DMA_CR_C, dma_base + CR);
184 idma->state = DMA_ST_AB;
187 if (idma->dma.dma_mode == DMA_MODE_READ)
190 iomd_writeb(ctrl, dma_base + CR);
191 enable_irq(idma->irq);
194 static void iomd_disable_dma(unsigned int chan, dma_t *dma)
196 struct iomd_dma *idma = container_of(dma, struct iomd_dma, dma);
197 unsigned long dma_base = idma->base;
200 local_irq_save(flags);
201 if (idma->state != ~DMA_ST_AB)
202 disable_irq(idma->irq);
203 iomd_writeb(0, dma_base + CR);
204 local_irq_restore(flags);
207 static int iomd_set_dma_speed(unsigned int chan, dma_t *dma, int cycle)
213 else if (cycle <= 250)
215 else if (cycle < 438)
220 tcr = iomd_readb(IOMD_DMATCR);
225 tcr = (tcr & ~0x03) | speed;
229 tcr = (tcr & ~0x0c) | (speed << 2);
233 tcr = (tcr & ~0x30) | (speed << 4);
237 tcr = (tcr & ~0xc0) | (speed << 6);
244 iomd_writeb(tcr, IOMD_DMATCR);
249 static struct dma_ops iomd_dma_ops = {
251 .request = iomd_request_dma,
252 .free = iomd_free_dma,
253 .enable = iomd_enable_dma,
254 .disable = iomd_disable_dma,
255 .setspeed = iomd_set_dma_speed,
258 static struct fiq_handler fh = {
263 struct dma_struct dma;
267 static void floppy_enable_dma(unsigned int chan, dma_t *dma)
269 struct floppy_dma *fdma = container_of(dma, struct floppy_dma, dma);
270 void *fiqhandler_start;
271 unsigned int fiqhandler_length;
277 if (fdma->dma.dma_mode == DMA_MODE_READ) {
278 extern unsigned char floppy_fiqin_start, floppy_fiqin_end;
279 fiqhandler_start = &floppy_fiqin_start;
280 fiqhandler_length = &floppy_fiqin_end - &floppy_fiqin_start;
282 extern unsigned char floppy_fiqout_start, floppy_fiqout_end;
283 fiqhandler_start = &floppy_fiqout_start;
284 fiqhandler_length = &floppy_fiqout_end - &floppy_fiqout_start;
287 regs.ARM_r9 = fdma->dma.count;
288 regs.ARM_r10 = (unsigned long)fdma->dma.addr;
289 regs.ARM_fp = (unsigned long)FLOPPYDMA_BASE;
291 if (claim_fiq(&fh)) {
292 printk("floppydma: couldn't claim FIQ.\n");
296 set_fiq_handler(fiqhandler_start, fiqhandler_length);
298 enable_fiq(fdma->fiq);
301 static void floppy_disable_dma(unsigned int chan, dma_t *dma)
303 struct floppy_dma *fdma = container_of(dma, struct floppy_dma, dma);
304 disable_fiq(fdma->fiq);
308 static int floppy_get_residue(unsigned int chan, dma_t *dma)
315 static struct dma_ops floppy_dma_ops = {
317 .enable = floppy_enable_dma,
318 .disable = floppy_disable_dma,
319 .residue = floppy_get_residue,
323 * This is virtual DMA - we don't need anything here.
325 static void sound_enable_disable_dma(unsigned int chan, dma_t *dma)
329 static struct dma_ops sound_dma_ops = {
331 .enable = sound_enable_disable_dma,
332 .disable = sound_enable_disable_dma,
335 static struct iomd_dma iomd_dma[6];
337 static struct floppy_dma floppy_dma = {
339 .d_ops = &floppy_dma_ops,
341 .fiq = FIQ_FLOPPYDATA,
344 static dma_t sound_dma = {
345 .d_ops = &sound_dma_ops,
348 static int __init rpc_dma_init(void)
353 iomd_writeb(0, IOMD_IO0CR);
354 iomd_writeb(0, IOMD_IO1CR);
355 iomd_writeb(0, IOMD_IO2CR);
356 iomd_writeb(0, IOMD_IO3CR);
358 iomd_writeb(0xa0, IOMD_DMATCR);
361 * Setup DMA channels 2,3 to be for podules
362 * and channels 0,1 for internal devices
364 iomd_writeb(DMA_EXT_IO3|DMA_EXT_IO2, IOMD_DMAEXT);
366 iomd_dma[DMA_0].base = IOMD_IO0CURA;
367 iomd_dma[DMA_0].irq = IRQ_DMA0;
368 iomd_dma[DMA_1].base = IOMD_IO1CURA;
369 iomd_dma[DMA_1].irq = IRQ_DMA1;
370 iomd_dma[DMA_2].base = IOMD_IO2CURA;
371 iomd_dma[DMA_2].irq = IRQ_DMA2;
372 iomd_dma[DMA_3].base = IOMD_IO3CURA;
373 iomd_dma[DMA_3].irq = IRQ_DMA3;
374 iomd_dma[DMA_S0].base = IOMD_SD0CURA;
375 iomd_dma[DMA_S0].irq = IRQ_DMAS0;
376 iomd_dma[DMA_S1].base = IOMD_SD1CURA;
377 iomd_dma[DMA_S1].irq = IRQ_DMAS1;
379 for (i = DMA_0; i <= DMA_S1; i++) {
380 iomd_dma[i].dma.d_ops = &iomd_dma_ops;
382 ret = isa_dma_add(i, &iomd_dma[i].dma);
384 printk("IOMDDMA%u: unable to register: %d\n", i, ret);
387 ret = isa_dma_add(DMA_VIRTUAL_FLOPPY, &floppy_dma.dma);
389 printk("IOMDFLOPPY: unable to register: %d\n", ret);
390 ret = isa_dma_add(DMA_VIRTUAL_SOUND, &sound_dma);
392 printk("IOMDSOUND: unable to register: %d\n", ret);
395 core_initcall(rpc_dma_init);