arch/arm/mach-sti/platsmp.c

   1 /*
   2  *  arch/arm/mach-sti/platsmp.c
   3  *
   4  * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
   5  *              http://www.st.com
   6  *
   7  * Cloned from linux/arch/arm/mach-vexpress/platsmp.c
   8  *
   9  *  Copyright (C) 2002 ARM Ltd.
  10  *  All Rights Reserved
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License version 2 as
  14  * published by the Free Software Foundation.
  15  */
  16 #include <linux/init.h>
  17 #include <linux/errno.h>
  18 #include <linux/delay.h>
  19 #include <linux/smp.h>
  20 #include <linux/io.h>
  21 #include <linux/of.h>
  22 #include <linux/of_address.h>
  23 #include <linux/memblock.h>
  24
  25 #include <asm/cacheflush.h>
  26 #include <asm/smp_plat.h>
  27 #include <asm/smp_scu.h>
  28
  29 #include "smp.h"
  30
  31 static u32 __iomem *cpu_strt_ptr;
  32
  33 static int sti_boot_secondary(unsigned int cpu, struct task_struct *idle)
  34 {
  35         unsigned long entry_pa = __pa_symbol(secondary_startup);
  36
  37         /*
  38          * Secondary CPU is initialised and started by a U-BOOTROM firmware.
  39          * Secondary CPU is spinning and waiting for a write at cpu_strt_ptr.
  40          * Writing secondary_startup address at cpu_strt_ptr makes it to
  41          * jump directly to secondary_startup().
  42          */
  43         __raw_writel(entry_pa, cpu_strt_ptr);
  44
  45         /* wmb so that data is actually written before cache flush is done */
  46         smp_wmb();
  47         sync_cache_w(cpu_strt_ptr);
  48
  49         return 0;
  50 }
  51
  52 static void __init sti_smp_prepare_cpus(unsigned int max_cpus)
  53 {
  54         struct device_node *np;
  55         void __iomem *scu_base;
  56         u32 release_phys;
  57         int cpu;
  58
  59         np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu");
  60
  61         if (np) {
  62                 scu_base = of_iomap(np, 0);
  63                 scu_enable(scu_base);
  64                 of_node_put(np);
  65         }
  66
  67         if (max_cpus <= 1)
  68                 return;
  69
  70         for_each_possible_cpu(cpu) {
  71
  72                 np = of_get_cpu_node(cpu, NULL);
  73
  74                 if (!np)
  75                         continue;
  76
  77                 if (of_property_read_u32(np, "cpu-release-addr",
  78                                                 &release_phys)) {
  79                         pr_err("CPU %d: missing or invalid cpu-release-addr "
  80                                 "property\n", cpu);
  81                         continue;
  82                 }
  83
  84                 /*
  85                  * cpu-release-addr is usually configured in SBC DMEM but can
  86                  * also be in RAM.
  87                  */
  88
  89                 if (!memblock_is_memory(release_phys))
  90                         cpu_strt_ptr =
  91                                 ioremap(release_phys, sizeof(release_phys));
  92                 else
  93                         cpu_strt_ptr =
  94                                 (u32 __iomem *)phys_to_virt(release_phys);
  95
  96                 set_cpu_possible(cpu, true);
  97         }
  98 }
  99
 100 const struct smp_operations sti_smp_ops __initconst = {
 101         .smp_prepare_cpus       = sti_smp_prepare_cpus,
 102         .smp_boot_secondary     = sti_boot_secondary,
 103 };