2 * arch/arm/mach-tegra/sleep.S
4 * Copyright (c) 2010-2011, NVIDIA Corporation.
5 * Copyright (c) 2011, Google, Inc.
7 * Author: Colin Cross <ccross@android.com>
8 * Gary King <gking@nvidia.com>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful, but WITHOUT
16 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
20 * You should have received a copy of the GNU General Public License along
21 * with this program; if not, write to the Free Software Foundation, Inc.,
22 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
25 #include <linux/linkage.h>
27 #include <asm/assembler.h>
28 #include <asm/cache.h>
30 #include <asm/hardware/cache-l2x0.h>
35 #define CLK_RESET_CCLK_BURST 0x20
36 #define CLK_RESET_CCLK_DIVIDER 0x24
38 #if defined(CONFIG_HOTPLUG_CPU) || defined(CONFIG_PM_SLEEP)
40 * tegra_disable_clean_inv_dcache
42 * disable, clean & invalidate the D-cache
44 * Corrupted registers: r1-r3, r6, r8, r9-r11
46 ENTRY(tegra_disable_clean_inv_dcache)
47 stmfd sp!, {r0, r4-r5, r7, r9-r11, lr}
50 /* Disable the D-cache */
51 mrc p15, 0, r2, c1, c0, 0
52 tst r2, #CR_C @ see tegra_sleep_cpu()
54 mcrne p15, 0, r2, c1, c0, 0
57 /* Flush the D-cache */
58 cmp r0, #TEGRA_FLUSH_CACHE_ALL
59 blne v7_flush_dcache_louis
60 bleq v7_flush_dcache_all
62 /* Trun off coherency */
65 ldmfd sp!, {r0, r4-r5, r7, r9-r11, pc}
66 ENDPROC(tegra_disable_clean_inv_dcache)
69 #ifdef CONFIG_PM_SLEEP
71 * tegra_init_l2_for_a15
73 * set up the correct L2 cache data RAM latency
75 ENTRY(tegra_init_l2_for_a15)
76 mrc p15, 0, r0, c0, c0, 5
78 tst r0, #1 @ only need for cluster 0
81 mrc p15, 0x1, r0, c9, c0, 2
86 mcrne p15, 0x1, r0, c9, c0, 2
90 ENDPROC(tegra_init_l2_for_a15)
93 * tegra_sleep_cpu_finish(unsigned long v2p)
95 * enters suspend in LP2 by turning off the mmu and jumping to
96 * tegra?_tear_down_cpu
98 ENTRY(tegra_sleep_cpu_finish)
100 /* Flush and disable the L1 data cache */
101 mov r0, #TEGRA_FLUSH_CACHE_ALL
102 bl tegra_disable_clean_inv_dcache
105 mov32 r6, tegra_tear_down_cpu
109 mov32 r3, tegra_shut_off_mmu
114 ENDPROC(tegra_sleep_cpu_finish)
119 * r0 = physical address to jump to with mmu off
121 * called with VA=PA mapping
122 * turns off MMU, icache, dcache and branch prediction
124 .align L1_CACHE_SHIFT
125 .pushsection .idmap.text, "ax"
126 ENTRY(tegra_shut_off_mmu)
127 mrc p15, 0, r3, c1, c0, 0
128 movw r2, #CR_I | CR_Z | CR_C | CR_M
131 mcr p15, 0, r3, c1, c0, 0
133 #ifdef CONFIG_CACHE_L2X0
134 /* Disable L2 cache */
135 check_cpu_part_num 0xc09, r9, r10
138 mov32 r2, TEGRA_ARM_PERIF_BASE + 0x3000
139 ldr r3, [r2, #L2X0_CTRL]
140 tst r3, #L2X0_CTRL_EN @ see tegra_sleep_cpu()
142 strne r3, [r2, #L2X0_CTRL]
145 ENDPROC(tegra_shut_off_mmu)
149 * tegra_switch_cpu_to_pllp
151 * In LP2 the normal cpu clock pllx will be turned off. Switch the CPU to pllp
153 ENTRY(tegra_switch_cpu_to_pllp)
154 /* in LP2 idle (SDRAM active), set the CPU burst policy to PLLP */
155 mov32 r5, TEGRA_CLK_RESET_BASE
156 mov r0, #(2 << 28) @ burst policy = run mode
157 orr r0, r0, #(4 << 4) @ use PLLP in run mode burst
158 str r0, [r5, #CLK_RESET_CCLK_BURST]
160 str r0, [r5, #CLK_RESET_CCLK_DIVIDER]
162 ENDPROC(tegra_switch_cpu_to_pllp)