1 /* linux/arch/arm/plat-samsung/devs.c
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
6 * Base SAMSUNG platform device definitions
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/kernel.h>
14 #include <linux/types.h>
15 #include <linux/interrupt.h>
16 #include <linux/list.h>
17 #include <linux/timer.h>
18 #include <linux/init.h>
19 #include <linux/serial_core.h>
20 #include <linux/platform_device.h>
22 #include <linux/slab.h>
23 #include <linux/string.h>
24 #include <linux/dma-mapping.h>
26 #include <linux/gfp.h>
27 #include <linux/mtd/mtd.h>
28 #include <linux/mtd/onenand.h>
29 #include <linux/mtd/partitions.h>
30 #include <linux/mmc/host.h>
31 #include <linux/ioport.h>
32 #include <linux/platform_data/s3c-hsudc.h>
36 #include <asm/mach/arch.h>
37 #include <asm/mach/map.h>
38 #include <asm/mach/irq.h>
40 #include <mach/hardware.h>
42 #include <mach/irqs.h>
46 #include <plat/devs.h>
49 #include <plat/ehci.h>
51 #include <plat/fb-s3c2410.h>
52 #include <plat/hwmon.h>
54 #include <plat/keypad.h>
56 #include <plat/nand.h>
57 #include <plat/sdhci.h>
60 #include <plat/udc-hs.h>
61 #include <plat/usb-control.h>
62 #include <plat/usb-phy.h>
63 #include <plat/regs-iic.h>
64 #include <plat/regs-serial.h>
65 #include <plat/regs-spi.h>
66 #include <plat/s3c64xx-spi.h>
68 static u64 samsung_device_dma_mask = DMA_BIT_MASK(32);
71 #ifdef CONFIG_CPU_S3C2440
72 static struct resource s3c_ac97_resource[] = {
73 [0] = DEFINE_RES_MEM(S3C2440_PA_AC97, S3C2440_SZ_AC97),
74 [1] = DEFINE_RES_IRQ(IRQ_S3C244X_AC97),
75 [2] = DEFINE_RES_DMA_NAMED(DMACH_PCM_OUT, "PCM out"),
76 [3] = DEFINE_RES_DMA_NAMED(DMACH_PCM_IN, "PCM in"),
77 [4] = DEFINE_RES_DMA_NAMED(DMACH_MIC_IN, "Mic in"),
80 struct platform_device s3c_device_ac97 = {
81 .name = "samsung-ac97",
83 .num_resources = ARRAY_SIZE(s3c_ac97_resource),
84 .resource = s3c_ac97_resource,
86 .dma_mask = &samsung_device_dma_mask,
87 .coherent_dma_mask = DMA_BIT_MASK(32),
90 #endif /* CONFIG_CPU_S3C2440 */
94 #ifdef CONFIG_PLAT_S3C24XX
95 static struct resource s3c_adc_resource[] = {
96 [0] = DEFINE_RES_MEM(S3C24XX_PA_ADC, S3C24XX_SZ_ADC),
97 [1] = DEFINE_RES_IRQ(IRQ_TC),
98 [2] = DEFINE_RES_IRQ(IRQ_ADC),
101 struct platform_device s3c_device_adc = {
102 .name = "s3c24xx-adc",
104 .num_resources = ARRAY_SIZE(s3c_adc_resource),
105 .resource = s3c_adc_resource,
107 #endif /* CONFIG_PLAT_S3C24XX */
109 #if defined(CONFIG_SAMSUNG_DEV_ADC)
110 static struct resource s3c_adc_resource[] = {
111 [0] = DEFINE_RES_MEM(SAMSUNG_PA_ADC, SZ_256),
112 [1] = DEFINE_RES_IRQ(IRQ_TC),
113 [2] = DEFINE_RES_IRQ(IRQ_ADC),
116 struct platform_device s3c_device_adc = {
117 .name = "samsung-adc",
119 .num_resources = ARRAY_SIZE(s3c_adc_resource),
120 .resource = s3c_adc_resource,
122 #endif /* CONFIG_SAMSUNG_DEV_ADC */
124 /* Camif Controller */
126 #ifdef CONFIG_CPU_S3C2440
127 static struct resource s3c_camif_resource[] = {
128 [0] = DEFINE_RES_MEM(S3C2440_PA_CAMIF, S3C2440_SZ_CAMIF),
129 [1] = DEFINE_RES_IRQ(IRQ_CAM),
132 struct platform_device s3c_device_camif = {
133 .name = "s3c2440-camif",
135 .num_resources = ARRAY_SIZE(s3c_camif_resource),
136 .resource = s3c_camif_resource,
138 .dma_mask = &samsung_device_dma_mask,
139 .coherent_dma_mask = DMA_BIT_MASK(32),
142 #endif /* CONFIG_CPU_S3C2440 */
146 struct platform_device samsung_asoc_dma = {
147 .name = "samsung-audio",
150 .dma_mask = &samsung_device_dma_mask,
151 .coherent_dma_mask = DMA_BIT_MASK(32),
155 struct platform_device samsung_asoc_idma = {
156 .name = "samsung-idma",
159 .dma_mask = &samsung_device_dma_mask,
160 .coherent_dma_mask = DMA_BIT_MASK(32),
166 #ifdef CONFIG_S3C_DEV_FB
167 static struct resource s3c_fb_resource[] = {
168 [0] = DEFINE_RES_MEM(S3C_PA_FB, SZ_16K),
169 [1] = DEFINE_RES_IRQ(IRQ_LCD_VSYNC),
170 [2] = DEFINE_RES_IRQ(IRQ_LCD_FIFO),
171 [3] = DEFINE_RES_IRQ(IRQ_LCD_SYSTEM),
174 struct platform_device s3c_device_fb = {
177 .num_resources = ARRAY_SIZE(s3c_fb_resource),
178 .resource = s3c_fb_resource,
180 .dma_mask = &samsung_device_dma_mask,
181 .coherent_dma_mask = DMA_BIT_MASK(32),
185 void __init s3c_fb_set_platdata(struct s3c_fb_platdata *pd)
187 s3c_set_platdata(pd, sizeof(struct s3c_fb_platdata),
190 #endif /* CONFIG_S3C_DEV_FB */
194 #ifdef CONFIG_S5P_DEV_FIMC0
195 static struct resource s5p_fimc0_resource[] = {
196 [0] = DEFINE_RES_MEM(S5P_PA_FIMC0, SZ_4K),
197 [1] = DEFINE_RES_IRQ(IRQ_FIMC0),
200 struct platform_device s5p_device_fimc0 = {
203 .num_resources = ARRAY_SIZE(s5p_fimc0_resource),
204 .resource = s5p_fimc0_resource,
206 .dma_mask = &samsung_device_dma_mask,
207 .coherent_dma_mask = DMA_BIT_MASK(32),
211 struct platform_device s5p_device_fimc_md = {
212 .name = "s5p-fimc-md",
215 #endif /* CONFIG_S5P_DEV_FIMC0 */
217 #ifdef CONFIG_S5P_DEV_FIMC1
218 static struct resource s5p_fimc1_resource[] = {
219 [0] = DEFINE_RES_MEM(S5P_PA_FIMC1, SZ_4K),
220 [1] = DEFINE_RES_IRQ(IRQ_FIMC1),
223 struct platform_device s5p_device_fimc1 = {
226 .num_resources = ARRAY_SIZE(s5p_fimc1_resource),
227 .resource = s5p_fimc1_resource,
229 .dma_mask = &samsung_device_dma_mask,
230 .coherent_dma_mask = DMA_BIT_MASK(32),
233 #endif /* CONFIG_S5P_DEV_FIMC1 */
235 #ifdef CONFIG_S5P_DEV_FIMC2
236 static struct resource s5p_fimc2_resource[] = {
237 [0] = DEFINE_RES_MEM(S5P_PA_FIMC2, SZ_4K),
238 [1] = DEFINE_RES_IRQ(IRQ_FIMC2),
241 struct platform_device s5p_device_fimc2 = {
244 .num_resources = ARRAY_SIZE(s5p_fimc2_resource),
245 .resource = s5p_fimc2_resource,
247 .dma_mask = &samsung_device_dma_mask,
248 .coherent_dma_mask = DMA_BIT_MASK(32),
251 #endif /* CONFIG_S5P_DEV_FIMC2 */
253 #ifdef CONFIG_S5P_DEV_FIMC3
254 static struct resource s5p_fimc3_resource[] = {
255 [0] = DEFINE_RES_MEM(S5P_PA_FIMC3, SZ_4K),
256 [1] = DEFINE_RES_IRQ(IRQ_FIMC3),
259 struct platform_device s5p_device_fimc3 = {
262 .num_resources = ARRAY_SIZE(s5p_fimc3_resource),
263 .resource = s5p_fimc3_resource,
265 .dma_mask = &samsung_device_dma_mask,
266 .coherent_dma_mask = DMA_BIT_MASK(32),
269 #endif /* CONFIG_S5P_DEV_FIMC3 */
273 #ifdef CONFIG_S5P_DEV_G2D
274 static struct resource s5p_g2d_resource[] = {
277 .end = S5P_PA_G2D + SZ_4K - 1,
278 .flags = IORESOURCE_MEM,
283 .flags = IORESOURCE_IRQ,
287 struct platform_device s5p_device_g2d = {
290 .num_resources = ARRAY_SIZE(s5p_g2d_resource),
291 .resource = s5p_g2d_resource,
293 .dma_mask = &samsung_device_dma_mask,
294 .coherent_dma_mask = DMA_BIT_MASK(32),
297 #endif /* CONFIG_S5P_DEV_G2D */
299 #ifdef CONFIG_S5P_DEV_JPEG
300 static struct resource s5p_jpeg_resource[] = {
301 [0] = DEFINE_RES_MEM(S5P_PA_JPEG, SZ_4K),
302 [1] = DEFINE_RES_IRQ(IRQ_JPEG),
305 struct platform_device s5p_device_jpeg = {
308 .num_resources = ARRAY_SIZE(s5p_jpeg_resource),
309 .resource = s5p_jpeg_resource,
311 .dma_mask = &samsung_device_dma_mask,
312 .coherent_dma_mask = DMA_BIT_MASK(32),
315 #endif /* CONFIG_S5P_DEV_JPEG */
319 #ifdef CONFIG_S5P_DEV_FIMD0
320 static struct resource s5p_fimd0_resource[] = {
321 [0] = DEFINE_RES_MEM(S5P_PA_FIMD0, SZ_32K),
322 [1] = DEFINE_RES_IRQ(IRQ_FIMD0_VSYNC),
323 [2] = DEFINE_RES_IRQ(IRQ_FIMD0_FIFO),
324 [3] = DEFINE_RES_IRQ(IRQ_FIMD0_SYSTEM),
327 struct platform_device s5p_device_fimd0 = {
330 .num_resources = ARRAY_SIZE(s5p_fimd0_resource),
331 .resource = s5p_fimd0_resource,
333 .dma_mask = &samsung_device_dma_mask,
334 .coherent_dma_mask = DMA_BIT_MASK(32),
338 void __init s5p_fimd0_set_platdata(struct s3c_fb_platdata *pd)
340 s3c_set_platdata(pd, sizeof(struct s3c_fb_platdata),
343 #endif /* CONFIG_S5P_DEV_FIMD0 */
347 #ifdef CONFIG_S3C_DEV_HWMON
348 struct platform_device s3c_device_hwmon = {
351 .dev.parent = &s3c_device_adc.dev,
354 void __init s3c_hwmon_set_platdata(struct s3c_hwmon_pdata *pd)
356 s3c_set_platdata(pd, sizeof(struct s3c_hwmon_pdata),
359 #endif /* CONFIG_S3C_DEV_HWMON */
363 #ifdef CONFIG_S3C_DEV_HSMMC
364 static struct resource s3c_hsmmc_resource[] = {
365 [0] = DEFINE_RES_MEM(S3C_PA_HSMMC0, SZ_4K),
366 [1] = DEFINE_RES_IRQ(IRQ_HSMMC0),
369 struct s3c_sdhci_platdata s3c_hsmmc0_def_platdata = {
371 .host_caps = (MMC_CAP_4_BIT_DATA |
372 MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
373 .clk_type = S3C_SDHCI_CLK_DIV_INTERNAL,
376 struct platform_device s3c_device_hsmmc0 = {
379 .num_resources = ARRAY_SIZE(s3c_hsmmc_resource),
380 .resource = s3c_hsmmc_resource,
382 .dma_mask = &samsung_device_dma_mask,
383 .coherent_dma_mask = DMA_BIT_MASK(32),
384 .platform_data = &s3c_hsmmc0_def_platdata,
388 void s3c_sdhci0_set_platdata(struct s3c_sdhci_platdata *pd)
390 s3c_sdhci_set_platdata(pd, &s3c_hsmmc0_def_platdata);
392 #endif /* CONFIG_S3C_DEV_HSMMC */
394 #ifdef CONFIG_S3C_DEV_HSMMC1
395 static struct resource s3c_hsmmc1_resource[] = {
396 [0] = DEFINE_RES_MEM(S3C_PA_HSMMC1, SZ_4K),
397 [1] = DEFINE_RES_IRQ(IRQ_HSMMC1),
400 struct s3c_sdhci_platdata s3c_hsmmc1_def_platdata = {
402 .host_caps = (MMC_CAP_4_BIT_DATA |
403 MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
404 .clk_type = S3C_SDHCI_CLK_DIV_INTERNAL,
407 struct platform_device s3c_device_hsmmc1 = {
410 .num_resources = ARRAY_SIZE(s3c_hsmmc1_resource),
411 .resource = s3c_hsmmc1_resource,
413 .dma_mask = &samsung_device_dma_mask,
414 .coherent_dma_mask = DMA_BIT_MASK(32),
415 .platform_data = &s3c_hsmmc1_def_platdata,
419 void s3c_sdhci1_set_platdata(struct s3c_sdhci_platdata *pd)
421 s3c_sdhci_set_platdata(pd, &s3c_hsmmc1_def_platdata);
423 #endif /* CONFIG_S3C_DEV_HSMMC1 */
427 #ifdef CONFIG_S3C_DEV_HSMMC2
428 static struct resource s3c_hsmmc2_resource[] = {
429 [0] = DEFINE_RES_MEM(S3C_PA_HSMMC2, SZ_4K),
430 [1] = DEFINE_RES_IRQ(IRQ_HSMMC2),
433 struct s3c_sdhci_platdata s3c_hsmmc2_def_platdata = {
435 .host_caps = (MMC_CAP_4_BIT_DATA |
436 MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
437 .clk_type = S3C_SDHCI_CLK_DIV_INTERNAL,
440 struct platform_device s3c_device_hsmmc2 = {
443 .num_resources = ARRAY_SIZE(s3c_hsmmc2_resource),
444 .resource = s3c_hsmmc2_resource,
446 .dma_mask = &samsung_device_dma_mask,
447 .coherent_dma_mask = DMA_BIT_MASK(32),
448 .platform_data = &s3c_hsmmc2_def_platdata,
452 void s3c_sdhci2_set_platdata(struct s3c_sdhci_platdata *pd)
454 s3c_sdhci_set_platdata(pd, &s3c_hsmmc2_def_platdata);
456 #endif /* CONFIG_S3C_DEV_HSMMC2 */
458 #ifdef CONFIG_S3C_DEV_HSMMC3
459 static struct resource s3c_hsmmc3_resource[] = {
460 [0] = DEFINE_RES_MEM(S3C_PA_HSMMC3, SZ_4K),
461 [1] = DEFINE_RES_IRQ(IRQ_HSMMC3),
464 struct s3c_sdhci_platdata s3c_hsmmc3_def_platdata = {
466 .host_caps = (MMC_CAP_4_BIT_DATA |
467 MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
468 .clk_type = S3C_SDHCI_CLK_DIV_INTERNAL,
471 struct platform_device s3c_device_hsmmc3 = {
474 .num_resources = ARRAY_SIZE(s3c_hsmmc3_resource),
475 .resource = s3c_hsmmc3_resource,
477 .dma_mask = &samsung_device_dma_mask,
478 .coherent_dma_mask = DMA_BIT_MASK(32),
479 .platform_data = &s3c_hsmmc3_def_platdata,
483 void s3c_sdhci3_set_platdata(struct s3c_sdhci_platdata *pd)
485 s3c_sdhci_set_platdata(pd, &s3c_hsmmc3_def_platdata);
487 #endif /* CONFIG_S3C_DEV_HSMMC3 */
491 static struct resource s3c_i2c0_resource[] = {
492 [0] = DEFINE_RES_MEM(S3C_PA_IIC, SZ_4K),
493 [1] = DEFINE_RES_IRQ(IRQ_IIC),
496 struct platform_device s3c_device_i2c0 = {
497 .name = "s3c2410-i2c",
498 #ifdef CONFIG_S3C_DEV_I2C1
503 .num_resources = ARRAY_SIZE(s3c_i2c0_resource),
504 .resource = s3c_i2c0_resource,
507 struct s3c2410_platform_i2c default_i2c_data __initdata = {
510 .frequency = 100*1000,
514 void __init s3c_i2c0_set_platdata(struct s3c2410_platform_i2c *pd)
516 struct s3c2410_platform_i2c *npd;
519 pd = &default_i2c_data;
523 npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
527 npd->cfg_gpio = s3c_i2c0_cfg_gpio;
530 #ifdef CONFIG_S3C_DEV_I2C1
531 static struct resource s3c_i2c1_resource[] = {
532 [0] = DEFINE_RES_MEM(S3C_PA_IIC1, SZ_4K),
533 [1] = DEFINE_RES_IRQ(IRQ_IIC1),
536 struct platform_device s3c_device_i2c1 = {
537 .name = "s3c2410-i2c",
539 .num_resources = ARRAY_SIZE(s3c_i2c1_resource),
540 .resource = s3c_i2c1_resource,
543 void __init s3c_i2c1_set_platdata(struct s3c2410_platform_i2c *pd)
545 struct s3c2410_platform_i2c *npd;
548 pd = &default_i2c_data;
552 npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
556 npd->cfg_gpio = s3c_i2c1_cfg_gpio;
558 #endif /* CONFIG_S3C_DEV_I2C1 */
560 #ifdef CONFIG_S3C_DEV_I2C2
561 static struct resource s3c_i2c2_resource[] = {
562 [0] = DEFINE_RES_MEM(S3C_PA_IIC2, SZ_4K),
563 [1] = DEFINE_RES_IRQ(IRQ_IIC2),
566 struct platform_device s3c_device_i2c2 = {
567 .name = "s3c2410-i2c",
569 .num_resources = ARRAY_SIZE(s3c_i2c2_resource),
570 .resource = s3c_i2c2_resource,
573 void __init s3c_i2c2_set_platdata(struct s3c2410_platform_i2c *pd)
575 struct s3c2410_platform_i2c *npd;
578 pd = &default_i2c_data;
582 npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
586 npd->cfg_gpio = s3c_i2c2_cfg_gpio;
588 #endif /* CONFIG_S3C_DEV_I2C2 */
590 #ifdef CONFIG_S3C_DEV_I2C3
591 static struct resource s3c_i2c3_resource[] = {
592 [0] = DEFINE_RES_MEM(S3C_PA_IIC3, SZ_4K),
593 [1] = DEFINE_RES_IRQ(IRQ_IIC3),
596 struct platform_device s3c_device_i2c3 = {
597 .name = "s3c2440-i2c",
599 .num_resources = ARRAY_SIZE(s3c_i2c3_resource),
600 .resource = s3c_i2c3_resource,
603 void __init s3c_i2c3_set_platdata(struct s3c2410_platform_i2c *pd)
605 struct s3c2410_platform_i2c *npd;
608 pd = &default_i2c_data;
612 npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
616 npd->cfg_gpio = s3c_i2c3_cfg_gpio;
618 #endif /*CONFIG_S3C_DEV_I2C3 */
620 #ifdef CONFIG_S3C_DEV_I2C4
621 static struct resource s3c_i2c4_resource[] = {
622 [0] = DEFINE_RES_MEM(S3C_PA_IIC4, SZ_4K),
623 [1] = DEFINE_RES_IRQ(IRQ_IIC4),
626 struct platform_device s3c_device_i2c4 = {
627 .name = "s3c2440-i2c",
629 .num_resources = ARRAY_SIZE(s3c_i2c4_resource),
630 .resource = s3c_i2c4_resource,
633 void __init s3c_i2c4_set_platdata(struct s3c2410_platform_i2c *pd)
635 struct s3c2410_platform_i2c *npd;
638 pd = &default_i2c_data;
642 npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
646 npd->cfg_gpio = s3c_i2c4_cfg_gpio;
648 #endif /*CONFIG_S3C_DEV_I2C4 */
650 #ifdef CONFIG_S3C_DEV_I2C5
651 static struct resource s3c_i2c5_resource[] = {
652 [0] = DEFINE_RES_MEM(S3C_PA_IIC5, SZ_4K),
653 [1] = DEFINE_RES_IRQ(IRQ_IIC5),
656 struct platform_device s3c_device_i2c5 = {
657 .name = "s3c2440-i2c",
659 .num_resources = ARRAY_SIZE(s3c_i2c5_resource),
660 .resource = s3c_i2c5_resource,
663 void __init s3c_i2c5_set_platdata(struct s3c2410_platform_i2c *pd)
665 struct s3c2410_platform_i2c *npd;
668 pd = &default_i2c_data;
672 npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
676 npd->cfg_gpio = s3c_i2c5_cfg_gpio;
678 #endif /*CONFIG_S3C_DEV_I2C5 */
680 #ifdef CONFIG_S3C_DEV_I2C6
681 static struct resource s3c_i2c6_resource[] = {
682 [0] = DEFINE_RES_MEM(S3C_PA_IIC6, SZ_4K),
683 [1] = DEFINE_RES_IRQ(IRQ_IIC6),
686 struct platform_device s3c_device_i2c6 = {
687 .name = "s3c2440-i2c",
689 .num_resources = ARRAY_SIZE(s3c_i2c6_resource),
690 .resource = s3c_i2c6_resource,
693 void __init s3c_i2c6_set_platdata(struct s3c2410_platform_i2c *pd)
695 struct s3c2410_platform_i2c *npd;
698 pd = &default_i2c_data;
702 npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
706 npd->cfg_gpio = s3c_i2c6_cfg_gpio;
708 #endif /* CONFIG_S3C_DEV_I2C6 */
710 #ifdef CONFIG_S3C_DEV_I2C7
711 static struct resource s3c_i2c7_resource[] = {
712 [0] = DEFINE_RES_MEM(S3C_PA_IIC7, SZ_4K),
713 [1] = DEFINE_RES_IRQ(IRQ_IIC7),
716 struct platform_device s3c_device_i2c7 = {
717 .name = "s3c2440-i2c",
719 .num_resources = ARRAY_SIZE(s3c_i2c7_resource),
720 .resource = s3c_i2c7_resource,
723 void __init s3c_i2c7_set_platdata(struct s3c2410_platform_i2c *pd)
725 struct s3c2410_platform_i2c *npd;
728 pd = &default_i2c_data;
732 npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
736 npd->cfg_gpio = s3c_i2c7_cfg_gpio;
738 #endif /* CONFIG_S3C_DEV_I2C7 */
742 #ifdef CONFIG_S5P_DEV_I2C_HDMIPHY
743 static struct resource s5p_i2c_resource[] = {
744 [0] = DEFINE_RES_MEM(S5P_PA_IIC_HDMIPHY, SZ_4K),
745 [1] = DEFINE_RES_IRQ(IRQ_IIC_HDMIPHY),
748 struct platform_device s5p_device_i2c_hdmiphy = {
749 .name = "s3c2440-hdmiphy-i2c",
751 .num_resources = ARRAY_SIZE(s5p_i2c_resource),
752 .resource = s5p_i2c_resource,
755 void __init s5p_i2c_hdmiphy_set_platdata(struct s3c2410_platform_i2c *pd)
757 struct s3c2410_platform_i2c *npd;
760 pd = &default_i2c_data;
762 if (soc_is_exynos4210())
764 else if (soc_is_s5pv210())
770 npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
771 &s5p_device_i2c_hdmiphy);
773 #endif /* CONFIG_S5P_DEV_I2C_HDMIPHY */
777 #ifdef CONFIG_PLAT_S3C24XX
778 static struct resource s3c_iis_resource[] = {
779 [0] = DEFINE_RES_MEM(S3C24XX_PA_IIS, S3C24XX_SZ_IIS),
782 struct platform_device s3c_device_iis = {
783 .name = "s3c24xx-iis",
785 .num_resources = ARRAY_SIZE(s3c_iis_resource),
786 .resource = s3c_iis_resource,
788 .dma_mask = &samsung_device_dma_mask,
789 .coherent_dma_mask = DMA_BIT_MASK(32),
792 #endif /* CONFIG_PLAT_S3C24XX */
794 #ifdef CONFIG_CPU_S3C2440
795 struct platform_device s3c2412_device_iis = {
796 .name = "s3c2412-iis",
799 .dma_mask = &samsung_device_dma_mask,
800 .coherent_dma_mask = DMA_BIT_MASK(32),
803 #endif /* CONFIG_CPU_S3C2440 */
807 #ifdef CONFIG_SAMSUNG_DEV_IDE
808 static struct resource s3c_cfcon_resource[] = {
809 [0] = DEFINE_RES_MEM(SAMSUNG_PA_CFCON, SZ_16K),
810 [1] = DEFINE_RES_IRQ(IRQ_CFCON),
813 struct platform_device s3c_device_cfcon = {
815 .num_resources = ARRAY_SIZE(s3c_cfcon_resource),
816 .resource = s3c_cfcon_resource,
819 void __init s3c_ide_set_platdata(struct s3c_ide_platdata *pdata)
821 s3c_set_platdata(pdata, sizeof(struct s3c_ide_platdata),
824 #endif /* CONFIG_SAMSUNG_DEV_IDE */
828 #ifdef CONFIG_SAMSUNG_DEV_KEYPAD
829 static struct resource samsung_keypad_resources[] = {
830 [0] = DEFINE_RES_MEM(SAMSUNG_PA_KEYPAD, SZ_32),
831 [1] = DEFINE_RES_IRQ(IRQ_KEYPAD),
834 struct platform_device samsung_device_keypad = {
835 .name = "samsung-keypad",
837 .num_resources = ARRAY_SIZE(samsung_keypad_resources),
838 .resource = samsung_keypad_resources,
841 void __init samsung_keypad_set_platdata(struct samsung_keypad_platdata *pd)
843 struct samsung_keypad_platdata *npd;
845 npd = s3c_set_platdata(pd, sizeof(struct samsung_keypad_platdata),
846 &samsung_device_keypad);
849 npd->cfg_gpio = samsung_keypad_cfg_gpio;
851 #endif /* CONFIG_SAMSUNG_DEV_KEYPAD */
855 #ifdef CONFIG_PLAT_S3C24XX
856 static struct resource s3c_lcd_resource[] = {
857 [0] = DEFINE_RES_MEM(S3C24XX_PA_LCD, S3C24XX_SZ_LCD),
858 [1] = DEFINE_RES_IRQ(IRQ_LCD),
861 struct platform_device s3c_device_lcd = {
862 .name = "s3c2410-lcd",
864 .num_resources = ARRAY_SIZE(s3c_lcd_resource),
865 .resource = s3c_lcd_resource,
867 .dma_mask = &samsung_device_dma_mask,
868 .coherent_dma_mask = DMA_BIT_MASK(32),
872 void __init s3c24xx_fb_set_platdata(struct s3c2410fb_mach_info *pd)
874 struct s3c2410fb_mach_info *npd;
876 npd = s3c_set_platdata(pd, sizeof(*npd), &s3c_device_lcd);
878 npd->displays = kmemdup(pd->displays,
879 sizeof(struct s3c2410fb_display) * npd->num_displays,
882 printk(KERN_ERR "no memory for LCD display data\n");
884 printk(KERN_ERR "no memory for LCD platform data\n");
887 #endif /* CONFIG_PLAT_S3C24XX */
891 #ifdef CONFIG_S5P_DEV_MFC
892 static struct resource s5p_mfc_resource[] = {
893 [0] = DEFINE_RES_MEM(S5P_PA_MFC, SZ_64K),
894 [1] = DEFINE_RES_IRQ(IRQ_MFC),
897 struct platform_device s5p_device_mfc = {
900 .num_resources = ARRAY_SIZE(s5p_mfc_resource),
901 .resource = s5p_mfc_resource,
905 * MFC hardware has 2 memory interfaces which are modelled as two separate
906 * platform devices to let dma-mapping distinguish between them.
908 * MFC parent device (s5p_device_mfc) must be registered before memory
909 * interface specific devices (s5p_device_mfc_l and s5p_device_mfc_r).
912 struct platform_device s5p_device_mfc_l = {
916 .parent = &s5p_device_mfc.dev,
917 .dma_mask = &samsung_device_dma_mask,
918 .coherent_dma_mask = DMA_BIT_MASK(32),
922 struct platform_device s5p_device_mfc_r = {
926 .parent = &s5p_device_mfc.dev,
927 .dma_mask = &samsung_device_dma_mask,
928 .coherent_dma_mask = DMA_BIT_MASK(32),
931 #endif /* CONFIG_S5P_DEV_MFC */
935 #ifdef CONFIG_S5P_DEV_CSIS0
936 static struct resource s5p_mipi_csis0_resource[] = {
937 [0] = DEFINE_RES_MEM(S5P_PA_MIPI_CSIS0, SZ_16K),
938 [1] = DEFINE_RES_IRQ(IRQ_MIPI_CSIS0),
941 struct platform_device s5p_device_mipi_csis0 = {
942 .name = "s5p-mipi-csis",
944 .num_resources = ARRAY_SIZE(s5p_mipi_csis0_resource),
945 .resource = s5p_mipi_csis0_resource,
947 #endif /* CONFIG_S5P_DEV_CSIS0 */
949 #ifdef CONFIG_S5P_DEV_CSIS1
950 static struct resource s5p_mipi_csis1_resource[] = {
951 [0] = DEFINE_RES_MEM(S5P_PA_MIPI_CSIS1, SZ_16K),
952 [1] = DEFINE_RES_IRQ(IRQ_MIPI_CSIS1),
955 struct platform_device s5p_device_mipi_csis1 = {
956 .name = "s5p-mipi-csis",
958 .num_resources = ARRAY_SIZE(s5p_mipi_csis1_resource),
959 .resource = s5p_mipi_csis1_resource,
965 #ifdef CONFIG_S3C_DEV_NAND
966 static struct resource s3c_nand_resource[] = {
967 [0] = DEFINE_RES_MEM(S3C_PA_NAND, SZ_1M),
970 struct platform_device s3c_device_nand = {
971 .name = "s3c2410-nand",
973 .num_resources = ARRAY_SIZE(s3c_nand_resource),
974 .resource = s3c_nand_resource,
978 * s3c_nand_copy_set() - copy nand set data
979 * @set: The new structure, directly copied from the old.
981 * Copy all the fields from the NAND set field from what is probably __initdata
982 * to new kernel memory. The code returns 0 if the copy happened correctly or
983 * an error code for the calling function to display.
985 * Note, we currently do not try and look to see if we've already copied the
986 * data in a previous set.
988 static int __init s3c_nand_copy_set(struct s3c2410_nand_set *set)
993 size = sizeof(struct mtd_partition) * set->nr_partitions;
995 ptr = kmemdup(set->partitions, size, GFP_KERNEL);
996 set->partitions = ptr;
1002 if (set->nr_map && set->nr_chips) {
1003 size = sizeof(int) * set->nr_chips;
1004 ptr = kmemdup(set->nr_map, size, GFP_KERNEL);
1011 if (set->ecc_layout) {
1012 ptr = kmemdup(set->ecc_layout,
1013 sizeof(struct nand_ecclayout), GFP_KERNEL);
1014 set->ecc_layout = ptr;
1023 void __init s3c_nand_set_platdata(struct s3c2410_platform_nand *nand)
1025 struct s3c2410_platform_nand *npd;
1029 /* note, if we get a failure in allocation, we simply drop out of the
1030 * function. If there is so little memory available at initialisation
1031 * time then there is little chance the system is going to run.
1034 npd = s3c_set_platdata(nand, sizeof(struct s3c2410_platform_nand),
1039 /* now see if we need to copy any of the nand set data */
1041 size = sizeof(struct s3c2410_nand_set) * npd->nr_sets;
1043 struct s3c2410_nand_set *from = npd->sets;
1044 struct s3c2410_nand_set *to;
1047 to = kmemdup(from, size, GFP_KERNEL);
1048 npd->sets = to; /* set, even if we failed */
1051 printk(KERN_ERR "%s: no memory for sets\n", __func__);
1055 for (i = 0; i < npd->nr_sets; i++) {
1056 ret = s3c_nand_copy_set(to);
1058 printk(KERN_ERR "%s: failed to copy set %d\n",
1066 #endif /* CONFIG_S3C_DEV_NAND */
1070 #ifdef CONFIG_S3C_DEV_ONENAND
1071 static struct resource s3c_onenand_resources[] = {
1072 [0] = DEFINE_RES_MEM(S3C_PA_ONENAND, SZ_1K),
1073 [1] = DEFINE_RES_MEM(S3C_PA_ONENAND_BUF, S3C_SZ_ONENAND_BUF),
1074 [2] = DEFINE_RES_IRQ(IRQ_ONENAND),
1077 struct platform_device s3c_device_onenand = {
1078 .name = "samsung-onenand",
1080 .num_resources = ARRAY_SIZE(s3c_onenand_resources),
1081 .resource = s3c_onenand_resources,
1083 #endif /* CONFIG_S3C_DEV_ONENAND */
1085 #ifdef CONFIG_S3C64XX_DEV_ONENAND1
1086 static struct resource s3c64xx_onenand1_resources[] = {
1087 [0] = DEFINE_RES_MEM(S3C64XX_PA_ONENAND1, SZ_1K),
1088 [1] = DEFINE_RES_MEM(S3C64XX_PA_ONENAND1_BUF, S3C64XX_SZ_ONENAND1_BUF),
1089 [2] = DEFINE_RES_IRQ(IRQ_ONENAND1),
1092 struct platform_device s3c64xx_device_onenand1 = {
1093 .name = "samsung-onenand",
1095 .num_resources = ARRAY_SIZE(s3c64xx_onenand1_resources),
1096 .resource = s3c64xx_onenand1_resources,
1099 void __init s3c64xx_onenand1_set_platdata(struct onenand_platform_data *pdata)
1101 s3c_set_platdata(pdata, sizeof(struct onenand_platform_data),
1102 &s3c64xx_device_onenand1);
1104 #endif /* CONFIG_S3C64XX_DEV_ONENAND1 */
1106 #ifdef CONFIG_S5P_DEV_ONENAND
1107 static struct resource s5p_onenand_resources[] = {
1108 [0] = DEFINE_RES_MEM(S5P_PA_ONENAND, SZ_128K),
1109 [1] = DEFINE_RES_MEM(S5P_PA_ONENAND_DMA, SZ_8K),
1110 [2] = DEFINE_RES_IRQ(IRQ_ONENAND_AUDI),
1113 struct platform_device s5p_device_onenand = {
1114 .name = "s5pc110-onenand",
1116 .num_resources = ARRAY_SIZE(s5p_onenand_resources),
1117 .resource = s5p_onenand_resources,
1119 #endif /* CONFIG_S5P_DEV_ONENAND */
1123 #ifdef CONFIG_PLAT_S5P
1124 static struct resource s5p_pmu_resource[] = {
1125 DEFINE_RES_IRQ(IRQ_PMU)
1128 struct platform_device s5p_device_pmu = {
1130 .id = ARM_PMU_DEVICE_CPU,
1131 .num_resources = ARRAY_SIZE(s5p_pmu_resource),
1132 .resource = s5p_pmu_resource,
1135 static int __init s5p_pmu_init(void)
1137 platform_device_register(&s5p_device_pmu);
1140 arch_initcall(s5p_pmu_init);
1141 #endif /* CONFIG_PLAT_S5P */
1145 #ifdef CONFIG_SAMSUNG_DEV_PWM
1147 #define TIMER_RESOURCE_SIZE (1)
1149 #define TIMER_RESOURCE(_tmr, _irq) \
1150 (struct resource [TIMER_RESOURCE_SIZE]) { \
1154 .flags = IORESOURCE_IRQ \
1158 #define DEFINE_S3C_TIMER(_tmr_no, _irq) \
1159 .name = "s3c24xx-pwm", \
1161 .num_resources = TIMER_RESOURCE_SIZE, \
1162 .resource = TIMER_RESOURCE(_tmr_no, _irq), \
1165 * since we already have an static mapping for the timer,
1166 * we do not bother setting any IO resource for the base.
1169 struct platform_device s3c_device_timer[] = {
1170 [0] = { DEFINE_S3C_TIMER(0, IRQ_TIMER0) },
1171 [1] = { DEFINE_S3C_TIMER(1, IRQ_TIMER1) },
1172 [2] = { DEFINE_S3C_TIMER(2, IRQ_TIMER2) },
1173 [3] = { DEFINE_S3C_TIMER(3, IRQ_TIMER3) },
1174 [4] = { DEFINE_S3C_TIMER(4, IRQ_TIMER4) },
1176 #endif /* CONFIG_SAMSUNG_DEV_PWM */
1180 #ifdef CONFIG_PLAT_S3C24XX
1181 static struct resource s3c_rtc_resource[] = {
1182 [0] = DEFINE_RES_MEM(S3C24XX_PA_RTC, SZ_256),
1183 [1] = DEFINE_RES_IRQ(IRQ_RTC),
1184 [2] = DEFINE_RES_IRQ(IRQ_TICK),
1187 struct platform_device s3c_device_rtc = {
1188 .name = "s3c2410-rtc",
1190 .num_resources = ARRAY_SIZE(s3c_rtc_resource),
1191 .resource = s3c_rtc_resource,
1193 #endif /* CONFIG_PLAT_S3C24XX */
1195 #ifdef CONFIG_S3C_DEV_RTC
1196 static struct resource s3c_rtc_resource[] = {
1197 [0] = DEFINE_RES_MEM(S3C_PA_RTC, SZ_256),
1198 [1] = DEFINE_RES_IRQ(IRQ_RTC_ALARM),
1199 [2] = DEFINE_RES_IRQ(IRQ_RTC_TIC),
1202 struct platform_device s3c_device_rtc = {
1203 .name = "s3c64xx-rtc",
1205 .num_resources = ARRAY_SIZE(s3c_rtc_resource),
1206 .resource = s3c_rtc_resource,
1208 #endif /* CONFIG_S3C_DEV_RTC */
1212 #ifdef CONFIG_PLAT_S3C24XX
1213 static struct resource s3c_sdi_resource[] = {
1214 [0] = DEFINE_RES_MEM(S3C24XX_PA_SDI, S3C24XX_SZ_SDI),
1215 [1] = DEFINE_RES_IRQ(IRQ_SDI),
1218 struct platform_device s3c_device_sdi = {
1219 .name = "s3c2410-sdi",
1221 .num_resources = ARRAY_SIZE(s3c_sdi_resource),
1222 .resource = s3c_sdi_resource,
1225 void __init s3c24xx_mci_set_platdata(struct s3c24xx_mci_pdata *pdata)
1227 s3c_set_platdata(pdata, sizeof(struct s3c24xx_mci_pdata),
1230 #endif /* CONFIG_PLAT_S3C24XX */
1234 #ifdef CONFIG_PLAT_S3C24XX
1235 static struct resource s3c_spi0_resource[] = {
1236 [0] = DEFINE_RES_MEM(S3C24XX_PA_SPI, SZ_32),
1237 [1] = DEFINE_RES_IRQ(IRQ_SPI0),
1240 struct platform_device s3c_device_spi0 = {
1241 .name = "s3c2410-spi",
1243 .num_resources = ARRAY_SIZE(s3c_spi0_resource),
1244 .resource = s3c_spi0_resource,
1246 .dma_mask = &samsung_device_dma_mask,
1247 .coherent_dma_mask = DMA_BIT_MASK(32),
1251 static struct resource s3c_spi1_resource[] = {
1252 [0] = DEFINE_RES_MEM(S3C24XX_PA_SPI1, SZ_32),
1253 [1] = DEFINE_RES_IRQ(IRQ_SPI1),
1256 struct platform_device s3c_device_spi1 = {
1257 .name = "s3c2410-spi",
1259 .num_resources = ARRAY_SIZE(s3c_spi1_resource),
1260 .resource = s3c_spi1_resource,
1262 .dma_mask = &samsung_device_dma_mask,
1263 .coherent_dma_mask = DMA_BIT_MASK(32),
1266 #endif /* CONFIG_PLAT_S3C24XX */
1270 #ifdef CONFIG_PLAT_S3C24XX
1271 static struct resource s3c_ts_resource[] = {
1272 [0] = DEFINE_RES_MEM(S3C24XX_PA_ADC, S3C24XX_SZ_ADC),
1273 [1] = DEFINE_RES_IRQ(IRQ_TC),
1276 struct platform_device s3c_device_ts = {
1277 .name = "s3c2410-ts",
1279 .dev.parent = &s3c_device_adc.dev,
1280 .num_resources = ARRAY_SIZE(s3c_ts_resource),
1281 .resource = s3c_ts_resource,
1284 void __init s3c24xx_ts_set_platdata(struct s3c2410_ts_mach_info *hard_s3c2410ts_info)
1286 s3c_set_platdata(hard_s3c2410ts_info,
1287 sizeof(struct s3c2410_ts_mach_info), &s3c_device_ts);
1289 #endif /* CONFIG_PLAT_S3C24XX */
1291 #ifdef CONFIG_SAMSUNG_DEV_TS
1292 static struct resource s3c_ts_resource[] = {
1293 [0] = DEFINE_RES_MEM(SAMSUNG_PA_ADC, SZ_256),
1294 [1] = DEFINE_RES_IRQ(IRQ_TC),
1297 static struct s3c2410_ts_mach_info default_ts_data __initdata = {
1300 .oversampling_shift = 2,
1303 struct platform_device s3c_device_ts = {
1304 .name = "s3c64xx-ts",
1306 .num_resources = ARRAY_SIZE(s3c_ts_resource),
1307 .resource = s3c_ts_resource,
1310 void __init s3c24xx_ts_set_platdata(struct s3c2410_ts_mach_info *pd)
1313 pd = &default_ts_data;
1315 s3c_set_platdata(pd, sizeof(struct s3c2410_ts_mach_info),
1318 #endif /* CONFIG_SAMSUNG_DEV_TS */
1322 #ifdef CONFIG_S5P_DEV_TV
1324 static struct resource s5p_hdmi_resources[] = {
1325 [0] = DEFINE_RES_MEM(S5P_PA_HDMI, SZ_1M),
1326 [1] = DEFINE_RES_IRQ(IRQ_HDMI),
1329 struct platform_device s5p_device_hdmi = {
1332 .num_resources = ARRAY_SIZE(s5p_hdmi_resources),
1333 .resource = s5p_hdmi_resources,
1336 static struct resource s5p_sdo_resources[] = {
1337 [0] = DEFINE_RES_MEM(S5P_PA_SDO, SZ_64K),
1338 [1] = DEFINE_RES_IRQ(IRQ_SDO),
1341 struct platform_device s5p_device_sdo = {
1344 .num_resources = ARRAY_SIZE(s5p_sdo_resources),
1345 .resource = s5p_sdo_resources,
1348 static struct resource s5p_mixer_resources[] = {
1349 [0] = DEFINE_RES_MEM_NAMED(S5P_PA_MIXER, SZ_64K, "mxr"),
1350 [1] = DEFINE_RES_MEM_NAMED(S5P_PA_VP, SZ_64K, "vp"),
1351 [2] = DEFINE_RES_IRQ_NAMED(IRQ_MIXER, "irq"),
1354 struct platform_device s5p_device_mixer = {
1355 .name = "s5p-mixer",
1357 .num_resources = ARRAY_SIZE(s5p_mixer_resources),
1358 .resource = s5p_mixer_resources,
1360 .dma_mask = &samsung_device_dma_mask,
1361 .coherent_dma_mask = DMA_BIT_MASK(32),
1364 #endif /* CONFIG_S5P_DEV_TV */
1368 #ifdef CONFIG_S3C_DEV_USB_HOST
1369 static struct resource s3c_usb_resource[] = {
1370 [0] = DEFINE_RES_MEM(S3C_PA_USBHOST, SZ_256),
1371 [1] = DEFINE_RES_IRQ(IRQ_USBH),
1374 struct platform_device s3c_device_ohci = {
1375 .name = "s3c2410-ohci",
1377 .num_resources = ARRAY_SIZE(s3c_usb_resource),
1378 .resource = s3c_usb_resource,
1380 .dma_mask = &samsung_device_dma_mask,
1381 .coherent_dma_mask = DMA_BIT_MASK(32),
1386 * s3c_ohci_set_platdata - initialise OHCI device platform data
1387 * @info: The platform data.
1389 * This call copies the @info passed in and sets the device .platform_data
1390 * field to that copy. The @info is copied so that the original can be marked
1394 void __init s3c_ohci_set_platdata(struct s3c2410_hcd_info *info)
1396 s3c_set_platdata(info, sizeof(struct s3c2410_hcd_info),
1399 #endif /* CONFIG_S3C_DEV_USB_HOST */
1401 /* USB Device (Gadget) */
1403 #ifdef CONFIG_PLAT_S3C24XX
1404 static struct resource s3c_usbgadget_resource[] = {
1405 [0] = DEFINE_RES_MEM(S3C24XX_PA_USBDEV, S3C24XX_SZ_USBDEV),
1406 [1] = DEFINE_RES_IRQ(IRQ_USBD),
1409 struct platform_device s3c_device_usbgadget = {
1410 .name = "s3c2410-usbgadget",
1412 .num_resources = ARRAY_SIZE(s3c_usbgadget_resource),
1413 .resource = s3c_usbgadget_resource,
1416 void __init s3c24xx_udc_set_platdata(struct s3c2410_udc_mach_info *pd)
1418 s3c_set_platdata(pd, sizeof(*pd), &s3c_device_usbgadget);
1420 #endif /* CONFIG_PLAT_S3C24XX */
1422 /* USB EHCI Host Controller */
1424 #ifdef CONFIG_S5P_DEV_USB_EHCI
1425 static struct resource s5p_ehci_resource[] = {
1426 [0] = DEFINE_RES_MEM(S5P_PA_EHCI, SZ_256),
1427 [1] = DEFINE_RES_IRQ(IRQ_USB_HOST),
1430 struct platform_device s5p_device_ehci = {
1433 .num_resources = ARRAY_SIZE(s5p_ehci_resource),
1434 .resource = s5p_ehci_resource,
1436 .dma_mask = &samsung_device_dma_mask,
1437 .coherent_dma_mask = DMA_BIT_MASK(32),
1441 void __init s5p_ehci_set_platdata(struct s5p_ehci_platdata *pd)
1443 struct s5p_ehci_platdata *npd;
1445 npd = s3c_set_platdata(pd, sizeof(struct s5p_ehci_platdata),
1449 npd->phy_init = s5p_usb_phy_init;
1451 npd->phy_exit = s5p_usb_phy_exit;
1453 #endif /* CONFIG_S5P_DEV_USB_EHCI */
1457 #ifdef CONFIG_S3C_DEV_USB_HSOTG
1458 static struct resource s3c_usb_hsotg_resources[] = {
1459 [0] = DEFINE_RES_MEM(S3C_PA_USB_HSOTG, SZ_16K),
1460 [1] = DEFINE_RES_IRQ(IRQ_OTG),
1463 struct platform_device s3c_device_usb_hsotg = {
1464 .name = "s3c-hsotg",
1466 .num_resources = ARRAY_SIZE(s3c_usb_hsotg_resources),
1467 .resource = s3c_usb_hsotg_resources,
1469 .dma_mask = &samsung_device_dma_mask,
1470 .coherent_dma_mask = DMA_BIT_MASK(32),
1474 void __init s3c_hsotg_set_platdata(struct s3c_hsotg_plat *pd)
1476 struct s3c_hsotg_plat *npd;
1478 npd = s3c_set_platdata(pd, sizeof(struct s3c_hsotg_plat),
1479 &s3c_device_usb_hsotg);
1482 npd->phy_init = s5p_usb_phy_init;
1484 npd->phy_exit = s5p_usb_phy_exit;
1486 #endif /* CONFIG_S3C_DEV_USB_HSOTG */
1488 /* USB High Spped 2.0 Device (Gadget) */
1490 #ifdef CONFIG_PLAT_S3C24XX
1491 static struct resource s3c_hsudc_resource[] = {
1492 [0] = DEFINE_RES_MEM(S3C2416_PA_HSUDC, S3C2416_SZ_HSUDC),
1493 [1] = DEFINE_RES_IRQ(IRQ_USBD),
1496 struct platform_device s3c_device_usb_hsudc = {
1497 .name = "s3c-hsudc",
1499 .num_resources = ARRAY_SIZE(s3c_hsudc_resource),
1500 .resource = s3c_hsudc_resource,
1502 .dma_mask = &samsung_device_dma_mask,
1503 .coherent_dma_mask = DMA_BIT_MASK(32),
1507 void __init s3c24xx_hsudc_set_platdata(struct s3c24xx_hsudc_platdata *pd)
1509 s3c_set_platdata(pd, sizeof(*pd), &s3c_device_usb_hsudc);
1511 #endif /* CONFIG_PLAT_S3C24XX */
1515 #ifdef CONFIG_S3C_DEV_WDT
1516 static struct resource s3c_wdt_resource[] = {
1517 [0] = DEFINE_RES_MEM(S3C_PA_WDT, SZ_1K),
1518 [1] = DEFINE_RES_IRQ(IRQ_WDT),
1521 struct platform_device s3c_device_wdt = {
1522 .name = "s3c2410-wdt",
1524 .num_resources = ARRAY_SIZE(s3c_wdt_resource),
1525 .resource = s3c_wdt_resource,
1527 #endif /* CONFIG_S3C_DEV_WDT */
1529 #ifdef CONFIG_S3C64XX_DEV_SPI0
1530 static struct resource s3c64xx_spi0_resource[] = {
1531 [0] = DEFINE_RES_MEM(S3C_PA_SPI0, SZ_256),
1532 [1] = DEFINE_RES_DMA(DMACH_SPI0_TX),
1533 [2] = DEFINE_RES_DMA(DMACH_SPI0_RX),
1534 [3] = DEFINE_RES_IRQ(IRQ_SPI0),
1537 struct platform_device s3c64xx_device_spi0 = {
1538 .name = "s3c64xx-spi",
1540 .num_resources = ARRAY_SIZE(s3c64xx_spi0_resource),
1541 .resource = s3c64xx_spi0_resource,
1543 .dma_mask = &samsung_device_dma_mask,
1544 .coherent_dma_mask = DMA_BIT_MASK(32),
1548 void __init s3c64xx_spi0_set_platdata(struct s3c64xx_spi_info *pd,
1549 int src_clk_nr, int num_cs)
1552 pr_err("%s:Need to pass platform data\n", __func__);
1556 /* Reject invalid configuration */
1557 if (!num_cs || src_clk_nr < 0) {
1558 pr_err("%s: Invalid SPI configuration\n", __func__);
1562 pd->num_cs = num_cs;
1563 pd->src_clk_nr = src_clk_nr;
1565 pd->cfg_gpio = s3c64xx_spi0_cfg_gpio;
1567 s3c_set_platdata(pd, sizeof(*pd), &s3c64xx_device_spi0);
1569 #endif /* CONFIG_S3C64XX_DEV_SPI0 */
1571 #ifdef CONFIG_S3C64XX_DEV_SPI1
1572 static struct resource s3c64xx_spi1_resource[] = {
1573 [0] = DEFINE_RES_MEM(S3C_PA_SPI1, SZ_256),
1574 [1] = DEFINE_RES_DMA(DMACH_SPI1_TX),
1575 [2] = DEFINE_RES_DMA(DMACH_SPI1_RX),
1576 [3] = DEFINE_RES_IRQ(IRQ_SPI1),
1579 struct platform_device s3c64xx_device_spi1 = {
1580 .name = "s3c64xx-spi",
1582 .num_resources = ARRAY_SIZE(s3c64xx_spi1_resource),
1583 .resource = s3c64xx_spi1_resource,
1585 .dma_mask = &samsung_device_dma_mask,
1586 .coherent_dma_mask = DMA_BIT_MASK(32),
1590 void __init s3c64xx_spi1_set_platdata(struct s3c64xx_spi_info *pd,
1591 int src_clk_nr, int num_cs)
1594 pr_err("%s:Need to pass platform data\n", __func__);
1598 /* Reject invalid configuration */
1599 if (!num_cs || src_clk_nr < 0) {
1600 pr_err("%s: Invalid SPI configuration\n", __func__);
1604 pd->num_cs = num_cs;
1605 pd->src_clk_nr = src_clk_nr;
1607 pd->cfg_gpio = s3c64xx_spi1_cfg_gpio;
1609 s3c_set_platdata(pd, sizeof(*pd), &s3c64xx_device_spi1);
1611 #endif /* CONFIG_S3C64XX_DEV_SPI1 */
1613 #ifdef CONFIG_S3C64XX_DEV_SPI2
1614 static struct resource s3c64xx_spi2_resource[] = {
1615 [0] = DEFINE_RES_MEM(S3C_PA_SPI2, SZ_256),
1616 [1] = DEFINE_RES_DMA(DMACH_SPI2_TX),
1617 [2] = DEFINE_RES_DMA(DMACH_SPI2_RX),
1618 [3] = DEFINE_RES_IRQ(IRQ_SPI2),
1621 struct platform_device s3c64xx_device_spi2 = {
1622 .name = "s3c64xx-spi",
1624 .num_resources = ARRAY_SIZE(s3c64xx_spi2_resource),
1625 .resource = s3c64xx_spi2_resource,
1627 .dma_mask = &samsung_device_dma_mask,
1628 .coherent_dma_mask = DMA_BIT_MASK(32),
1632 void __init s3c64xx_spi2_set_platdata(struct s3c64xx_spi_info *pd,
1633 int src_clk_nr, int num_cs)
1636 pr_err("%s:Need to pass platform data\n", __func__);
1640 /* Reject invalid configuration */
1641 if (!num_cs || src_clk_nr < 0) {
1642 pr_err("%s: Invalid SPI configuration\n", __func__);
1646 pd->num_cs = num_cs;
1647 pd->src_clk_nr = src_clk_nr;
1649 pd->cfg_gpio = s3c64xx_spi2_cfg_gpio;
1651 s3c_set_platdata(pd, sizeof(*pd), &s3c64xx_device_spi2);
1653 #endif /* CONFIG_S3C64XX_DEV_SPI2 */