3 select ACPI_CCA_REQUIRED if ACPI
4 select ACPI_GENERIC_GSI if ACPI
5 select ACPI_GTDT if ACPI
6 select ACPI_IORT if ACPI
7 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
8 select ACPI_MCFG if ACPI
9 select ACPI_SPCR_TABLE if ACPI
10 select ACPI_PPTT if ACPI
11 select ARCH_CLOCKSOURCE_DATA
12 select ARCH_HAS_DEBUG_VIRTUAL
13 select ARCH_HAS_DEVMEM_IS_ALLOWED
14 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
15 select ARCH_HAS_ELF_RANDOMIZE
16 select ARCH_HAS_FAST_MULTIPLIER
17 select ARCH_HAS_FORTIFY_SOURCE
18 select ARCH_HAS_GCOV_PROFILE_ALL
19 select ARCH_HAS_GIGANTIC_PAGE if (MEMORY_ISOLATION && COMPACTION) || CMA
21 select ARCH_HAS_MEMBARRIER_SYNC_CORE
22 select ARCH_HAS_SET_MEMORY
23 select ARCH_HAS_SG_CHAIN
24 select ARCH_HAS_STRICT_KERNEL_RWX
25 select ARCH_HAS_STRICT_MODULE_RWX
26 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
27 select ARCH_HAVE_NMI_SAFE_CMPXCHG
28 select ARCH_INLINE_READ_LOCK if !PREEMPT
29 select ARCH_INLINE_READ_LOCK_BH if !PREEMPT
30 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPT
31 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPT
32 select ARCH_INLINE_READ_UNLOCK if !PREEMPT
33 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPT
34 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPT
35 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPT
36 select ARCH_INLINE_WRITE_LOCK if !PREEMPT
37 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPT
38 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPT
39 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPT
40 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPT
41 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPT
42 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPT
43 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPT
44 select ARCH_USE_CMPXCHG_LOCKREF
45 select ARCH_USE_QUEUED_RWLOCKS
46 select ARCH_SUPPORTS_MEMORY_FAILURE
47 select ARCH_SUPPORTS_ATOMIC_RMW
48 select ARCH_SUPPORTS_NUMA_BALANCING
49 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
50 select ARCH_WANT_FRAME_POINTERS
51 select ARCH_HAS_UBSAN_SANITIZE_ALL
55 select AUDIT_ARCH_COMPAT_GENERIC
56 select ARM_GIC_V2M if PCI
58 select ARM_GIC_V3_ITS if PCI
60 select BUILDTIME_EXTABLE_SORT
61 select CLONE_BACKWARDS
63 select CPU_PM if (SUSPEND || CPU_IDLE)
64 select DCACHE_WORD_ACCESS
68 select GENERIC_ALLOCATOR
69 select GENERIC_ARCH_TOPOLOGY
70 select GENERIC_CLOCKEVENTS
71 select GENERIC_CLOCKEVENTS_BROADCAST
72 select GENERIC_CPU_AUTOPROBE
73 select GENERIC_EARLY_IOREMAP
74 select GENERIC_IDLE_POLL_SETUP
75 select GENERIC_IRQ_PROBE
76 select GENERIC_IRQ_SHOW
77 select GENERIC_IRQ_SHOW_LEVEL
78 select GENERIC_PCI_IOMAP
79 select GENERIC_SCHED_CLOCK
80 select GENERIC_SMP_IDLE_THREAD
81 select GENERIC_STRNCPY_FROM_USER
82 select GENERIC_STRNLEN_USER
83 select GENERIC_TIME_VSYSCALL
84 select HANDLE_DOMAIN_IRQ
85 select HARDIRQS_SW_RESEND
86 select HAVE_ACPI_APEI if (ACPI && EFI)
87 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
88 select HAVE_ARCH_AUDITSYSCALL
89 select HAVE_ARCH_BITREVERSE
90 select HAVE_ARCH_HUGE_VMAP
91 select HAVE_ARCH_JUMP_LABEL
92 select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
94 select HAVE_ARCH_MMAP_RND_BITS
95 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
96 select HAVE_ARCH_SECCOMP_FILTER
97 select HAVE_ARCH_THREAD_STRUCT_WHITELIST
98 select HAVE_ARCH_TRACEHOOK
99 select HAVE_ARCH_TRANSPARENT_HUGEPAGE
100 select HAVE_ARCH_VMAP_STACK
101 select HAVE_ARM_SMCCC
103 select HAVE_C_RECORDMCOUNT
104 select HAVE_CC_STACKPROTECTOR
105 select HAVE_CMPXCHG_DOUBLE
106 select HAVE_CMPXCHG_LOCAL
107 select HAVE_CONTEXT_TRACKING
108 select HAVE_DEBUG_BUGVERBOSE
109 select HAVE_DEBUG_KMEMLEAK
110 select HAVE_DMA_API_DEBUG
111 select HAVE_DMA_CONTIGUOUS
112 select HAVE_DYNAMIC_FTRACE
113 select HAVE_EFFICIENT_UNALIGNED_ACCESS
114 select HAVE_FTRACE_MCOUNT_RECORD
115 select HAVE_FUNCTION_TRACER
116 select HAVE_FUNCTION_GRAPH_TRACER
117 select HAVE_GCC_PLUGINS
118 select HAVE_GENERIC_DMA_COHERENT
119 select HAVE_HW_BREAKPOINT if PERF_EVENTS
120 select HAVE_IRQ_TIME_ACCOUNTING
122 select HAVE_MEMBLOCK_NODE_MAP if NUMA
124 select HAVE_PATA_PLATFORM
125 select HAVE_PERF_EVENTS
126 select HAVE_PERF_REGS
127 select HAVE_PERF_USER_STACK_DUMP
128 select HAVE_REGS_AND_STACK_ACCESS_API
129 select HAVE_RCU_TABLE_FREE
130 select HAVE_SYSCALL_TRACEPOINTS
132 select HAVE_KRETPROBES
133 select IOMMU_DMA if IOMMU_SUPPORT
135 select IRQ_FORCED_THREADING
136 select MODULES_USE_ELF_RELA
137 select MULTI_IRQ_HANDLER
140 select OF_EARLY_FLATTREE
141 select OF_RESERVED_MEM
142 select PCI_ECAM if ACPI
147 select SYSCTL_EXCEPTION_TRACE
148 select THREAD_INFO_IN_TASK
150 ARM 64-bit (AArch64) Linux support.
155 config ARCH_PHYS_ADDR_T_64BIT
161 config ARM64_PAGE_SHIFT
163 default 16 if ARM64_64K_PAGES
164 default 14 if ARM64_16K_PAGES
167 config ARM64_CONT_SHIFT
169 default 5 if ARM64_64K_PAGES
170 default 7 if ARM64_16K_PAGES
173 config ARCH_MMAP_RND_BITS_MIN
174 default 14 if ARM64_64K_PAGES
175 default 16 if ARM64_16K_PAGES
178 # max bits determined by the following formula:
179 # VA_BITS - PAGE_SHIFT - 3
180 config ARCH_MMAP_RND_BITS_MAX
181 default 19 if ARM64_VA_BITS=36
182 default 24 if ARM64_VA_BITS=39
183 default 27 if ARM64_VA_BITS=42
184 default 30 if ARM64_VA_BITS=47
185 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
186 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
187 default 33 if ARM64_VA_BITS=48
188 default 14 if ARM64_64K_PAGES
189 default 16 if ARM64_16K_PAGES
192 config ARCH_MMAP_RND_COMPAT_BITS_MIN
193 default 7 if ARM64_64K_PAGES
194 default 9 if ARM64_16K_PAGES
197 config ARCH_MMAP_RND_COMPAT_BITS_MAX
203 config STACKTRACE_SUPPORT
206 config ILLEGAL_POINTER_VALUE
208 default 0xdead000000000000
210 config LOCKDEP_SUPPORT
213 config TRACE_IRQFLAGS_SUPPORT
216 config RWSEM_XCHGADD_ALGORITHM
223 config GENERIC_BUG_RELATIVE_POINTERS
225 depends on GENERIC_BUG
227 config GENERIC_HWEIGHT
233 config GENERIC_CALIBRATE_DELAY
239 config HAVE_GENERIC_GUP
242 config ARCH_DMA_ADDR_T_64BIT
245 config NEED_DMA_MAP_STATE
248 config NEED_SG_DMA_LENGTH
260 config KERNEL_MODE_NEON
263 config FIX_EARLYCON_MEM
266 config PGTABLE_LEVELS
268 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
269 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
270 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
271 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
272 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
273 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
275 config ARCH_SUPPORTS_UPROBES
278 config ARCH_PROC_KCORE_TEXT
281 config MULTI_IRQ_HANDLER
284 source "init/Kconfig"
286 source "kernel/Kconfig.freezer"
288 source "arch/arm64/Kconfig.platforms"
295 This feature enables support for PCI bus system. If you say Y
296 here, the kernel will include drivers and infrastructure code
297 to support PCI bus devices.
302 config PCI_DOMAINS_GENERIC
308 source "drivers/pci/Kconfig"
312 menu "Kernel Features"
314 menu "ARM errata workarounds via the alternatives framework"
316 config ARM64_ERRATUM_826319
317 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
320 This option adds an alternative code sequence to work around ARM
321 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
322 AXI master interface and an L2 cache.
324 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
325 and is unable to accept a certain write via this interface, it will
326 not progress on read data presented on the read data channel and the
329 The workaround promotes data cache clean instructions to
330 data cache clean-and-invalidate.
331 Please note that this does not necessarily enable the workaround,
332 as it depends on the alternative framework, which will only patch
333 the kernel if an affected CPU is detected.
337 config ARM64_ERRATUM_827319
338 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
341 This option adds an alternative code sequence to work around ARM
342 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
343 master interface and an L2 cache.
345 Under certain conditions this erratum can cause a clean line eviction
346 to occur at the same time as another transaction to the same address
347 on the AMBA 5 CHI interface, which can cause data corruption if the
348 interconnect reorders the two transactions.
350 The workaround promotes data cache clean instructions to
351 data cache clean-and-invalidate.
352 Please note that this does not necessarily enable the workaround,
353 as it depends on the alternative framework, which will only patch
354 the kernel if an affected CPU is detected.
358 config ARM64_ERRATUM_824069
359 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
362 This option adds an alternative code sequence to work around ARM
363 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
364 to a coherent interconnect.
366 If a Cortex-A53 processor is executing a store or prefetch for
367 write instruction at the same time as a processor in another
368 cluster is executing a cache maintenance operation to the same
369 address, then this erratum might cause a clean cache line to be
370 incorrectly marked as dirty.
372 The workaround promotes data cache clean instructions to
373 data cache clean-and-invalidate.
374 Please note that this option does not necessarily enable the
375 workaround, as it depends on the alternative framework, which will
376 only patch the kernel if an affected CPU is detected.
380 config ARM64_ERRATUM_819472
381 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
384 This option adds an alternative code sequence to work around ARM
385 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
386 present when it is connected to a coherent interconnect.
388 If the processor is executing a load and store exclusive sequence at
389 the same time as a processor in another cluster is executing a cache
390 maintenance operation to the same address, then this erratum might
391 cause data corruption.
393 The workaround promotes data cache clean instructions to
394 data cache clean-and-invalidate.
395 Please note that this does not necessarily enable the workaround,
396 as it depends on the alternative framework, which will only patch
397 the kernel if an affected CPU is detected.
401 config ARM64_ERRATUM_832075
402 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
405 This option adds an alternative code sequence to work around ARM
406 erratum 832075 on Cortex-A57 parts up to r1p2.
408 Affected Cortex-A57 parts might deadlock when exclusive load/store
409 instructions to Write-Back memory are mixed with Device loads.
411 The workaround is to promote device loads to use Load-Acquire
413 Please note that this does not necessarily enable the workaround,
414 as it depends on the alternative framework, which will only patch
415 the kernel if an affected CPU is detected.
419 config ARM64_ERRATUM_834220
420 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
424 This option adds an alternative code sequence to work around ARM
425 erratum 834220 on Cortex-A57 parts up to r1p2.
427 Affected Cortex-A57 parts might report a Stage 2 translation
428 fault as the result of a Stage 1 fault for load crossing a
429 page boundary when there is a permission or device memory
430 alignment fault at Stage 1 and a translation fault at Stage 2.
432 The workaround is to verify that the Stage 1 translation
433 doesn't generate a fault before handling the Stage 2 fault.
434 Please note that this does not necessarily enable the workaround,
435 as it depends on the alternative framework, which will only patch
436 the kernel if an affected CPU is detected.
440 config ARM64_ERRATUM_845719
441 bool "Cortex-A53: 845719: a load might read incorrect data"
445 This option adds an alternative code sequence to work around ARM
446 erratum 845719 on Cortex-A53 parts up to r0p4.
448 When running a compat (AArch32) userspace on an affected Cortex-A53
449 part, a load at EL0 from a virtual address that matches the bottom 32
450 bits of the virtual address used by a recent load at (AArch64) EL1
451 might return incorrect data.
453 The workaround is to write the contextidr_el1 register on exception
454 return to a 32-bit task.
455 Please note that this does not necessarily enable the workaround,
456 as it depends on the alternative framework, which will only patch
457 the kernel if an affected CPU is detected.
461 config ARM64_ERRATUM_843419
462 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
464 select ARM64_MODULE_PLTS if MODULES
466 This option links the kernel with '--fix-cortex-a53-843419' and
467 enables PLT support to replace certain ADRP instructions, which can
468 cause subsequent memory accesses to use an incorrect address on
469 Cortex-A53 parts up to r0p4.
473 config ARM64_ERRATUM_1024718
474 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update"
477 This option adds work around for Arm Cortex-A55 Erratum 1024718.
479 Affected Cortex-A55 cores (r0p0, r0p1, r1p0) could cause incorrect
480 update of the hardware dirty bit when the DBM/AP bits are updated
481 without a break-before-make. The work around is to disable the usage
482 of hardware DBM locally on the affected cores. CPUs not affected by
483 erratum will continue to use the feature.
487 config CAVIUM_ERRATUM_22375
488 bool "Cavium erratum 22375, 24313"
491 Enable workaround for erratum 22375, 24313.
493 This implements two gicv3-its errata workarounds for ThunderX. Both
494 with small impact affecting only ITS table allocation.
496 erratum 22375: only alloc 8MB table size
497 erratum 24313: ignore memory access type
499 The fixes are in ITS initialization and basically ignore memory access
500 type and table size provided by the TYPER and BASER registers.
504 config CAVIUM_ERRATUM_23144
505 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
509 ITS SYNC command hang for cross node io and collections/cpu mapping.
513 config CAVIUM_ERRATUM_23154
514 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
517 The gicv3 of ThunderX requires a modified version for
518 reading the IAR status to ensure data synchronization
519 (access to icc_iar1_el1 is not sync'ed before and after).
523 config CAVIUM_ERRATUM_27456
524 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
527 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
528 instructions may cause the icache to become corrupted if it
529 contains data for a non-current ASID. The fix is to
530 invalidate the icache when changing the mm context.
534 config CAVIUM_ERRATUM_30115
535 bool "Cavium erratum 30115: Guest may disable interrupts in host"
538 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through
539 1.2, and T83 Pass 1.0, KVM guest execution may disable
540 interrupts in host. Trapping both GICv3 group-0 and group-1
541 accesses sidesteps the issue.
545 config QCOM_FALKOR_ERRATUM_1003
546 bool "Falkor E1003: Incorrect translation due to ASID change"
549 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
550 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID
551 in TTBR1_EL1, this situation only occurs in the entry trampoline and
552 then only for entries in the walk cache, since the leaf translation
553 is unchanged. Work around the erratum by invalidating the walk cache
554 entries for the trampoline before entering the kernel proper.
556 config QCOM_FALKOR_ERRATUM_1009
557 bool "Falkor E1009: Prematurely complete a DSB after a TLBI"
560 On Falkor v1, the CPU may prematurely complete a DSB following a
561 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation
562 one more time to fix the issue.
566 config QCOM_QDF2400_ERRATUM_0065
567 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size"
570 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports
571 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have
572 been indicated as 16Bytes (0xf), not 8Bytes (0x7).
576 config SOCIONEXT_SYNQUACER_PREITS
577 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
580 Socionext Synquacer SoCs implement a separate h/w block to generate
581 MSI doorbell writes with non-zero values for the device ID.
585 config HISILICON_ERRATUM_161600802
586 bool "Hip07 161600802: Erroneous redistributor VLPI base"
589 The HiSilicon Hip07 SoC usees the wrong redistributor base
590 when issued ITS commands such as VMOVP and VMAPP, and requires
591 a 128kB offset to be applied to the target address in this commands.
595 config QCOM_FALKOR_ERRATUM_E1041
596 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access"
599 Falkor CPU may speculatively fetch instructions from an improper
600 memory location when MMU translation is changed from SCTLR_ELn[M]=1
601 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem.
610 default ARM64_4K_PAGES
612 Page size (translation granule) configuration.
614 config ARM64_4K_PAGES
617 This feature enables 4KB pages support.
619 config ARM64_16K_PAGES
622 The system will use 16KB pages support. AArch32 emulation
623 requires applications compiled with 16K (or a multiple of 16K)
626 config ARM64_64K_PAGES
629 This feature enables 64KB pages support (4KB by default)
630 allowing only two levels of page tables and faster TLB
631 look-up. AArch32 emulation requires applications compiled
632 with 64K aligned segments.
637 prompt "Virtual address space size"
638 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
639 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
640 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
642 Allows choosing one of multiple possible virtual address
643 space sizes. The level of translation table is determined by
644 a combination of page size and virtual address space size.
646 config ARM64_VA_BITS_36
647 bool "36-bit" if EXPERT
648 depends on ARM64_16K_PAGES
650 config ARM64_VA_BITS_39
652 depends on ARM64_4K_PAGES
654 config ARM64_VA_BITS_42
656 depends on ARM64_64K_PAGES
658 config ARM64_VA_BITS_47
660 depends on ARM64_16K_PAGES
662 config ARM64_VA_BITS_48
669 default 36 if ARM64_VA_BITS_36
670 default 39 if ARM64_VA_BITS_39
671 default 42 if ARM64_VA_BITS_42
672 default 47 if ARM64_VA_BITS_47
673 default 48 if ARM64_VA_BITS_48
676 prompt "Physical address space size"
677 default ARM64_PA_BITS_48
679 Choose the maximum physical address range that the kernel will
682 config ARM64_PA_BITS_48
685 config ARM64_PA_BITS_52
686 bool "52-bit (ARMv8.2)"
687 depends on ARM64_64K_PAGES
688 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
690 Enable support for a 52-bit physical address space, introduced as
691 part of the ARMv8.2-LPA extension.
693 With this enabled, the kernel will also continue to work on CPUs that
694 do not support ARMv8.2-LPA, but with some added memory overhead (and
695 minor performance overhead).
701 default 48 if ARM64_PA_BITS_48
702 default 52 if ARM64_PA_BITS_52
704 config CPU_BIG_ENDIAN
705 bool "Build big-endian kernel"
707 Say Y if you plan on running a kernel in big-endian mode.
710 bool "Multi-core scheduler support"
712 Multi-core scheduler support improves the CPU scheduler's decision
713 making when dealing with multi-core CPU chips at a cost of slightly
714 increased overhead in some places. If unsure say N here.
717 bool "SMT scheduler support"
719 Improves the CPU scheduler's decision making when dealing with
720 MultiThreading at a cost of slightly increased overhead in some
721 places. If unsure say N here.
724 int "Maximum number of CPUs (2-4096)"
726 # These have to remain sorted largest to smallest
730 bool "Support for hot-pluggable CPUs"
731 select GENERIC_IRQ_MIGRATION
733 Say Y here to experiment with turning CPUs off and on. CPUs
734 can be controlled through /sys/devices/system/cpu.
736 # Common NUMA Features
738 bool "Numa Memory Allocation and Scheduler Support"
739 select ACPI_NUMA if ACPI
742 Enable NUMA (Non Uniform Memory Access) support.
744 The kernel will try to allocate memory used by a CPU on the
745 local memory of the CPU and add some more
746 NUMA awareness to the kernel.
749 int "Maximum NUMA Nodes (as a power of 2)"
752 depends on NEED_MULTIPLE_NODES
754 Specify the maximum number of NUMA Nodes available on the target
755 system. Increases memory reserved to accommodate various tables.
757 config USE_PERCPU_NUMA_NODE_ID
761 config HAVE_SETUP_PER_CPU_AREA
765 config NEED_PER_CPU_EMBED_FIRST_CHUNK
773 source kernel/Kconfig.preempt
774 source kernel/Kconfig.hz
776 config ARCH_SUPPORTS_DEBUG_PAGEALLOC
779 config ARCH_HAS_HOLES_MEMORYMODEL
780 def_bool y if SPARSEMEM
782 config ARCH_SPARSEMEM_ENABLE
784 select SPARSEMEM_VMEMMAP_ENABLE
786 config ARCH_SPARSEMEM_DEFAULT
787 def_bool ARCH_SPARSEMEM_ENABLE
789 config ARCH_SELECT_MEMORY_MODEL
790 def_bool ARCH_SPARSEMEM_ENABLE
792 config HAVE_ARCH_PFN_VALID
793 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
795 config HW_PERF_EVENTS
799 config SYS_SUPPORTS_HUGETLBFS
802 config ARCH_WANT_HUGE_PMD_SHARE
803 def_bool y if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
805 config ARCH_HAS_CACHE_LINE_SIZE
811 bool "Enable seccomp to safely compute untrusted bytecode"
813 This kernel feature is useful for number crunching applications
814 that may need to compute untrusted bytecode during their
815 execution. By using pipes or other transports made available to
816 the process as file descriptors supporting the read/write
817 syscalls, it's possible to isolate those applications in
818 their own address space using seccomp. Once seccomp is
819 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
820 and the task is only allowed to execute a few safe syscalls
821 defined by each seccomp mode.
824 bool "Enable paravirtualization code"
826 This changes the kernel so it can modify itself when it is run
827 under a hypervisor, potentially improving performance significantly
828 over full virtualization.
830 config PARAVIRT_TIME_ACCOUNTING
831 bool "Paravirtual steal time accounting"
835 Select this option to enable fine granularity task steal time
836 accounting. Time spent executing other tasks in parallel with
837 the current vCPU is discounted from the vCPU power. To account for
838 that, there can be a small performance impact.
840 If in doubt, say N here.
843 depends on PM_SLEEP_SMP
845 bool "kexec system call"
847 kexec is a system call that implements the ability to shutdown your
848 current kernel, and to start another kernel. It is like a reboot
849 but it is independent of the system firmware. And like a reboot
850 you can start any kernel with it, not just Linux.
853 bool "Build kdump crash kernel"
855 Generate crash dump after being started by kexec. This should
856 be normally only set in special crash dump kernels which are
857 loaded in the main kernel with kexec-tools into a specially
858 reserved region and then later executed after a crash by
861 For more details see Documentation/kdump/kdump.txt
868 bool "Xen guest support on ARM64"
869 depends on ARM64 && OF
873 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
875 config FORCE_MAX_ZONEORDER
877 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
878 default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE)
881 The kernel memory allocator divides physically contiguous memory
882 blocks into "zones", where each zone is a power of two number of
883 pages. This option selects the largest power of two that the kernel
884 keeps in the memory allocator. If you need to allocate very large
885 blocks of physically contiguous memory, then you may need to
888 This config option is actually maximum order plus one. For example,
889 a value of 11 means that the largest free memory block is 2^10 pages.
891 We make sure that we can allocate upto a HugePage size for each configuration.
893 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
895 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
896 4M allocations matching the default size used by generic code.
898 config UNMAP_KERNEL_AT_EL0
899 bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT
902 Speculation attacks against some high-performance processors can
903 be used to bypass MMU permission checks and leak kernel data to
904 userspace. This can be defended against by unmapping the kernel
905 when running in userspace, mapping it back in on exception entry
906 via a trampoline page in the vector table.
910 config HARDEN_BRANCH_PREDICTOR
911 bool "Harden the branch predictor against aliasing attacks" if EXPERT
914 Speculation attacks against some high-performance processors rely on
915 being able to manipulate the branch predictor for a victim context by
916 executing aliasing branches in the attacker context. Such attacks
917 can be partially mitigated against by clearing internal branch
918 predictor state and limiting the prediction logic in some situations.
920 This config option will take CPU-specific actions to harden the
921 branch predictor against aliasing attacks and may rely on specific
922 instruction sequences or control bits being set by the system
927 config HARDEN_EL2_VECTORS
928 bool "Harden EL2 vector mapping against system register leak" if EXPERT
931 Speculation attacks against some high-performance processors can
932 be used to leak privileged information such as the vector base
933 register, resulting in a potential defeat of the EL2 layout
936 This config option will map the vectors to a fixed location,
937 independent of the EL2 code mapping, so that revealing VBAR_EL2
938 to an attacker does not give away any extra information. This
939 only gets enabled on affected CPUs.
943 menuconfig ARMV8_DEPRECATED
944 bool "Emulate deprecated/obsolete ARMv8 instructions"
948 Legacy software support may require certain instructions
949 that have been deprecated or obsoleted in the architecture.
951 Enable this config to enable selective emulation of these
959 bool "Emulate SWP/SWPB instructions"
961 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
962 they are always undefined. Say Y here to enable software
963 emulation of these instructions for userspace using LDXR/STXR.
965 In some older versions of glibc [<=2.8] SWP is used during futex
966 trylock() operations with the assumption that the code will not
967 be preempted. This invalid assumption may be more likely to fail
968 with SWP emulation enabled, leading to deadlock of the user
971 NOTE: when accessing uncached shared regions, LDXR/STXR rely
972 on an external transaction monitoring block called a global
973 monitor to maintain update atomicity. If your system does not
974 implement a global monitor, this option can cause programs that
975 perform SWP operations to uncached memory to deadlock.
979 config CP15_BARRIER_EMULATION
980 bool "Emulate CP15 Barrier instructions"
982 The CP15 barrier instructions - CP15ISB, CP15DSB, and
983 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
984 strongly recommended to use the ISB, DSB, and DMB
985 instructions instead.
987 Say Y here to enable software emulation of these
988 instructions for AArch32 userspace code. When this option is
989 enabled, CP15 barrier usage is traced which can help
990 identify software that needs updating.
994 config SETEND_EMULATION
995 bool "Emulate SETEND instruction"
997 The SETEND instruction alters the data-endianness of the
998 AArch32 EL0, and is deprecated in ARMv8.
1000 Say Y here to enable software emulation of the instruction
1001 for AArch32 userspace code.
1003 Note: All the cpus on the system must have mixed endian support at EL0
1004 for this feature to be enabled. If a new CPU - which doesn't support mixed
1005 endian - is hotplugged in after this feature has been enabled, there could
1006 be unexpected results in the applications.
1011 config ARM64_SW_TTBR0_PAN
1012 bool "Emulate Privileged Access Never using TTBR0_EL1 switching"
1014 Enabling this option prevents the kernel from accessing
1015 user-space memory directly by pointing TTBR0_EL1 to a reserved
1016 zeroed area and reserved ASID. The user access routines
1017 restore the valid TTBR0_EL1 temporarily.
1019 menu "ARMv8.1 architectural features"
1021 config ARM64_HW_AFDBM
1022 bool "Support for hardware updates of the Access and Dirty page flags"
1025 The ARMv8.1 architecture extensions introduce support for
1026 hardware updates of the access and dirty information in page
1027 table entries. When enabled in TCR_EL1 (HA and HD bits) on
1028 capable processors, accesses to pages with PTE_AF cleared will
1029 set this bit instead of raising an access flag fault.
1030 Similarly, writes to read-only pages with the DBM bit set will
1031 clear the read-only bit (AP[2]) instead of raising a
1034 Kernels built with this configuration option enabled continue
1035 to work on pre-ARMv8.1 hardware and the performance impact is
1036 minimal. If unsure, say Y.
1039 bool "Enable support for Privileged Access Never (PAN)"
1042 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
1043 prevents the kernel or hypervisor from accessing user-space (EL0)
1046 Choosing this option will cause any unprotected (not using
1047 copy_to_user et al) memory access to fail with a permission fault.
1049 The feature is detected at runtime, and will remain as a 'nop'
1050 instruction if the cpu does not implement the feature.
1052 config ARM64_LSE_ATOMICS
1053 bool "Atomic instructions"
1056 As part of the Large System Extensions, ARMv8.1 introduces new
1057 atomic instructions that are designed specifically to scale in
1060 Say Y here to make use of these instructions for the in-kernel
1061 atomic routines. This incurs a small overhead on CPUs that do
1062 not support these instructions and requires the kernel to be
1063 built with binutils >= 2.25 in order for the new instructions
1067 bool "Enable support for Virtualization Host Extensions (VHE)"
1070 Virtualization Host Extensions (VHE) allow the kernel to run
1071 directly at EL2 (instead of EL1) on processors that support
1072 it. This leads to better performance for KVM, as they reduce
1073 the cost of the world switch.
1075 Selecting this option allows the VHE feature to be detected
1076 at runtime, and does not affect processors that do not
1077 implement this feature.
1081 menu "ARMv8.2 architectural features"
1084 bool "Enable support for User Access Override (UAO)"
1087 User Access Override (UAO; part of the ARMv8.2 Extensions)
1088 causes the 'unprivileged' variant of the load/store instructions to
1089 be overridden to be privileged.
1091 This option changes get_user() and friends to use the 'unprivileged'
1092 variant of the load/store instructions. This ensures that user-space
1093 really did have access to the supplied memory. When addr_limit is
1094 set to kernel memory the UAO bit will be set, allowing privileged
1095 access to kernel memory.
1097 Choosing this option will cause copy_to_user() et al to use user-space
1100 The feature is detected at runtime, the kernel will use the
1101 regular load/store instructions if the cpu does not implement the
1105 bool "Enable support for persistent memory"
1106 select ARCH_HAS_PMEM_API
1107 select ARCH_HAS_UACCESS_FLUSHCACHE
1109 Say Y to enable support for the persistent memory API based on the
1110 ARMv8.2 DCPoP feature.
1112 The feature is detected at runtime, and the kernel will use DC CVAC
1113 operations if DC CVAP is not supported (following the behaviour of
1114 DC CVAP itself if the system does not define a point of persistence).
1116 config ARM64_RAS_EXTN
1117 bool "Enable support for RAS CPU Extensions"
1120 CPUs that support the Reliability, Availability and Serviceability
1121 (RAS) Extensions, part of ARMv8.2 are able to track faults and
1122 errors, classify them and report them to software.
1124 On CPUs with these extensions system software can use additional
1125 barriers to determine if faults are pending and read the
1126 classification from a new set of registers.
1128 Selecting this feature will allow the kernel to use these barriers
1129 and access the new registers if the system supports the extension.
1130 Platform RAS features may additionally depend on firmware support.
1135 bool "ARM Scalable Vector Extension support"
1138 The Scalable Vector Extension (SVE) is an extension to the AArch64
1139 execution state which complements and extends the SIMD functionality
1140 of the base architecture to support much larger vectors and to enable
1141 additional vectorisation opportunities.
1143 To enable use of this extension on CPUs that implement it, say Y.
1145 Note that for architectural reasons, firmware _must_ implement SVE
1146 support when running on SVE capable hardware. The required support
1149 * version 1.5 and later of the ARM Trusted Firmware
1150 * the AArch64 boot wrapper since commit 5e1261e08abf
1151 ("bootwrapper: SVE: Enable SVE for EL2 and below").
1153 For other firmware implementations, consult the firmware documentation
1156 If you need the kernel to boot on SVE-capable hardware with broken
1157 firmware, you may need to say N here until you get your firmware
1158 fixed. Otherwise, you may experience firmware panics or lockups when
1159 booting the kernel. If unsure and you are not observing these
1160 symptoms, you should assume that it is safe to say Y.
1162 config ARM64_MODULE_PLTS
1164 select HAVE_MOD_ARCH_SPECIFIC
1169 This builds the kernel as a Position Independent Executable (PIE),
1170 which retains all relocation metadata required to relocate the
1171 kernel binary at runtime to a different virtual address than the
1172 address it was linked at.
1173 Since AArch64 uses the RELA relocation format, this requires a
1174 relocation pass at runtime even if the kernel is loaded at the
1175 same address it was linked at.
1177 config RANDOMIZE_BASE
1178 bool "Randomize the address of the kernel image"
1179 select ARM64_MODULE_PLTS if MODULES
1182 Randomizes the virtual address at which the kernel image is
1183 loaded, as a security feature that deters exploit attempts
1184 relying on knowledge of the location of kernel internals.
1186 It is the bootloader's job to provide entropy, by passing a
1187 random u64 value in /chosen/kaslr-seed at kernel entry.
1189 When booting via the UEFI stub, it will invoke the firmware's
1190 EFI_RNG_PROTOCOL implementation (if available) to supply entropy
1191 to the kernel proper. In addition, it will randomise the physical
1192 location of the kernel Image as well.
1196 config RANDOMIZE_MODULE_REGION_FULL
1197 bool "Randomize the module region over a 4 GB range"
1198 depends on RANDOMIZE_BASE
1201 Randomizes the location of the module region inside a 4 GB window
1202 covering the core kernel. This way, it is less likely for modules
1203 to leak information about the location of core kernel data structures
1204 but it does imply that function calls between modules and the core
1205 kernel will need to be resolved via veneers in the module PLT.
1207 When this option is not set, the module region will be randomized over
1208 a limited range that contains the [_stext, _etext] interval of the
1209 core kernel, so branch relocations are always in range.
1215 config ARM64_ACPI_PARKING_PROTOCOL
1216 bool "Enable support for the ARM64 ACPI parking protocol"
1219 Enable support for the ARM64 ACPI parking protocol. If disabled
1220 the kernel will not allow booting through the ARM64 ACPI parking
1221 protocol even if the corresponding data is present in the ACPI
1225 string "Default kernel command string"
1228 Provide a set of default command-line options at build time by
1229 entering them here. As a minimum, you should specify the the
1230 root device (e.g. root=/dev/nfs).
1232 config CMDLINE_FORCE
1233 bool "Always use the default kernel command string"
1235 Always use the default kernel command string, even if the boot
1236 loader passes other arguments to the kernel.
1237 This is useful if you cannot or don't want to change the
1238 command-line options your boot loader passes to the kernel.
1244 bool "UEFI runtime support"
1245 depends on OF && !CPU_BIG_ENDIAN
1246 depends on KERNEL_MODE_NEON
1249 select EFI_PARAMS_FROM_FDT
1250 select EFI_RUNTIME_WRAPPERS
1255 This option provides support for runtime services provided
1256 by UEFI firmware (such as non-volatile variables, realtime
1257 clock, and platform reset). A UEFI stub is also provided to
1258 allow the kernel to be booted as an EFI application. This
1259 is only useful on systems that have UEFI firmware.
1262 bool "Enable support for SMBIOS (DMI) tables"
1266 This enables SMBIOS/DMI feature for systems.
1268 This option is only useful on systems that have UEFI firmware.
1269 However, even with this option, the resultant kernel should
1270 continue to boot on existing non-UEFI platforms.
1274 menu "Userspace binary formats"
1276 source "fs/Kconfig.binfmt"
1279 bool "Kernel support for 32-bit EL0"
1280 depends on ARM64_4K_PAGES || EXPERT
1281 select COMPAT_BINFMT_ELF if BINFMT_ELF
1283 select OLD_SIGSUSPEND3
1284 select COMPAT_OLD_SIGACTION
1286 This option enables support for a 32-bit EL0 running under a 64-bit
1287 kernel at EL1. AArch32-specific components such as system calls,
1288 the user helper functions, VFP support and the ptrace interface are
1289 handled appropriately by the kernel.
1291 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
1292 that you will only be able to execute AArch32 binaries that were compiled
1293 with page size aligned segments.
1295 If you want to execute 32-bit userspace applications, say Y.
1297 config SYSVIPC_COMPAT
1299 depends on COMPAT && SYSVIPC
1303 menu "Power management options"
1305 source "kernel/power/Kconfig"
1307 config ARCH_HIBERNATION_POSSIBLE
1311 config ARCH_HIBERNATION_HEADER
1313 depends on HIBERNATION
1315 config ARCH_SUSPEND_POSSIBLE
1320 menu "CPU Power Management"
1322 source "drivers/cpuidle/Kconfig"
1324 source "drivers/cpufreq/Kconfig"
1328 source "net/Kconfig"
1330 source "drivers/Kconfig"
1332 source "drivers/firmware/Kconfig"
1334 source "drivers/acpi/Kconfig"
1338 source "arch/arm64/kvm/Kconfig"
1340 source "arch/arm64/Kconfig.debug"
1342 source "security/Kconfig"
1344 source "crypto/Kconfig"
1346 source "arch/arm64/crypto/Kconfig"
1349 source "lib/Kconfig"