3 select ACPI_CCA_REQUIRED if ACPI
4 select ACPI_GENERIC_GSI if ACPI
5 select ACPI_GTDT if ACPI
6 select ACPI_IORT if ACPI
7 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
8 select ACPI_MCFG if ACPI
9 select ACPI_SPCR_TABLE if ACPI
10 select ACPI_PPTT if ACPI
11 select ARCH_CLOCKSOURCE_DATA
12 select ARCH_HAS_DEBUG_VIRTUAL
13 select ARCH_HAS_DEVMEM_IS_ALLOWED
14 select ARCH_HAS_DMA_COHERENT_TO_PFN
15 select ARCH_HAS_DMA_MMAP_PGPROT
16 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
17 select ARCH_HAS_ELF_RANDOMIZE
18 select ARCH_HAS_FAST_MULTIPLIER
19 select ARCH_HAS_FORTIFY_SOURCE
20 select ARCH_HAS_GCOV_PROFILE_ALL
21 select ARCH_HAS_GIGANTIC_PAGE if (MEMORY_ISOLATION && COMPACTION) || CMA
23 select ARCH_HAS_MEMBARRIER_SYNC_CORE
24 select ARCH_HAS_PTE_SPECIAL
25 select ARCH_HAS_SET_MEMORY
26 select ARCH_HAS_SG_CHAIN
27 select ARCH_HAS_STRICT_KERNEL_RWX
28 select ARCH_HAS_STRICT_MODULE_RWX
29 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
30 select ARCH_HAS_SYNC_DMA_FOR_CPU
31 select ARCH_HAS_SYSCALL_WRAPPER
32 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
33 select ARCH_HAVE_NMI_SAFE_CMPXCHG
34 select ARCH_INLINE_READ_LOCK if !PREEMPT
35 select ARCH_INLINE_READ_LOCK_BH if !PREEMPT
36 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPT
37 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPT
38 select ARCH_INLINE_READ_UNLOCK if !PREEMPT
39 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPT
40 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPT
41 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPT
42 select ARCH_INLINE_WRITE_LOCK if !PREEMPT
43 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPT
44 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPT
45 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPT
46 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPT
47 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPT
48 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPT
49 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPT
50 select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPT
51 select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPT
52 select ARCH_INLINE_SPIN_LOCK if !PREEMPT
53 select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPT
54 select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPT
55 select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPT
56 select ARCH_INLINE_SPIN_UNLOCK if !PREEMPT
57 select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPT
58 select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPT
59 select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPT
60 select ARCH_USE_CMPXCHG_LOCKREF
61 select ARCH_USE_QUEUED_RWLOCKS
62 select ARCH_USE_QUEUED_SPINLOCKS
63 select ARCH_SUPPORTS_MEMORY_FAILURE
64 select ARCH_SUPPORTS_ATOMIC_RMW
65 select ARCH_SUPPORTS_INT128 if GCC_VERSION >= 50000 || CC_IS_CLANG
66 select ARCH_SUPPORTS_NUMA_BALANCING
67 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
68 select ARCH_WANT_FRAME_POINTERS
69 select ARCH_HAS_UBSAN_SANITIZE_ALL
73 select AUDIT_ARCH_COMPAT_GENERIC
74 select ARM_GIC_V2M if PCI
76 select ARM_GIC_V3_ITS if PCI
78 select BUILDTIME_EXTABLE_SORT
79 select CLONE_BACKWARDS
81 select CPU_PM if (SUSPEND || CPU_IDLE)
83 select DCACHE_WORD_ACCESS
87 select GENERIC_ALLOCATOR
88 select GENERIC_ARCH_TOPOLOGY
89 select GENERIC_CLOCKEVENTS
90 select GENERIC_CLOCKEVENTS_BROADCAST
91 select GENERIC_CPU_AUTOPROBE
92 select GENERIC_EARLY_IOREMAP
93 select GENERIC_IDLE_POLL_SETUP
94 select GENERIC_IRQ_MULTI_HANDLER
95 select GENERIC_IRQ_PROBE
96 select GENERIC_IRQ_SHOW
97 select GENERIC_IRQ_SHOW_LEVEL
98 select GENERIC_PCI_IOMAP
99 select GENERIC_SCHED_CLOCK
100 select GENERIC_SMP_IDLE_THREAD
101 select GENERIC_STRNCPY_FROM_USER
102 select GENERIC_STRNLEN_USER
103 select GENERIC_TIME_VSYSCALL
104 select HANDLE_DOMAIN_IRQ
105 select HARDIRQS_SW_RESEND
106 select HAVE_ACPI_APEI if (ACPI && EFI)
107 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
108 select HAVE_ARCH_AUDITSYSCALL
109 select HAVE_ARCH_BITREVERSE
110 select HAVE_ARCH_HUGE_VMAP
111 select HAVE_ARCH_JUMP_LABEL
112 select HAVE_ARCH_JUMP_LABEL_RELATIVE
113 select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
114 select HAVE_ARCH_KGDB
115 select HAVE_ARCH_MMAP_RND_BITS
116 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
117 select HAVE_ARCH_PREL32_RELOCATIONS
118 select HAVE_ARCH_SECCOMP_FILTER
119 select HAVE_ARCH_STACKLEAK
120 select HAVE_ARCH_THREAD_STRUCT_WHITELIST
121 select HAVE_ARCH_TRACEHOOK
122 select HAVE_ARCH_TRANSPARENT_HUGEPAGE
123 select HAVE_ARCH_VMAP_STACK
124 select HAVE_ARM_SMCCC
126 select HAVE_C_RECORDMCOUNT
127 select HAVE_CMPXCHG_DOUBLE
128 select HAVE_CMPXCHG_LOCAL
129 select HAVE_CONTEXT_TRACKING
130 select HAVE_DEBUG_BUGVERBOSE
131 select HAVE_DEBUG_KMEMLEAK
132 select HAVE_DMA_CONTIGUOUS
133 select HAVE_DYNAMIC_FTRACE
134 select HAVE_EFFICIENT_UNALIGNED_ACCESS
135 select HAVE_FTRACE_MCOUNT_RECORD
136 select HAVE_FUNCTION_TRACER
137 select HAVE_FUNCTION_GRAPH_TRACER
138 select HAVE_GCC_PLUGINS
139 select HAVE_GENERIC_DMA_COHERENT
140 select HAVE_HW_BREAKPOINT if PERF_EVENTS
141 select HAVE_IRQ_TIME_ACCOUNTING
142 select HAVE_MEMBLOCK_NODE_MAP if NUMA
144 select HAVE_PATA_PLATFORM
145 select HAVE_PERF_EVENTS
146 select HAVE_PERF_REGS
147 select HAVE_PERF_USER_STACK_DUMP
148 select HAVE_REGS_AND_STACK_ACCESS_API
149 select HAVE_RCU_TABLE_FREE
150 select HAVE_RCU_TABLE_INVALIDATE
152 select HAVE_STACKPROTECTOR
153 select HAVE_SYSCALL_TRACEPOINTS
155 select HAVE_KRETPROBES
156 select IOMMU_DMA if IOMMU_SUPPORT
158 select IRQ_FORCED_THREADING
159 select MODULES_USE_ELF_RELA
160 select MULTI_IRQ_HANDLER
161 select NEED_DMA_MAP_STATE
162 select NEED_SG_DMA_LENGTH
164 select OF_EARLY_FLATTREE
165 select OF_RESERVED_MEM
166 select PCI_ECAM if ACPI
172 select SYSCTL_EXCEPTION_TRACE
173 select THREAD_INFO_IN_TASK
175 ARM 64-bit (AArch64) Linux support.
183 config ARM64_PAGE_SHIFT
185 default 16 if ARM64_64K_PAGES
186 default 14 if ARM64_16K_PAGES
189 config ARM64_CONT_SHIFT
191 default 5 if ARM64_64K_PAGES
192 default 7 if ARM64_16K_PAGES
195 config ARCH_MMAP_RND_BITS_MIN
196 default 14 if ARM64_64K_PAGES
197 default 16 if ARM64_16K_PAGES
200 # max bits determined by the following formula:
201 # VA_BITS - PAGE_SHIFT - 3
202 config ARCH_MMAP_RND_BITS_MAX
203 default 19 if ARM64_VA_BITS=36
204 default 24 if ARM64_VA_BITS=39
205 default 27 if ARM64_VA_BITS=42
206 default 30 if ARM64_VA_BITS=47
207 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
208 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
209 default 33 if ARM64_VA_BITS=48
210 default 14 if ARM64_64K_PAGES
211 default 16 if ARM64_16K_PAGES
214 config ARCH_MMAP_RND_COMPAT_BITS_MIN
215 default 7 if ARM64_64K_PAGES
216 default 9 if ARM64_16K_PAGES
219 config ARCH_MMAP_RND_COMPAT_BITS_MAX
225 config STACKTRACE_SUPPORT
228 config ILLEGAL_POINTER_VALUE
230 default 0xdead000000000000
232 config LOCKDEP_SUPPORT
235 config TRACE_IRQFLAGS_SUPPORT
238 config RWSEM_XCHGADD_ALGORITHM
245 config GENERIC_BUG_RELATIVE_POINTERS
247 depends on GENERIC_BUG
249 config GENERIC_HWEIGHT
255 config GENERIC_CALIBRATE_DELAY
261 config HAVE_GENERIC_GUP
267 config KERNEL_MODE_NEON
270 config FIX_EARLYCON_MEM
273 config PGTABLE_LEVELS
275 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
276 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
277 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
278 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
279 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
280 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
282 config ARCH_SUPPORTS_UPROBES
285 config ARCH_PROC_KCORE_TEXT
288 source "arch/arm64/Kconfig.platforms"
295 This feature enables support for PCI bus system. If you say Y
296 here, the kernel will include drivers and infrastructure code
297 to support PCI bus devices.
302 config PCI_DOMAINS_GENERIC
308 source "drivers/pci/Kconfig"
312 menu "Kernel Features"
314 menu "ARM errata workarounds via the alternatives framework"
316 config ARM64_ERRATUM_826319
317 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
320 This option adds an alternative code sequence to work around ARM
321 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
322 AXI master interface and an L2 cache.
324 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
325 and is unable to accept a certain write via this interface, it will
326 not progress on read data presented on the read data channel and the
329 The workaround promotes data cache clean instructions to
330 data cache clean-and-invalidate.
331 Please note that this does not necessarily enable the workaround,
332 as it depends on the alternative framework, which will only patch
333 the kernel if an affected CPU is detected.
337 config ARM64_ERRATUM_827319
338 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
341 This option adds an alternative code sequence to work around ARM
342 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
343 master interface and an L2 cache.
345 Under certain conditions this erratum can cause a clean line eviction
346 to occur at the same time as another transaction to the same address
347 on the AMBA 5 CHI interface, which can cause data corruption if the
348 interconnect reorders the two transactions.
350 The workaround promotes data cache clean instructions to
351 data cache clean-and-invalidate.
352 Please note that this does not necessarily enable the workaround,
353 as it depends on the alternative framework, which will only patch
354 the kernel if an affected CPU is detected.
358 config ARM64_ERRATUM_824069
359 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
362 This option adds an alternative code sequence to work around ARM
363 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
364 to a coherent interconnect.
366 If a Cortex-A53 processor is executing a store or prefetch for
367 write instruction at the same time as a processor in another
368 cluster is executing a cache maintenance operation to the same
369 address, then this erratum might cause a clean cache line to be
370 incorrectly marked as dirty.
372 The workaround promotes data cache clean instructions to
373 data cache clean-and-invalidate.
374 Please note that this option does not necessarily enable the
375 workaround, as it depends on the alternative framework, which will
376 only patch the kernel if an affected CPU is detected.
380 config ARM64_ERRATUM_819472
381 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
384 This option adds an alternative code sequence to work around ARM
385 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
386 present when it is connected to a coherent interconnect.
388 If the processor is executing a load and store exclusive sequence at
389 the same time as a processor in another cluster is executing a cache
390 maintenance operation to the same address, then this erratum might
391 cause data corruption.
393 The workaround promotes data cache clean instructions to
394 data cache clean-and-invalidate.
395 Please note that this does not necessarily enable the workaround,
396 as it depends on the alternative framework, which will only patch
397 the kernel if an affected CPU is detected.
401 config ARM64_ERRATUM_832075
402 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
405 This option adds an alternative code sequence to work around ARM
406 erratum 832075 on Cortex-A57 parts up to r1p2.
408 Affected Cortex-A57 parts might deadlock when exclusive load/store
409 instructions to Write-Back memory are mixed with Device loads.
411 The workaround is to promote device loads to use Load-Acquire
413 Please note that this does not necessarily enable the workaround,
414 as it depends on the alternative framework, which will only patch
415 the kernel if an affected CPU is detected.
419 config ARM64_ERRATUM_834220
420 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
424 This option adds an alternative code sequence to work around ARM
425 erratum 834220 on Cortex-A57 parts up to r1p2.
427 Affected Cortex-A57 parts might report a Stage 2 translation
428 fault as the result of a Stage 1 fault for load crossing a
429 page boundary when there is a permission or device memory
430 alignment fault at Stage 1 and a translation fault at Stage 2.
432 The workaround is to verify that the Stage 1 translation
433 doesn't generate a fault before handling the Stage 2 fault.
434 Please note that this does not necessarily enable the workaround,
435 as it depends on the alternative framework, which will only patch
436 the kernel if an affected CPU is detected.
440 config ARM64_ERRATUM_845719
441 bool "Cortex-A53: 845719: a load might read incorrect data"
445 This option adds an alternative code sequence to work around ARM
446 erratum 845719 on Cortex-A53 parts up to r0p4.
448 When running a compat (AArch32) userspace on an affected Cortex-A53
449 part, a load at EL0 from a virtual address that matches the bottom 32
450 bits of the virtual address used by a recent load at (AArch64) EL1
451 might return incorrect data.
453 The workaround is to write the contextidr_el1 register on exception
454 return to a 32-bit task.
455 Please note that this does not necessarily enable the workaround,
456 as it depends on the alternative framework, which will only patch
457 the kernel if an affected CPU is detected.
461 config ARM64_ERRATUM_843419
462 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
464 select ARM64_MODULE_PLTS if MODULES
466 This option links the kernel with '--fix-cortex-a53-843419' and
467 enables PLT support to replace certain ADRP instructions, which can
468 cause subsequent memory accesses to use an incorrect address on
469 Cortex-A53 parts up to r0p4.
473 config ARM64_ERRATUM_1024718
474 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update"
477 This option adds work around for Arm Cortex-A55 Erratum 1024718.
479 Affected Cortex-A55 cores (r0p0, r0p1, r1p0) could cause incorrect
480 update of the hardware dirty bit when the DBM/AP bits are updated
481 without a break-before-make. The work around is to disable the usage
482 of hardware DBM locally on the affected cores. CPUs not affected by
483 erratum will continue to use the feature.
487 config ARM64_ERRATUM_1188873
488 bool "Cortex-A76: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result"
490 select ARM_ARCH_TIMER_OOL_WORKAROUND
492 This option adds work arounds for ARM Cortex-A76 erratum 1188873
494 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could cause
495 register corruption when accessing the timer registers from
500 config ARM64_ERRATUM_1165522
501 bool "Cortex-A76: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
504 This option adds work arounds for ARM Cortex-A76 erratum 1165522
506 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with
507 corrupted TLBs by speculating an AT instruction during a guest
512 config CAVIUM_ERRATUM_22375
513 bool "Cavium erratum 22375, 24313"
516 Enable workaround for erratum 22375, 24313.
518 This implements two gicv3-its errata workarounds for ThunderX. Both
519 with small impact affecting only ITS table allocation.
521 erratum 22375: only alloc 8MB table size
522 erratum 24313: ignore memory access type
524 The fixes are in ITS initialization and basically ignore memory access
525 type and table size provided by the TYPER and BASER registers.
529 config CAVIUM_ERRATUM_23144
530 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
534 ITS SYNC command hang for cross node io and collections/cpu mapping.
538 config CAVIUM_ERRATUM_23154
539 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
542 The gicv3 of ThunderX requires a modified version for
543 reading the IAR status to ensure data synchronization
544 (access to icc_iar1_el1 is not sync'ed before and after).
548 config CAVIUM_ERRATUM_27456
549 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
552 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
553 instructions may cause the icache to become corrupted if it
554 contains data for a non-current ASID. The fix is to
555 invalidate the icache when changing the mm context.
559 config CAVIUM_ERRATUM_30115
560 bool "Cavium erratum 30115: Guest may disable interrupts in host"
563 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through
564 1.2, and T83 Pass 1.0, KVM guest execution may disable
565 interrupts in host. Trapping both GICv3 group-0 and group-1
566 accesses sidesteps the issue.
570 config QCOM_FALKOR_ERRATUM_1003
571 bool "Falkor E1003: Incorrect translation due to ASID change"
574 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
575 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID
576 in TTBR1_EL1, this situation only occurs in the entry trampoline and
577 then only for entries in the walk cache, since the leaf translation
578 is unchanged. Work around the erratum by invalidating the walk cache
579 entries for the trampoline before entering the kernel proper.
581 config QCOM_FALKOR_ERRATUM_1009
582 bool "Falkor E1009: Prematurely complete a DSB after a TLBI"
585 On Falkor v1, the CPU may prematurely complete a DSB following a
586 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation
587 one more time to fix the issue.
591 config QCOM_QDF2400_ERRATUM_0065
592 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size"
595 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports
596 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have
597 been indicated as 16Bytes (0xf), not 8Bytes (0x7).
601 config SOCIONEXT_SYNQUACER_PREITS
602 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
605 Socionext Synquacer SoCs implement a separate h/w block to generate
606 MSI doorbell writes with non-zero values for the device ID.
610 config HISILICON_ERRATUM_161600802
611 bool "Hip07 161600802: Erroneous redistributor VLPI base"
614 The HiSilicon Hip07 SoC usees the wrong redistributor base
615 when issued ITS commands such as VMOVP and VMAPP, and requires
616 a 128kB offset to be applied to the target address in this commands.
620 config QCOM_FALKOR_ERRATUM_E1041
621 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access"
624 Falkor CPU may speculatively fetch instructions from an improper
625 memory location when MMU translation is changed from SCTLR_ELn[M]=1
626 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem.
635 default ARM64_4K_PAGES
637 Page size (translation granule) configuration.
639 config ARM64_4K_PAGES
642 This feature enables 4KB pages support.
644 config ARM64_16K_PAGES
647 The system will use 16KB pages support. AArch32 emulation
648 requires applications compiled with 16K (or a multiple of 16K)
651 config ARM64_64K_PAGES
654 This feature enables 64KB pages support (4KB by default)
655 allowing only two levels of page tables and faster TLB
656 look-up. AArch32 emulation requires applications compiled
657 with 64K aligned segments.
662 prompt "Virtual address space size"
663 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
664 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
665 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
667 Allows choosing one of multiple possible virtual address
668 space sizes. The level of translation table is determined by
669 a combination of page size and virtual address space size.
671 config ARM64_VA_BITS_36
672 bool "36-bit" if EXPERT
673 depends on ARM64_16K_PAGES
675 config ARM64_VA_BITS_39
677 depends on ARM64_4K_PAGES
679 config ARM64_VA_BITS_42
681 depends on ARM64_64K_PAGES
683 config ARM64_VA_BITS_47
685 depends on ARM64_16K_PAGES
687 config ARM64_VA_BITS_48
694 default 36 if ARM64_VA_BITS_36
695 default 39 if ARM64_VA_BITS_39
696 default 42 if ARM64_VA_BITS_42
697 default 47 if ARM64_VA_BITS_47
698 default 48 if ARM64_VA_BITS_48
701 prompt "Physical address space size"
702 default ARM64_PA_BITS_48
704 Choose the maximum physical address range that the kernel will
707 config ARM64_PA_BITS_48
710 config ARM64_PA_BITS_52
711 bool "52-bit (ARMv8.2)"
712 depends on ARM64_64K_PAGES
713 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
715 Enable support for a 52-bit physical address space, introduced as
716 part of the ARMv8.2-LPA extension.
718 With this enabled, the kernel will also continue to work on CPUs that
719 do not support ARMv8.2-LPA, but with some added memory overhead (and
720 minor performance overhead).
726 default 48 if ARM64_PA_BITS_48
727 default 52 if ARM64_PA_BITS_52
729 config CPU_BIG_ENDIAN
730 bool "Build big-endian kernel"
732 Say Y if you plan on running a kernel in big-endian mode.
735 bool "Multi-core scheduler support"
737 Multi-core scheduler support improves the CPU scheduler's decision
738 making when dealing with multi-core CPU chips at a cost of slightly
739 increased overhead in some places. If unsure say N here.
742 bool "SMT scheduler support"
744 Improves the CPU scheduler's decision making when dealing with
745 MultiThreading at a cost of slightly increased overhead in some
746 places. If unsure say N here.
749 int "Maximum number of CPUs (2-4096)"
751 # These have to remain sorted largest to smallest
755 bool "Support for hot-pluggable CPUs"
756 select GENERIC_IRQ_MIGRATION
758 Say Y here to experiment with turning CPUs off and on. CPUs
759 can be controlled through /sys/devices/system/cpu.
761 # Common NUMA Features
763 bool "Numa Memory Allocation and Scheduler Support"
764 select ACPI_NUMA if ACPI
767 Enable NUMA (Non Uniform Memory Access) support.
769 The kernel will try to allocate memory used by a CPU on the
770 local memory of the CPU and add some more
771 NUMA awareness to the kernel.
774 int "Maximum NUMA Nodes (as a power of 2)"
777 depends on NEED_MULTIPLE_NODES
779 Specify the maximum number of NUMA Nodes available on the target
780 system. Increases memory reserved to accommodate various tables.
782 config USE_PERCPU_NUMA_NODE_ID
786 config HAVE_SETUP_PER_CPU_AREA
790 config NEED_PER_CPU_EMBED_FIRST_CHUNK
797 source kernel/Kconfig.hz
799 config ARCH_SUPPORTS_DEBUG_PAGEALLOC
802 config ARCH_SPARSEMEM_ENABLE
804 select SPARSEMEM_VMEMMAP_ENABLE
806 config ARCH_SPARSEMEM_DEFAULT
807 def_bool ARCH_SPARSEMEM_ENABLE
809 config ARCH_SELECT_MEMORY_MODEL
810 def_bool ARCH_SPARSEMEM_ENABLE
812 config ARCH_FLATMEM_ENABLE
815 config HAVE_ARCH_PFN_VALID
818 config HW_PERF_EVENTS
822 config SYS_SUPPORTS_HUGETLBFS
825 config ARCH_WANT_HUGE_PMD_SHARE
826 def_bool y if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
828 config ARCH_HAS_CACHE_LINE_SIZE
832 bool "Enable seccomp to safely compute untrusted bytecode"
834 This kernel feature is useful for number crunching applications
835 that may need to compute untrusted bytecode during their
836 execution. By using pipes or other transports made available to
837 the process as file descriptors supporting the read/write
838 syscalls, it's possible to isolate those applications in
839 their own address space using seccomp. Once seccomp is
840 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
841 and the task is only allowed to execute a few safe syscalls
842 defined by each seccomp mode.
845 bool "Enable paravirtualization code"
847 This changes the kernel so it can modify itself when it is run
848 under a hypervisor, potentially improving performance significantly
849 over full virtualization.
851 config PARAVIRT_TIME_ACCOUNTING
852 bool "Paravirtual steal time accounting"
856 Select this option to enable fine granularity task steal time
857 accounting. Time spent executing other tasks in parallel with
858 the current vCPU is discounted from the vCPU power. To account for
859 that, there can be a small performance impact.
861 If in doubt, say N here.
864 depends on PM_SLEEP_SMP
866 bool "kexec system call"
868 kexec is a system call that implements the ability to shutdown your
869 current kernel, and to start another kernel. It is like a reboot
870 but it is independent of the system firmware. And like a reboot
871 you can start any kernel with it, not just Linux.
874 bool "Build kdump crash kernel"
876 Generate crash dump after being started by kexec. This should
877 be normally only set in special crash dump kernels which are
878 loaded in the main kernel with kexec-tools into a specially
879 reserved region and then later executed after a crash by
882 For more details see Documentation/kdump/kdump.txt
889 bool "Xen guest support on ARM64"
890 depends on ARM64 && OF
894 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
896 config FORCE_MAX_ZONEORDER
898 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
899 default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE)
902 The kernel memory allocator divides physically contiguous memory
903 blocks into "zones", where each zone is a power of two number of
904 pages. This option selects the largest power of two that the kernel
905 keeps in the memory allocator. If you need to allocate very large
906 blocks of physically contiguous memory, then you may need to
909 This config option is actually maximum order plus one. For example,
910 a value of 11 means that the largest free memory block is 2^10 pages.
912 We make sure that we can allocate upto a HugePage size for each configuration.
914 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
916 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
917 4M allocations matching the default size used by generic code.
919 config UNMAP_KERNEL_AT_EL0
920 bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT
923 Speculation attacks against some high-performance processors can
924 be used to bypass MMU permission checks and leak kernel data to
925 userspace. This can be defended against by unmapping the kernel
926 when running in userspace, mapping it back in on exception entry
927 via a trampoline page in the vector table.
931 config HARDEN_BRANCH_PREDICTOR
932 bool "Harden the branch predictor against aliasing attacks" if EXPERT
935 Speculation attacks against some high-performance processors rely on
936 being able to manipulate the branch predictor for a victim context by
937 executing aliasing branches in the attacker context. Such attacks
938 can be partially mitigated against by clearing internal branch
939 predictor state and limiting the prediction logic in some situations.
941 This config option will take CPU-specific actions to harden the
942 branch predictor against aliasing attacks and may rely on specific
943 instruction sequences or control bits being set by the system
948 config HARDEN_EL2_VECTORS
949 bool "Harden EL2 vector mapping against system register leak" if EXPERT
952 Speculation attacks against some high-performance processors can
953 be used to leak privileged information such as the vector base
954 register, resulting in a potential defeat of the EL2 layout
957 This config option will map the vectors to a fixed location,
958 independent of the EL2 code mapping, so that revealing VBAR_EL2
959 to an attacker does not give away any extra information. This
960 only gets enabled on affected CPUs.
965 bool "Speculative Store Bypass Disable" if EXPERT
968 This enables mitigation of the bypassing of previous stores
969 by speculative loads.
973 menuconfig ARMV8_DEPRECATED
974 bool "Emulate deprecated/obsolete ARMv8 instructions"
978 Legacy software support may require certain instructions
979 that have been deprecated or obsoleted in the architecture.
981 Enable this config to enable selective emulation of these
989 bool "Emulate SWP/SWPB instructions"
991 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
992 they are always undefined. Say Y here to enable software
993 emulation of these instructions for userspace using LDXR/STXR.
995 In some older versions of glibc [<=2.8] SWP is used during futex
996 trylock() operations with the assumption that the code will not
997 be preempted. This invalid assumption may be more likely to fail
998 with SWP emulation enabled, leading to deadlock of the user
1001 NOTE: when accessing uncached shared regions, LDXR/STXR rely
1002 on an external transaction monitoring block called a global
1003 monitor to maintain update atomicity. If your system does not
1004 implement a global monitor, this option can cause programs that
1005 perform SWP operations to uncached memory to deadlock.
1009 config CP15_BARRIER_EMULATION
1010 bool "Emulate CP15 Barrier instructions"
1012 The CP15 barrier instructions - CP15ISB, CP15DSB, and
1013 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
1014 strongly recommended to use the ISB, DSB, and DMB
1015 instructions instead.
1017 Say Y here to enable software emulation of these
1018 instructions for AArch32 userspace code. When this option is
1019 enabled, CP15 barrier usage is traced which can help
1020 identify software that needs updating.
1024 config SETEND_EMULATION
1025 bool "Emulate SETEND instruction"
1027 The SETEND instruction alters the data-endianness of the
1028 AArch32 EL0, and is deprecated in ARMv8.
1030 Say Y here to enable software emulation of the instruction
1031 for AArch32 userspace code.
1033 Note: All the cpus on the system must have mixed endian support at EL0
1034 for this feature to be enabled. If a new CPU - which doesn't support mixed
1035 endian - is hotplugged in after this feature has been enabled, there could
1036 be unexpected results in the applications.
1041 config ARM64_SW_TTBR0_PAN
1042 bool "Emulate Privileged Access Never using TTBR0_EL1 switching"
1044 Enabling this option prevents the kernel from accessing
1045 user-space memory directly by pointing TTBR0_EL1 to a reserved
1046 zeroed area and reserved ASID. The user access routines
1047 restore the valid TTBR0_EL1 temporarily.
1049 menu "ARMv8.1 architectural features"
1051 config ARM64_HW_AFDBM
1052 bool "Support for hardware updates of the Access and Dirty page flags"
1055 The ARMv8.1 architecture extensions introduce support for
1056 hardware updates of the access and dirty information in page
1057 table entries. When enabled in TCR_EL1 (HA and HD bits) on
1058 capable processors, accesses to pages with PTE_AF cleared will
1059 set this bit instead of raising an access flag fault.
1060 Similarly, writes to read-only pages with the DBM bit set will
1061 clear the read-only bit (AP[2]) instead of raising a
1064 Kernels built with this configuration option enabled continue
1065 to work on pre-ARMv8.1 hardware and the performance impact is
1066 minimal. If unsure, say Y.
1069 bool "Enable support for Privileged Access Never (PAN)"
1072 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
1073 prevents the kernel or hypervisor from accessing user-space (EL0)
1076 Choosing this option will cause any unprotected (not using
1077 copy_to_user et al) memory access to fail with a permission fault.
1079 The feature is detected at runtime, and will remain as a 'nop'
1080 instruction if the cpu does not implement the feature.
1082 config ARM64_LSE_ATOMICS
1083 bool "Atomic instructions"
1086 As part of the Large System Extensions, ARMv8.1 introduces new
1087 atomic instructions that are designed specifically to scale in
1090 Say Y here to make use of these instructions for the in-kernel
1091 atomic routines. This incurs a small overhead on CPUs that do
1092 not support these instructions and requires the kernel to be
1093 built with binutils >= 2.25 in order for the new instructions
1097 bool "Enable support for Virtualization Host Extensions (VHE)"
1100 Virtualization Host Extensions (VHE) allow the kernel to run
1101 directly at EL2 (instead of EL1) on processors that support
1102 it. This leads to better performance for KVM, as they reduce
1103 the cost of the world switch.
1105 Selecting this option allows the VHE feature to be detected
1106 at runtime, and does not affect processors that do not
1107 implement this feature.
1111 menu "ARMv8.2 architectural features"
1114 bool "Enable support for User Access Override (UAO)"
1117 User Access Override (UAO; part of the ARMv8.2 Extensions)
1118 causes the 'unprivileged' variant of the load/store instructions to
1119 be overridden to be privileged.
1121 This option changes get_user() and friends to use the 'unprivileged'
1122 variant of the load/store instructions. This ensures that user-space
1123 really did have access to the supplied memory. When addr_limit is
1124 set to kernel memory the UAO bit will be set, allowing privileged
1125 access to kernel memory.
1127 Choosing this option will cause copy_to_user() et al to use user-space
1130 The feature is detected at runtime, the kernel will use the
1131 regular load/store instructions if the cpu does not implement the
1135 bool "Enable support for persistent memory"
1136 select ARCH_HAS_PMEM_API
1137 select ARCH_HAS_UACCESS_FLUSHCACHE
1139 Say Y to enable support for the persistent memory API based on the
1140 ARMv8.2 DCPoP feature.
1142 The feature is detected at runtime, and the kernel will use DC CVAC
1143 operations if DC CVAP is not supported (following the behaviour of
1144 DC CVAP itself if the system does not define a point of persistence).
1146 config ARM64_RAS_EXTN
1147 bool "Enable support for RAS CPU Extensions"
1150 CPUs that support the Reliability, Availability and Serviceability
1151 (RAS) Extensions, part of ARMv8.2 are able to track faults and
1152 errors, classify them and report them to software.
1154 On CPUs with these extensions system software can use additional
1155 barriers to determine if faults are pending and read the
1156 classification from a new set of registers.
1158 Selecting this feature will allow the kernel to use these barriers
1159 and access the new registers if the system supports the extension.
1160 Platform RAS features may additionally depend on firmware support.
1163 bool "Enable support for Common Not Private (CNP) translations"
1165 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
1167 Common Not Private (CNP) allows translation table entries to
1168 be shared between different PEs in the same inner shareable
1169 domain, so the hardware can use this fact to optimise the
1170 caching of such entries in the TLB.
1172 Selecting this option allows the CNP feature to be detected
1173 at runtime, and does not affect PEs that do not implement
1179 bool "ARM Scalable Vector Extension support"
1181 depends on !KVM || ARM64_VHE
1183 The Scalable Vector Extension (SVE) is an extension to the AArch64
1184 execution state which complements and extends the SIMD functionality
1185 of the base architecture to support much larger vectors and to enable
1186 additional vectorisation opportunities.
1188 To enable use of this extension on CPUs that implement it, say Y.
1190 Note that for architectural reasons, firmware _must_ implement SVE
1191 support when running on SVE capable hardware. The required support
1194 * version 1.5 and later of the ARM Trusted Firmware
1195 * the AArch64 boot wrapper since commit 5e1261e08abf
1196 ("bootwrapper: SVE: Enable SVE for EL2 and below").
1198 For other firmware implementations, consult the firmware documentation
1201 If you need the kernel to boot on SVE-capable hardware with broken
1202 firmware, you may need to say N here until you get your firmware
1203 fixed. Otherwise, you may experience firmware panics or lockups when
1204 booting the kernel. If unsure and you are not observing these
1205 symptoms, you should assume that it is safe to say Y.
1207 CPUs that support SVE are architecturally required to support the
1208 Virtualization Host Extensions (VHE), so the kernel makes no
1209 provision for supporting SVE alongside KVM without VHE enabled.
1210 Thus, you will need to enable CONFIG_ARM64_VHE if you want to support
1211 KVM in the same kernel image.
1213 config ARM64_MODULE_PLTS
1215 select HAVE_MOD_ARCH_SPECIFIC
1220 This builds the kernel as a Position Independent Executable (PIE),
1221 which retains all relocation metadata required to relocate the
1222 kernel binary at runtime to a different virtual address than the
1223 address it was linked at.
1224 Since AArch64 uses the RELA relocation format, this requires a
1225 relocation pass at runtime even if the kernel is loaded at the
1226 same address it was linked at.
1228 config RANDOMIZE_BASE
1229 bool "Randomize the address of the kernel image"
1230 select ARM64_MODULE_PLTS if MODULES
1233 Randomizes the virtual address at which the kernel image is
1234 loaded, as a security feature that deters exploit attempts
1235 relying on knowledge of the location of kernel internals.
1237 It is the bootloader's job to provide entropy, by passing a
1238 random u64 value in /chosen/kaslr-seed at kernel entry.
1240 When booting via the UEFI stub, it will invoke the firmware's
1241 EFI_RNG_PROTOCOL implementation (if available) to supply entropy
1242 to the kernel proper. In addition, it will randomise the physical
1243 location of the kernel Image as well.
1247 config RANDOMIZE_MODULE_REGION_FULL
1248 bool "Randomize the module region over a 4 GB range"
1249 depends on RANDOMIZE_BASE
1252 Randomizes the location of the module region inside a 4 GB window
1253 covering the core kernel. This way, it is less likely for modules
1254 to leak information about the location of core kernel data structures
1255 but it does imply that function calls between modules and the core
1256 kernel will need to be resolved via veneers in the module PLT.
1258 When this option is not set, the module region will be randomized over
1259 a limited range that contains the [_stext, _etext] interval of the
1260 core kernel, so branch relocations are always in range.
1266 config ARM64_ACPI_PARKING_PROTOCOL
1267 bool "Enable support for the ARM64 ACPI parking protocol"
1270 Enable support for the ARM64 ACPI parking protocol. If disabled
1271 the kernel will not allow booting through the ARM64 ACPI parking
1272 protocol even if the corresponding data is present in the ACPI
1276 string "Default kernel command string"
1279 Provide a set of default command-line options at build time by
1280 entering them here. As a minimum, you should specify the the
1281 root device (e.g. root=/dev/nfs).
1283 config CMDLINE_FORCE
1284 bool "Always use the default kernel command string"
1286 Always use the default kernel command string, even if the boot
1287 loader passes other arguments to the kernel.
1288 This is useful if you cannot or don't want to change the
1289 command-line options your boot loader passes to the kernel.
1295 bool "UEFI runtime support"
1296 depends on OF && !CPU_BIG_ENDIAN
1297 depends on KERNEL_MODE_NEON
1298 select ARCH_SUPPORTS_ACPI
1301 select EFI_PARAMS_FROM_FDT
1302 select EFI_RUNTIME_WRAPPERS
1307 This option provides support for runtime services provided
1308 by UEFI firmware (such as non-volatile variables, realtime
1309 clock, and platform reset). A UEFI stub is also provided to
1310 allow the kernel to be booted as an EFI application. This
1311 is only useful on systems that have UEFI firmware.
1314 bool "Enable support for SMBIOS (DMI) tables"
1318 This enables SMBIOS/DMI feature for systems.
1320 This option is only useful on systems that have UEFI firmware.
1321 However, even with this option, the resultant kernel should
1322 continue to boot on existing non-UEFI platforms.
1327 bool "Kernel support for 32-bit EL0"
1328 depends on ARM64_4K_PAGES || EXPERT
1329 select COMPAT_BINFMT_ELF if BINFMT_ELF
1331 select OLD_SIGSUSPEND3
1332 select COMPAT_OLD_SIGACTION
1334 This option enables support for a 32-bit EL0 running under a 64-bit
1335 kernel at EL1. AArch32-specific components such as system calls,
1336 the user helper functions, VFP support and the ptrace interface are
1337 handled appropriately by the kernel.
1339 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
1340 that you will only be able to execute AArch32 binaries that were compiled
1341 with page size aligned segments.
1343 If you want to execute 32-bit userspace applications, say Y.
1345 config SYSVIPC_COMPAT
1347 depends on COMPAT && SYSVIPC
1349 menu "Power management options"
1351 source "kernel/power/Kconfig"
1353 config ARCH_HIBERNATION_POSSIBLE
1357 config ARCH_HIBERNATION_HEADER
1359 depends on HIBERNATION
1361 config ARCH_SUSPEND_POSSIBLE
1366 menu "CPU Power Management"
1368 source "drivers/cpuidle/Kconfig"
1370 source "drivers/cpufreq/Kconfig"
1374 source "drivers/firmware/Kconfig"
1376 source "drivers/acpi/Kconfig"
1378 source "arch/arm64/kvm/Kconfig"
1381 source "arch/arm64/crypto/Kconfig"