3 select ACPI_CCA_REQUIRED if ACPI
4 select ACPI_GENERIC_GSI if ACPI
5 select ACPI_GTDT if ACPI
6 select ACPI_IORT if ACPI
7 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
8 select ACPI_MCFG if ACPI
9 select ACPI_SPCR_TABLE if ACPI
10 select ACPI_PPTT if ACPI
11 select ARCH_CLOCKSOURCE_DATA
12 select ARCH_HAS_DEBUG_VIRTUAL
13 select ARCH_HAS_DEVMEM_IS_ALLOWED
14 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
15 select ARCH_HAS_ELF_RANDOMIZE
16 select ARCH_HAS_FAST_MULTIPLIER
17 select ARCH_HAS_FORTIFY_SOURCE
18 select ARCH_HAS_GCOV_PROFILE_ALL
19 select ARCH_HAS_GIGANTIC_PAGE if (MEMORY_ISOLATION && COMPACTION) || CMA
21 select ARCH_HAS_MEMBARRIER_SYNC_CORE
22 select ARCH_HAS_PTE_SPECIAL
23 select ARCH_HAS_SET_MEMORY
24 select ARCH_HAS_SG_CHAIN
25 select ARCH_HAS_STRICT_KERNEL_RWX
26 select ARCH_HAS_STRICT_MODULE_RWX
27 select ARCH_HAS_SYSCALL_WRAPPER
28 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
29 select ARCH_HAVE_NMI_SAFE_CMPXCHG
30 select ARCH_INLINE_READ_LOCK if !PREEMPT
31 select ARCH_INLINE_READ_LOCK_BH if !PREEMPT
32 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPT
33 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPT
34 select ARCH_INLINE_READ_UNLOCK if !PREEMPT
35 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPT
36 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPT
37 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPT
38 select ARCH_INLINE_WRITE_LOCK if !PREEMPT
39 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPT
40 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPT
41 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPT
42 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPT
43 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPT
44 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPT
45 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPT
46 select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPT
47 select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPT
48 select ARCH_INLINE_SPIN_LOCK if !PREEMPT
49 select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPT
50 select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPT
51 select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPT
52 select ARCH_INLINE_SPIN_UNLOCK if !PREEMPT
53 select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPT
54 select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPT
55 select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPT
56 select ARCH_USE_CMPXCHG_LOCKREF
57 select ARCH_USE_QUEUED_RWLOCKS
58 select ARCH_USE_QUEUED_SPINLOCKS
59 select ARCH_SUPPORTS_MEMORY_FAILURE
60 select ARCH_SUPPORTS_ATOMIC_RMW
61 select ARCH_SUPPORTS_INT128 if GCC_VERSION >= 50000 || CC_IS_CLANG
62 select ARCH_SUPPORTS_NUMA_BALANCING
63 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
64 select ARCH_WANT_FRAME_POINTERS
65 select ARCH_HAS_UBSAN_SANITIZE_ALL
69 select AUDIT_ARCH_COMPAT_GENERIC
70 select ARM_GIC_V2M if PCI
72 select ARM_GIC_V3_ITS if PCI
74 select BUILDTIME_EXTABLE_SORT
75 select CLONE_BACKWARDS
77 select CPU_PM if (SUSPEND || CPU_IDLE)
79 select DCACHE_WORD_ACCESS
83 select GENERIC_ALLOCATOR
84 select GENERIC_ARCH_TOPOLOGY
85 select GENERIC_CLOCKEVENTS
86 select GENERIC_CLOCKEVENTS_BROADCAST
87 select GENERIC_CPU_AUTOPROBE
88 select GENERIC_EARLY_IOREMAP
89 select GENERIC_IDLE_POLL_SETUP
90 select GENERIC_IRQ_MULTI_HANDLER
91 select GENERIC_IRQ_PROBE
92 select GENERIC_IRQ_SHOW
93 select GENERIC_IRQ_SHOW_LEVEL
94 select GENERIC_PCI_IOMAP
95 select GENERIC_SCHED_CLOCK
96 select GENERIC_SMP_IDLE_THREAD
97 select GENERIC_STRNCPY_FROM_USER
98 select GENERIC_STRNLEN_USER
99 select GENERIC_TIME_VSYSCALL
100 select HANDLE_DOMAIN_IRQ
101 select HARDIRQS_SW_RESEND
102 select HAVE_ACPI_APEI if (ACPI && EFI)
103 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
104 select HAVE_ARCH_AUDITSYSCALL
105 select HAVE_ARCH_BITREVERSE
106 select HAVE_ARCH_HUGE_VMAP
107 select HAVE_ARCH_JUMP_LABEL
108 select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
109 select HAVE_ARCH_KGDB
110 select HAVE_ARCH_MMAP_RND_BITS
111 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
112 select HAVE_ARCH_PREL32_RELOCATIONS
113 select HAVE_ARCH_SECCOMP_FILTER
114 select HAVE_ARCH_STACKLEAK
115 select HAVE_ARCH_THREAD_STRUCT_WHITELIST
116 select HAVE_ARCH_TRACEHOOK
117 select HAVE_ARCH_TRANSPARENT_HUGEPAGE
118 select HAVE_ARCH_VMAP_STACK
119 select HAVE_ARM_SMCCC
121 select HAVE_C_RECORDMCOUNT
122 select HAVE_CMPXCHG_DOUBLE
123 select HAVE_CMPXCHG_LOCAL
124 select HAVE_CONTEXT_TRACKING
125 select HAVE_DEBUG_BUGVERBOSE
126 select HAVE_DEBUG_KMEMLEAK
127 select HAVE_DMA_CONTIGUOUS
128 select HAVE_DYNAMIC_FTRACE
129 select HAVE_EFFICIENT_UNALIGNED_ACCESS
130 select HAVE_FTRACE_MCOUNT_RECORD
131 select HAVE_FUNCTION_TRACER
132 select HAVE_FUNCTION_GRAPH_TRACER
133 select HAVE_GCC_PLUGINS
134 select HAVE_GENERIC_DMA_COHERENT
135 select HAVE_HW_BREAKPOINT if PERF_EVENTS
136 select HAVE_IRQ_TIME_ACCOUNTING
138 select HAVE_MEMBLOCK_NODE_MAP if NUMA
140 select HAVE_PATA_PLATFORM
141 select HAVE_PERF_EVENTS
142 select HAVE_PERF_REGS
143 select HAVE_PERF_USER_STACK_DUMP
144 select HAVE_REGS_AND_STACK_ACCESS_API
145 select HAVE_RCU_TABLE_FREE
146 select HAVE_RCU_TABLE_INVALIDATE
148 select HAVE_STACKPROTECTOR
149 select HAVE_SYSCALL_TRACEPOINTS
151 select HAVE_KRETPROBES
152 select IOMMU_DMA if IOMMU_SUPPORT
154 select IRQ_FORCED_THREADING
155 select MODULES_USE_ELF_RELA
156 select MULTI_IRQ_HANDLER
157 select NEED_DMA_MAP_STATE
158 select NEED_SG_DMA_LENGTH
161 select OF_EARLY_FLATTREE
162 select OF_RESERVED_MEM
163 select PCI_ECAM if ACPI
169 select SYSCTL_EXCEPTION_TRACE
170 select THREAD_INFO_IN_TASK
172 ARM 64-bit (AArch64) Linux support.
180 config ARM64_PAGE_SHIFT
182 default 16 if ARM64_64K_PAGES
183 default 14 if ARM64_16K_PAGES
186 config ARM64_CONT_SHIFT
188 default 5 if ARM64_64K_PAGES
189 default 7 if ARM64_16K_PAGES
192 config ARCH_MMAP_RND_BITS_MIN
193 default 14 if ARM64_64K_PAGES
194 default 16 if ARM64_16K_PAGES
197 # max bits determined by the following formula:
198 # VA_BITS - PAGE_SHIFT - 3
199 config ARCH_MMAP_RND_BITS_MAX
200 default 19 if ARM64_VA_BITS=36
201 default 24 if ARM64_VA_BITS=39
202 default 27 if ARM64_VA_BITS=42
203 default 30 if ARM64_VA_BITS=47
204 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
205 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
206 default 33 if ARM64_VA_BITS=48
207 default 14 if ARM64_64K_PAGES
208 default 16 if ARM64_16K_PAGES
211 config ARCH_MMAP_RND_COMPAT_BITS_MIN
212 default 7 if ARM64_64K_PAGES
213 default 9 if ARM64_16K_PAGES
216 config ARCH_MMAP_RND_COMPAT_BITS_MAX
222 config STACKTRACE_SUPPORT
225 config ILLEGAL_POINTER_VALUE
227 default 0xdead000000000000
229 config LOCKDEP_SUPPORT
232 config TRACE_IRQFLAGS_SUPPORT
235 config RWSEM_XCHGADD_ALGORITHM
242 config GENERIC_BUG_RELATIVE_POINTERS
244 depends on GENERIC_BUG
246 config GENERIC_HWEIGHT
252 config GENERIC_CALIBRATE_DELAY
258 config HAVE_GENERIC_GUP
264 config KERNEL_MODE_NEON
267 config FIX_EARLYCON_MEM
270 config PGTABLE_LEVELS
272 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
273 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
274 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
275 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
276 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
277 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
279 config ARCH_SUPPORTS_UPROBES
282 config ARCH_PROC_KCORE_TEXT
285 source "arch/arm64/Kconfig.platforms"
292 This feature enables support for PCI bus system. If you say Y
293 here, the kernel will include drivers and infrastructure code
294 to support PCI bus devices.
299 config PCI_DOMAINS_GENERIC
305 source "drivers/pci/Kconfig"
309 menu "Kernel Features"
311 menu "ARM errata workarounds via the alternatives framework"
313 config ARM64_ERRATUM_826319
314 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
317 This option adds an alternative code sequence to work around ARM
318 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
319 AXI master interface and an L2 cache.
321 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
322 and is unable to accept a certain write via this interface, it will
323 not progress on read data presented on the read data channel and the
326 The workaround promotes data cache clean instructions to
327 data cache clean-and-invalidate.
328 Please note that this does not necessarily enable the workaround,
329 as it depends on the alternative framework, which will only patch
330 the kernel if an affected CPU is detected.
334 config ARM64_ERRATUM_827319
335 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
338 This option adds an alternative code sequence to work around ARM
339 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
340 master interface and an L2 cache.
342 Under certain conditions this erratum can cause a clean line eviction
343 to occur at the same time as another transaction to the same address
344 on the AMBA 5 CHI interface, which can cause data corruption if the
345 interconnect reorders the two transactions.
347 The workaround promotes data cache clean instructions to
348 data cache clean-and-invalidate.
349 Please note that this does not necessarily enable the workaround,
350 as it depends on the alternative framework, which will only patch
351 the kernel if an affected CPU is detected.
355 config ARM64_ERRATUM_824069
356 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
359 This option adds an alternative code sequence to work around ARM
360 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
361 to a coherent interconnect.
363 If a Cortex-A53 processor is executing a store or prefetch for
364 write instruction at the same time as a processor in another
365 cluster is executing a cache maintenance operation to the same
366 address, then this erratum might cause a clean cache line to be
367 incorrectly marked as dirty.
369 The workaround promotes data cache clean instructions to
370 data cache clean-and-invalidate.
371 Please note that this option does not necessarily enable the
372 workaround, as it depends on the alternative framework, which will
373 only patch the kernel if an affected CPU is detected.
377 config ARM64_ERRATUM_819472
378 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
381 This option adds an alternative code sequence to work around ARM
382 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
383 present when it is connected to a coherent interconnect.
385 If the processor is executing a load and store exclusive sequence at
386 the same time as a processor in another cluster is executing a cache
387 maintenance operation to the same address, then this erratum might
388 cause data corruption.
390 The workaround promotes data cache clean instructions to
391 data cache clean-and-invalidate.
392 Please note that this does not necessarily enable the workaround,
393 as it depends on the alternative framework, which will only patch
394 the kernel if an affected CPU is detected.
398 config ARM64_ERRATUM_832075
399 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
402 This option adds an alternative code sequence to work around ARM
403 erratum 832075 on Cortex-A57 parts up to r1p2.
405 Affected Cortex-A57 parts might deadlock when exclusive load/store
406 instructions to Write-Back memory are mixed with Device loads.
408 The workaround is to promote device loads to use Load-Acquire
410 Please note that this does not necessarily enable the workaround,
411 as it depends on the alternative framework, which will only patch
412 the kernel if an affected CPU is detected.
416 config ARM64_ERRATUM_834220
417 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
421 This option adds an alternative code sequence to work around ARM
422 erratum 834220 on Cortex-A57 parts up to r1p2.
424 Affected Cortex-A57 parts might report a Stage 2 translation
425 fault as the result of a Stage 1 fault for load crossing a
426 page boundary when there is a permission or device memory
427 alignment fault at Stage 1 and a translation fault at Stage 2.
429 The workaround is to verify that the Stage 1 translation
430 doesn't generate a fault before handling the Stage 2 fault.
431 Please note that this does not necessarily enable the workaround,
432 as it depends on the alternative framework, which will only patch
433 the kernel if an affected CPU is detected.
437 config ARM64_ERRATUM_845719
438 bool "Cortex-A53: 845719: a load might read incorrect data"
442 This option adds an alternative code sequence to work around ARM
443 erratum 845719 on Cortex-A53 parts up to r0p4.
445 When running a compat (AArch32) userspace on an affected Cortex-A53
446 part, a load at EL0 from a virtual address that matches the bottom 32
447 bits of the virtual address used by a recent load at (AArch64) EL1
448 might return incorrect data.
450 The workaround is to write the contextidr_el1 register on exception
451 return to a 32-bit task.
452 Please note that this does not necessarily enable the workaround,
453 as it depends on the alternative framework, which will only patch
454 the kernel if an affected CPU is detected.
458 config ARM64_ERRATUM_843419
459 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
461 select ARM64_MODULE_PLTS if MODULES
463 This option links the kernel with '--fix-cortex-a53-843419' and
464 enables PLT support to replace certain ADRP instructions, which can
465 cause subsequent memory accesses to use an incorrect address on
466 Cortex-A53 parts up to r0p4.
470 config ARM64_ERRATUM_1024718
471 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update"
474 This option adds work around for Arm Cortex-A55 Erratum 1024718.
476 Affected Cortex-A55 cores (r0p0, r0p1, r1p0) could cause incorrect
477 update of the hardware dirty bit when the DBM/AP bits are updated
478 without a break-before-make. The work around is to disable the usage
479 of hardware DBM locally on the affected cores. CPUs not affected by
480 erratum will continue to use the feature.
484 config ARM64_ERRATUM_1188873
485 bool "Cortex-A76: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result"
487 select ARM_ARCH_TIMER_OOL_WORKAROUND
489 This option adds work arounds for ARM Cortex-A76 erratum 1188873
491 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could cause
492 register corruption when accessing the timer registers from
497 config CAVIUM_ERRATUM_22375
498 bool "Cavium erratum 22375, 24313"
501 Enable workaround for erratum 22375, 24313.
503 This implements two gicv3-its errata workarounds for ThunderX. Both
504 with small impact affecting only ITS table allocation.
506 erratum 22375: only alloc 8MB table size
507 erratum 24313: ignore memory access type
509 The fixes are in ITS initialization and basically ignore memory access
510 type and table size provided by the TYPER and BASER registers.
514 config CAVIUM_ERRATUM_23144
515 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
519 ITS SYNC command hang for cross node io and collections/cpu mapping.
523 config CAVIUM_ERRATUM_23154
524 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
527 The gicv3 of ThunderX requires a modified version for
528 reading the IAR status to ensure data synchronization
529 (access to icc_iar1_el1 is not sync'ed before and after).
533 config CAVIUM_ERRATUM_27456
534 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
537 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
538 instructions may cause the icache to become corrupted if it
539 contains data for a non-current ASID. The fix is to
540 invalidate the icache when changing the mm context.
544 config CAVIUM_ERRATUM_30115
545 bool "Cavium erratum 30115: Guest may disable interrupts in host"
548 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through
549 1.2, and T83 Pass 1.0, KVM guest execution may disable
550 interrupts in host. Trapping both GICv3 group-0 and group-1
551 accesses sidesteps the issue.
555 config QCOM_FALKOR_ERRATUM_1003
556 bool "Falkor E1003: Incorrect translation due to ASID change"
559 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
560 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID
561 in TTBR1_EL1, this situation only occurs in the entry trampoline and
562 then only for entries in the walk cache, since the leaf translation
563 is unchanged. Work around the erratum by invalidating the walk cache
564 entries for the trampoline before entering the kernel proper.
566 config QCOM_FALKOR_ERRATUM_1009
567 bool "Falkor E1009: Prematurely complete a DSB after a TLBI"
570 On Falkor v1, the CPU may prematurely complete a DSB following a
571 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation
572 one more time to fix the issue.
576 config QCOM_QDF2400_ERRATUM_0065
577 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size"
580 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports
581 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have
582 been indicated as 16Bytes (0xf), not 8Bytes (0x7).
586 config SOCIONEXT_SYNQUACER_PREITS
587 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
590 Socionext Synquacer SoCs implement a separate h/w block to generate
591 MSI doorbell writes with non-zero values for the device ID.
595 config HISILICON_ERRATUM_161600802
596 bool "Hip07 161600802: Erroneous redistributor VLPI base"
599 The HiSilicon Hip07 SoC usees the wrong redistributor base
600 when issued ITS commands such as VMOVP and VMAPP, and requires
601 a 128kB offset to be applied to the target address in this commands.
605 config QCOM_FALKOR_ERRATUM_E1041
606 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access"
609 Falkor CPU may speculatively fetch instructions from an improper
610 memory location when MMU translation is changed from SCTLR_ELn[M]=1
611 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem.
620 default ARM64_4K_PAGES
622 Page size (translation granule) configuration.
624 config ARM64_4K_PAGES
627 This feature enables 4KB pages support.
629 config ARM64_16K_PAGES
632 The system will use 16KB pages support. AArch32 emulation
633 requires applications compiled with 16K (or a multiple of 16K)
636 config ARM64_64K_PAGES
639 This feature enables 64KB pages support (4KB by default)
640 allowing only two levels of page tables and faster TLB
641 look-up. AArch32 emulation requires applications compiled
642 with 64K aligned segments.
647 prompt "Virtual address space size"
648 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
649 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
650 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
652 Allows choosing one of multiple possible virtual address
653 space sizes. The level of translation table is determined by
654 a combination of page size and virtual address space size.
656 config ARM64_VA_BITS_36
657 bool "36-bit" if EXPERT
658 depends on ARM64_16K_PAGES
660 config ARM64_VA_BITS_39
662 depends on ARM64_4K_PAGES
664 config ARM64_VA_BITS_42
666 depends on ARM64_64K_PAGES
668 config ARM64_VA_BITS_47
670 depends on ARM64_16K_PAGES
672 config ARM64_VA_BITS_48
679 default 36 if ARM64_VA_BITS_36
680 default 39 if ARM64_VA_BITS_39
681 default 42 if ARM64_VA_BITS_42
682 default 47 if ARM64_VA_BITS_47
683 default 48 if ARM64_VA_BITS_48
686 prompt "Physical address space size"
687 default ARM64_PA_BITS_48
689 Choose the maximum physical address range that the kernel will
692 config ARM64_PA_BITS_48
695 config ARM64_PA_BITS_52
696 bool "52-bit (ARMv8.2)"
697 depends on ARM64_64K_PAGES
698 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
700 Enable support for a 52-bit physical address space, introduced as
701 part of the ARMv8.2-LPA extension.
703 With this enabled, the kernel will also continue to work on CPUs that
704 do not support ARMv8.2-LPA, but with some added memory overhead (and
705 minor performance overhead).
711 default 48 if ARM64_PA_BITS_48
712 default 52 if ARM64_PA_BITS_52
714 config CPU_BIG_ENDIAN
715 bool "Build big-endian kernel"
717 Say Y if you plan on running a kernel in big-endian mode.
720 bool "Multi-core scheduler support"
722 Multi-core scheduler support improves the CPU scheduler's decision
723 making when dealing with multi-core CPU chips at a cost of slightly
724 increased overhead in some places. If unsure say N here.
727 bool "SMT scheduler support"
729 Improves the CPU scheduler's decision making when dealing with
730 MultiThreading at a cost of slightly increased overhead in some
731 places. If unsure say N here.
734 int "Maximum number of CPUs (2-4096)"
736 # These have to remain sorted largest to smallest
740 bool "Support for hot-pluggable CPUs"
741 select GENERIC_IRQ_MIGRATION
743 Say Y here to experiment with turning CPUs off and on. CPUs
744 can be controlled through /sys/devices/system/cpu.
746 # Common NUMA Features
748 bool "Numa Memory Allocation and Scheduler Support"
749 select ACPI_NUMA if ACPI
752 Enable NUMA (Non Uniform Memory Access) support.
754 The kernel will try to allocate memory used by a CPU on the
755 local memory of the CPU and add some more
756 NUMA awareness to the kernel.
759 int "Maximum NUMA Nodes (as a power of 2)"
762 depends on NEED_MULTIPLE_NODES
764 Specify the maximum number of NUMA Nodes available on the target
765 system. Increases memory reserved to accommodate various tables.
767 config USE_PERCPU_NUMA_NODE_ID
771 config HAVE_SETUP_PER_CPU_AREA
775 config NEED_PER_CPU_EMBED_FIRST_CHUNK
782 source kernel/Kconfig.hz
784 config ARCH_SUPPORTS_DEBUG_PAGEALLOC
787 config ARCH_SPARSEMEM_ENABLE
789 select SPARSEMEM_VMEMMAP_ENABLE
791 config ARCH_SPARSEMEM_DEFAULT
792 def_bool ARCH_SPARSEMEM_ENABLE
794 config ARCH_SELECT_MEMORY_MODEL
795 def_bool ARCH_SPARSEMEM_ENABLE
797 config ARCH_FLATMEM_ENABLE
800 config HAVE_ARCH_PFN_VALID
803 config HW_PERF_EVENTS
807 config SYS_SUPPORTS_HUGETLBFS
810 config ARCH_WANT_HUGE_PMD_SHARE
811 def_bool y if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
813 config ARCH_HAS_CACHE_LINE_SIZE
817 bool "Enable seccomp to safely compute untrusted bytecode"
819 This kernel feature is useful for number crunching applications
820 that may need to compute untrusted bytecode during their
821 execution. By using pipes or other transports made available to
822 the process as file descriptors supporting the read/write
823 syscalls, it's possible to isolate those applications in
824 their own address space using seccomp. Once seccomp is
825 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
826 and the task is only allowed to execute a few safe syscalls
827 defined by each seccomp mode.
830 bool "Enable paravirtualization code"
832 This changes the kernel so it can modify itself when it is run
833 under a hypervisor, potentially improving performance significantly
834 over full virtualization.
836 config PARAVIRT_TIME_ACCOUNTING
837 bool "Paravirtual steal time accounting"
841 Select this option to enable fine granularity task steal time
842 accounting. Time spent executing other tasks in parallel with
843 the current vCPU is discounted from the vCPU power. To account for
844 that, there can be a small performance impact.
846 If in doubt, say N here.
849 depends on PM_SLEEP_SMP
851 bool "kexec system call"
853 kexec is a system call that implements the ability to shutdown your
854 current kernel, and to start another kernel. It is like a reboot
855 but it is independent of the system firmware. And like a reboot
856 you can start any kernel with it, not just Linux.
859 bool "Build kdump crash kernel"
861 Generate crash dump after being started by kexec. This should
862 be normally only set in special crash dump kernels which are
863 loaded in the main kernel with kexec-tools into a specially
864 reserved region and then later executed after a crash by
867 For more details see Documentation/kdump/kdump.txt
874 bool "Xen guest support on ARM64"
875 depends on ARM64 && OF
879 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
881 config FORCE_MAX_ZONEORDER
883 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
884 default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE)
887 The kernel memory allocator divides physically contiguous memory
888 blocks into "zones", where each zone is a power of two number of
889 pages. This option selects the largest power of two that the kernel
890 keeps in the memory allocator. If you need to allocate very large
891 blocks of physically contiguous memory, then you may need to
894 This config option is actually maximum order plus one. For example,
895 a value of 11 means that the largest free memory block is 2^10 pages.
897 We make sure that we can allocate upto a HugePage size for each configuration.
899 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
901 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
902 4M allocations matching the default size used by generic code.
904 config UNMAP_KERNEL_AT_EL0
905 bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT
908 Speculation attacks against some high-performance processors can
909 be used to bypass MMU permission checks and leak kernel data to
910 userspace. This can be defended against by unmapping the kernel
911 when running in userspace, mapping it back in on exception entry
912 via a trampoline page in the vector table.
916 config HARDEN_BRANCH_PREDICTOR
917 bool "Harden the branch predictor against aliasing attacks" if EXPERT
920 Speculation attacks against some high-performance processors rely on
921 being able to manipulate the branch predictor for a victim context by
922 executing aliasing branches in the attacker context. Such attacks
923 can be partially mitigated against by clearing internal branch
924 predictor state and limiting the prediction logic in some situations.
926 This config option will take CPU-specific actions to harden the
927 branch predictor against aliasing attacks and may rely on specific
928 instruction sequences or control bits being set by the system
933 config HARDEN_EL2_VECTORS
934 bool "Harden EL2 vector mapping against system register leak" if EXPERT
937 Speculation attacks against some high-performance processors can
938 be used to leak privileged information such as the vector base
939 register, resulting in a potential defeat of the EL2 layout
942 This config option will map the vectors to a fixed location,
943 independent of the EL2 code mapping, so that revealing VBAR_EL2
944 to an attacker does not give away any extra information. This
945 only gets enabled on affected CPUs.
950 bool "Speculative Store Bypass Disable" if EXPERT
953 This enables mitigation of the bypassing of previous stores
954 by speculative loads.
958 menuconfig ARMV8_DEPRECATED
959 bool "Emulate deprecated/obsolete ARMv8 instructions"
963 Legacy software support may require certain instructions
964 that have been deprecated or obsoleted in the architecture.
966 Enable this config to enable selective emulation of these
974 bool "Emulate SWP/SWPB instructions"
976 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
977 they are always undefined. Say Y here to enable software
978 emulation of these instructions for userspace using LDXR/STXR.
980 In some older versions of glibc [<=2.8] SWP is used during futex
981 trylock() operations with the assumption that the code will not
982 be preempted. This invalid assumption may be more likely to fail
983 with SWP emulation enabled, leading to deadlock of the user
986 NOTE: when accessing uncached shared regions, LDXR/STXR rely
987 on an external transaction monitoring block called a global
988 monitor to maintain update atomicity. If your system does not
989 implement a global monitor, this option can cause programs that
990 perform SWP operations to uncached memory to deadlock.
994 config CP15_BARRIER_EMULATION
995 bool "Emulate CP15 Barrier instructions"
997 The CP15 barrier instructions - CP15ISB, CP15DSB, and
998 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
999 strongly recommended to use the ISB, DSB, and DMB
1000 instructions instead.
1002 Say Y here to enable software emulation of these
1003 instructions for AArch32 userspace code. When this option is
1004 enabled, CP15 barrier usage is traced which can help
1005 identify software that needs updating.
1009 config SETEND_EMULATION
1010 bool "Emulate SETEND instruction"
1012 The SETEND instruction alters the data-endianness of the
1013 AArch32 EL0, and is deprecated in ARMv8.
1015 Say Y here to enable software emulation of the instruction
1016 for AArch32 userspace code.
1018 Note: All the cpus on the system must have mixed endian support at EL0
1019 for this feature to be enabled. If a new CPU - which doesn't support mixed
1020 endian - is hotplugged in after this feature has been enabled, there could
1021 be unexpected results in the applications.
1026 config ARM64_SW_TTBR0_PAN
1027 bool "Emulate Privileged Access Never using TTBR0_EL1 switching"
1029 Enabling this option prevents the kernel from accessing
1030 user-space memory directly by pointing TTBR0_EL1 to a reserved
1031 zeroed area and reserved ASID. The user access routines
1032 restore the valid TTBR0_EL1 temporarily.
1034 menu "ARMv8.1 architectural features"
1036 config ARM64_HW_AFDBM
1037 bool "Support for hardware updates of the Access and Dirty page flags"
1040 The ARMv8.1 architecture extensions introduce support for
1041 hardware updates of the access and dirty information in page
1042 table entries. When enabled in TCR_EL1 (HA and HD bits) on
1043 capable processors, accesses to pages with PTE_AF cleared will
1044 set this bit instead of raising an access flag fault.
1045 Similarly, writes to read-only pages with the DBM bit set will
1046 clear the read-only bit (AP[2]) instead of raising a
1049 Kernels built with this configuration option enabled continue
1050 to work on pre-ARMv8.1 hardware and the performance impact is
1051 minimal. If unsure, say Y.
1054 bool "Enable support for Privileged Access Never (PAN)"
1057 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
1058 prevents the kernel or hypervisor from accessing user-space (EL0)
1061 Choosing this option will cause any unprotected (not using
1062 copy_to_user et al) memory access to fail with a permission fault.
1064 The feature is detected at runtime, and will remain as a 'nop'
1065 instruction if the cpu does not implement the feature.
1067 config ARM64_LSE_ATOMICS
1068 bool "Atomic instructions"
1071 As part of the Large System Extensions, ARMv8.1 introduces new
1072 atomic instructions that are designed specifically to scale in
1075 Say Y here to make use of these instructions for the in-kernel
1076 atomic routines. This incurs a small overhead on CPUs that do
1077 not support these instructions and requires the kernel to be
1078 built with binutils >= 2.25 in order for the new instructions
1082 bool "Enable support for Virtualization Host Extensions (VHE)"
1085 Virtualization Host Extensions (VHE) allow the kernel to run
1086 directly at EL2 (instead of EL1) on processors that support
1087 it. This leads to better performance for KVM, as they reduce
1088 the cost of the world switch.
1090 Selecting this option allows the VHE feature to be detected
1091 at runtime, and does not affect processors that do not
1092 implement this feature.
1096 menu "ARMv8.2 architectural features"
1099 bool "Enable support for User Access Override (UAO)"
1102 User Access Override (UAO; part of the ARMv8.2 Extensions)
1103 causes the 'unprivileged' variant of the load/store instructions to
1104 be overridden to be privileged.
1106 This option changes get_user() and friends to use the 'unprivileged'
1107 variant of the load/store instructions. This ensures that user-space
1108 really did have access to the supplied memory. When addr_limit is
1109 set to kernel memory the UAO bit will be set, allowing privileged
1110 access to kernel memory.
1112 Choosing this option will cause copy_to_user() et al to use user-space
1115 The feature is detected at runtime, the kernel will use the
1116 regular load/store instructions if the cpu does not implement the
1120 bool "Enable support for persistent memory"
1121 select ARCH_HAS_PMEM_API
1122 select ARCH_HAS_UACCESS_FLUSHCACHE
1124 Say Y to enable support for the persistent memory API based on the
1125 ARMv8.2 DCPoP feature.
1127 The feature is detected at runtime, and the kernel will use DC CVAC
1128 operations if DC CVAP is not supported (following the behaviour of
1129 DC CVAP itself if the system does not define a point of persistence).
1131 config ARM64_RAS_EXTN
1132 bool "Enable support for RAS CPU Extensions"
1135 CPUs that support the Reliability, Availability and Serviceability
1136 (RAS) Extensions, part of ARMv8.2 are able to track faults and
1137 errors, classify them and report them to software.
1139 On CPUs with these extensions system software can use additional
1140 barriers to determine if faults are pending and read the
1141 classification from a new set of registers.
1143 Selecting this feature will allow the kernel to use these barriers
1144 and access the new registers if the system supports the extension.
1145 Platform RAS features may additionally depend on firmware support.
1148 bool "Enable support for Common Not Private (CNP) translations"
1150 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
1152 Common Not Private (CNP) allows translation table entries to
1153 be shared between different PEs in the same inner shareable
1154 domain, so the hardware can use this fact to optimise the
1155 caching of such entries in the TLB.
1157 Selecting this option allows the CNP feature to be detected
1158 at runtime, and does not affect PEs that do not implement
1164 bool "ARM Scalable Vector Extension support"
1166 depends on !KVM || ARM64_VHE
1168 The Scalable Vector Extension (SVE) is an extension to the AArch64
1169 execution state which complements and extends the SIMD functionality
1170 of the base architecture to support much larger vectors and to enable
1171 additional vectorisation opportunities.
1173 To enable use of this extension on CPUs that implement it, say Y.
1175 Note that for architectural reasons, firmware _must_ implement SVE
1176 support when running on SVE capable hardware. The required support
1179 * version 1.5 and later of the ARM Trusted Firmware
1180 * the AArch64 boot wrapper since commit 5e1261e08abf
1181 ("bootwrapper: SVE: Enable SVE for EL2 and below").
1183 For other firmware implementations, consult the firmware documentation
1186 If you need the kernel to boot on SVE-capable hardware with broken
1187 firmware, you may need to say N here until you get your firmware
1188 fixed. Otherwise, you may experience firmware panics or lockups when
1189 booting the kernel. If unsure and you are not observing these
1190 symptoms, you should assume that it is safe to say Y.
1192 CPUs that support SVE are architecturally required to support the
1193 Virtualization Host Extensions (VHE), so the kernel makes no
1194 provision for supporting SVE alongside KVM without VHE enabled.
1195 Thus, you will need to enable CONFIG_ARM64_VHE if you want to support
1196 KVM in the same kernel image.
1198 config ARM64_MODULE_PLTS
1200 select HAVE_MOD_ARCH_SPECIFIC
1205 This builds the kernel as a Position Independent Executable (PIE),
1206 which retains all relocation metadata required to relocate the
1207 kernel binary at runtime to a different virtual address than the
1208 address it was linked at.
1209 Since AArch64 uses the RELA relocation format, this requires a
1210 relocation pass at runtime even if the kernel is loaded at the
1211 same address it was linked at.
1213 config RANDOMIZE_BASE
1214 bool "Randomize the address of the kernel image"
1215 select ARM64_MODULE_PLTS if MODULES
1218 Randomizes the virtual address at which the kernel image is
1219 loaded, as a security feature that deters exploit attempts
1220 relying on knowledge of the location of kernel internals.
1222 It is the bootloader's job to provide entropy, by passing a
1223 random u64 value in /chosen/kaslr-seed at kernel entry.
1225 When booting via the UEFI stub, it will invoke the firmware's
1226 EFI_RNG_PROTOCOL implementation (if available) to supply entropy
1227 to the kernel proper. In addition, it will randomise the physical
1228 location of the kernel Image as well.
1232 config RANDOMIZE_MODULE_REGION_FULL
1233 bool "Randomize the module region over a 4 GB range"
1234 depends on RANDOMIZE_BASE
1237 Randomizes the location of the module region inside a 4 GB window
1238 covering the core kernel. This way, it is less likely for modules
1239 to leak information about the location of core kernel data structures
1240 but it does imply that function calls between modules and the core
1241 kernel will need to be resolved via veneers in the module PLT.
1243 When this option is not set, the module region will be randomized over
1244 a limited range that contains the [_stext, _etext] interval of the
1245 core kernel, so branch relocations are always in range.
1251 config ARM64_ACPI_PARKING_PROTOCOL
1252 bool "Enable support for the ARM64 ACPI parking protocol"
1255 Enable support for the ARM64 ACPI parking protocol. If disabled
1256 the kernel will not allow booting through the ARM64 ACPI parking
1257 protocol even if the corresponding data is present in the ACPI
1261 string "Default kernel command string"
1264 Provide a set of default command-line options at build time by
1265 entering them here. As a minimum, you should specify the the
1266 root device (e.g. root=/dev/nfs).
1268 config CMDLINE_FORCE
1269 bool "Always use the default kernel command string"
1271 Always use the default kernel command string, even if the boot
1272 loader passes other arguments to the kernel.
1273 This is useful if you cannot or don't want to change the
1274 command-line options your boot loader passes to the kernel.
1280 bool "UEFI runtime support"
1281 depends on OF && !CPU_BIG_ENDIAN
1282 depends on KERNEL_MODE_NEON
1283 select ARCH_SUPPORTS_ACPI
1286 select EFI_PARAMS_FROM_FDT
1287 select EFI_RUNTIME_WRAPPERS
1292 This option provides support for runtime services provided
1293 by UEFI firmware (such as non-volatile variables, realtime
1294 clock, and platform reset). A UEFI stub is also provided to
1295 allow the kernel to be booted as an EFI application. This
1296 is only useful on systems that have UEFI firmware.
1299 bool "Enable support for SMBIOS (DMI) tables"
1303 This enables SMBIOS/DMI feature for systems.
1305 This option is only useful on systems that have UEFI firmware.
1306 However, even with this option, the resultant kernel should
1307 continue to boot on existing non-UEFI platforms.
1312 bool "Kernel support for 32-bit EL0"
1313 depends on ARM64_4K_PAGES || EXPERT
1314 select COMPAT_BINFMT_ELF if BINFMT_ELF
1316 select OLD_SIGSUSPEND3
1317 select COMPAT_OLD_SIGACTION
1319 This option enables support for a 32-bit EL0 running under a 64-bit
1320 kernel at EL1. AArch32-specific components such as system calls,
1321 the user helper functions, VFP support and the ptrace interface are
1322 handled appropriately by the kernel.
1324 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
1325 that you will only be able to execute AArch32 binaries that were compiled
1326 with page size aligned segments.
1328 If you want to execute 32-bit userspace applications, say Y.
1330 config SYSVIPC_COMPAT
1332 depends on COMPAT && SYSVIPC
1334 menu "Power management options"
1336 source "kernel/power/Kconfig"
1338 config ARCH_HIBERNATION_POSSIBLE
1342 config ARCH_HIBERNATION_HEADER
1344 depends on HIBERNATION
1346 config ARCH_SUSPEND_POSSIBLE
1351 menu "CPU Power Management"
1353 source "drivers/cpuidle/Kconfig"
1355 source "drivers/cpufreq/Kconfig"
1359 source "drivers/firmware/Kconfig"
1361 source "drivers/acpi/Kconfig"
1363 source "arch/arm64/kvm/Kconfig"
1366 source "arch/arm64/crypto/Kconfig"