1 # SPDX-License-Identifier: GPL-2.0-only
4 select ACPI_CCA_REQUIRED if ACPI
5 select ACPI_GENERIC_GSI if ACPI
6 select ACPI_GTDT if ACPI
7 select ACPI_IORT if ACPI
8 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
9 select ACPI_MCFG if (ACPI && PCI)
10 select ACPI_SPCR_TABLE if ACPI
11 select ACPI_PPTT if ACPI
12 select ARCH_CLOCKSOURCE_DATA
13 select ARCH_HAS_DEBUG_VIRTUAL
14 select ARCH_HAS_DEVMEM_IS_ALLOWED
15 select ARCH_HAS_DMA_COHERENT_TO_PFN
16 select ARCH_HAS_DMA_MMAP_PGPROT
17 select ARCH_HAS_DMA_PREP_COHERENT
18 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
19 select ARCH_HAS_ELF_RANDOMIZE
20 select ARCH_HAS_FAST_MULTIPLIER
21 select ARCH_HAS_FORTIFY_SOURCE
22 select ARCH_HAS_GCOV_PROFILE_ALL
23 select ARCH_HAS_GIGANTIC_PAGE
25 select ARCH_HAS_KEEPINITRD
26 select ARCH_HAS_MEMBARRIER_SYNC_CORE
27 select ARCH_HAS_PTE_DEVMAP
28 select ARCH_HAS_PTE_SPECIAL
29 select ARCH_HAS_SETUP_DMA_OPS
30 select ARCH_HAS_SET_DIRECT_MAP
31 select ARCH_HAS_SET_MEMORY
32 select ARCH_HAS_STRICT_KERNEL_RWX
33 select ARCH_HAS_STRICT_MODULE_RWX
34 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
35 select ARCH_HAS_SYNC_DMA_FOR_CPU
36 select ARCH_HAS_SYSCALL_WRAPPER
37 select ARCH_HAS_TEARDOWN_DMA_OPS if IOMMU_SUPPORT
38 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
39 select ARCH_HAVE_NMI_SAFE_CMPXCHG
40 select ARCH_INLINE_READ_LOCK if !PREEMPT
41 select ARCH_INLINE_READ_LOCK_BH if !PREEMPT
42 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPT
43 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPT
44 select ARCH_INLINE_READ_UNLOCK if !PREEMPT
45 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPT
46 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPT
47 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPT
48 select ARCH_INLINE_WRITE_LOCK if !PREEMPT
49 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPT
50 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPT
51 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPT
52 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPT
53 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPT
54 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPT
55 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPT
56 select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPT
57 select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPT
58 select ARCH_INLINE_SPIN_LOCK if !PREEMPT
59 select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPT
60 select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPT
61 select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPT
62 select ARCH_INLINE_SPIN_UNLOCK if !PREEMPT
63 select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPT
64 select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPT
65 select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPT
66 select ARCH_KEEP_MEMBLOCK
67 select ARCH_USE_CMPXCHG_LOCKREF
68 select ARCH_USE_QUEUED_RWLOCKS
69 select ARCH_USE_QUEUED_SPINLOCKS
70 select ARCH_SUPPORTS_MEMORY_FAILURE
71 select ARCH_SUPPORTS_ATOMIC_RMW
72 select ARCH_SUPPORTS_INT128 if GCC_VERSION >= 50000 || CC_IS_CLANG
73 select ARCH_SUPPORTS_NUMA_BALANCING
74 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT
75 select ARCH_WANT_FRAME_POINTERS
76 select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
77 select ARCH_HAS_UBSAN_SANITIZE_ALL
81 select AUDIT_ARCH_COMPAT_GENERIC
82 select ARM_GIC_V2M if PCI
84 select ARM_GIC_V3_ITS if PCI
86 select BUILDTIME_EXTABLE_SORT
87 select CLONE_BACKWARDS
89 select CPU_PM if (SUSPEND || CPU_IDLE)
91 select DCACHE_WORD_ACCESS
92 select DMA_DIRECT_REMAP
95 select GENERIC_ALLOCATOR
96 select GENERIC_ARCH_TOPOLOGY
97 select GENERIC_CLOCKEVENTS
98 select GENERIC_CLOCKEVENTS_BROADCAST
99 select GENERIC_CPU_AUTOPROBE
100 select GENERIC_CPU_VULNERABILITIES
101 select GENERIC_EARLY_IOREMAP
102 select GENERIC_IDLE_POLL_SETUP
103 select GENERIC_IRQ_MULTI_HANDLER
104 select GENERIC_IRQ_PROBE
105 select GENERIC_IRQ_SHOW
106 select GENERIC_IRQ_SHOW_LEVEL
107 select GENERIC_PCI_IOMAP
108 select GENERIC_SCHED_CLOCK
109 select GENERIC_SMP_IDLE_THREAD
110 select GENERIC_STRNCPY_FROM_USER
111 select GENERIC_STRNLEN_USER
112 select GENERIC_TIME_VSYSCALL
113 select GENERIC_GETTIMEOFDAY
114 select GENERIC_COMPAT_VDSO if (!CPU_BIG_ENDIAN && COMPAT)
115 select HANDLE_DOMAIN_IRQ
116 select HARDIRQS_SW_RESEND
118 select HAVE_ACPI_APEI if (ACPI && EFI)
119 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
120 select HAVE_ARCH_AUDITSYSCALL
121 select HAVE_ARCH_BITREVERSE
122 select HAVE_ARCH_HUGE_VMAP
123 select HAVE_ARCH_JUMP_LABEL
124 select HAVE_ARCH_JUMP_LABEL_RELATIVE
125 select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
126 select HAVE_ARCH_KASAN_SW_TAGS if HAVE_ARCH_KASAN
127 select HAVE_ARCH_KGDB
128 select HAVE_ARCH_MMAP_RND_BITS
129 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
130 select HAVE_ARCH_PREL32_RELOCATIONS
131 select HAVE_ARCH_SECCOMP_FILTER
132 select HAVE_ARCH_STACKLEAK
133 select HAVE_ARCH_THREAD_STRUCT_WHITELIST
134 select HAVE_ARCH_TRACEHOOK
135 select HAVE_ARCH_TRANSPARENT_HUGEPAGE
136 select HAVE_ARCH_VMAP_STACK
137 select HAVE_ARM_SMCCC
139 select HAVE_C_RECORDMCOUNT
140 select HAVE_CMPXCHG_DOUBLE
141 select HAVE_CMPXCHG_LOCAL
142 select HAVE_CONTEXT_TRACKING
143 select HAVE_DEBUG_BUGVERBOSE
144 select HAVE_DEBUG_KMEMLEAK
145 select HAVE_DMA_CONTIGUOUS
146 select HAVE_DYNAMIC_FTRACE
147 select HAVE_EFFICIENT_UNALIGNED_ACCESS
149 select HAVE_FTRACE_MCOUNT_RECORD
150 select HAVE_FUNCTION_TRACER
151 select HAVE_FUNCTION_ERROR_INJECTION
152 select HAVE_FUNCTION_GRAPH_TRACER
153 select HAVE_GCC_PLUGINS
154 select HAVE_HW_BREAKPOINT if PERF_EVENTS
155 select HAVE_IRQ_TIME_ACCOUNTING
156 select HAVE_MEMBLOCK_NODE_MAP if NUMA
158 select HAVE_PATA_PLATFORM
159 select HAVE_PERF_EVENTS
160 select HAVE_PERF_REGS
161 select HAVE_PERF_USER_STACK_DUMP
162 select HAVE_REGS_AND_STACK_ACCESS_API
163 select HAVE_FUNCTION_ARG_ACCESS_API
164 select HAVE_RCU_TABLE_FREE
166 select HAVE_STACKPROTECTOR
167 select HAVE_SYSCALL_TRACEPOINTS
169 select HAVE_KRETPROBES
170 select HAVE_GENERIC_VDSO
171 select IOMMU_DMA if IOMMU_SUPPORT
173 select IRQ_FORCED_THREADING
174 select MODULES_USE_ELF_RELA
175 select NEED_DMA_MAP_STATE
176 select NEED_SG_DMA_LENGTH
178 select OF_EARLY_FLATTREE
179 select PCI_DOMAINS_GENERIC if PCI
180 select PCI_ECAM if (ACPI && PCI)
181 select PCI_SYSCALL if PCI
187 select SYSCTL_EXCEPTION_TRACE
188 select THREAD_INFO_IN_TASK
190 ARM 64-bit (AArch64) Linux support.
198 config ARM64_PAGE_SHIFT
200 default 16 if ARM64_64K_PAGES
201 default 14 if ARM64_16K_PAGES
204 config ARM64_CONT_SHIFT
206 default 5 if ARM64_64K_PAGES
207 default 7 if ARM64_16K_PAGES
210 config ARCH_MMAP_RND_BITS_MIN
211 default 14 if ARM64_64K_PAGES
212 default 16 if ARM64_16K_PAGES
215 # max bits determined by the following formula:
216 # VA_BITS - PAGE_SHIFT - 3
217 config ARCH_MMAP_RND_BITS_MAX
218 default 19 if ARM64_VA_BITS=36
219 default 24 if ARM64_VA_BITS=39
220 default 27 if ARM64_VA_BITS=42
221 default 30 if ARM64_VA_BITS=47
222 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
223 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
224 default 33 if ARM64_VA_BITS=48
225 default 14 if ARM64_64K_PAGES
226 default 16 if ARM64_16K_PAGES
229 config ARCH_MMAP_RND_COMPAT_BITS_MIN
230 default 7 if ARM64_64K_PAGES
231 default 9 if ARM64_16K_PAGES
234 config ARCH_MMAP_RND_COMPAT_BITS_MAX
240 config STACKTRACE_SUPPORT
243 config ILLEGAL_POINTER_VALUE
245 default 0xdead000000000000
247 config LOCKDEP_SUPPORT
250 config TRACE_IRQFLAGS_SUPPORT
257 config GENERIC_BUG_RELATIVE_POINTERS
259 depends on GENERIC_BUG
261 config GENERIC_HWEIGHT
267 config GENERIC_CALIBRATE_DELAY
271 bool "Support DMA32 zone" if EXPERT
274 config ARCH_ENABLE_MEMORY_HOTPLUG
280 config KERNEL_MODE_NEON
283 config FIX_EARLYCON_MEM
286 config PGTABLE_LEVELS
288 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
289 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
290 default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_USER_VA_BITS_52)
291 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
292 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
293 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
295 config ARCH_SUPPORTS_UPROBES
298 config ARCH_PROC_KCORE_TEXT
301 source "arch/arm64/Kconfig.platforms"
303 menu "Kernel Features"
305 menu "ARM errata workarounds via the alternatives framework"
307 config ARM64_WORKAROUND_CLEAN_CACHE
310 config ARM64_ERRATUM_826319
311 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
313 select ARM64_WORKAROUND_CLEAN_CACHE
315 This option adds an alternative code sequence to work around ARM
316 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
317 AXI master interface and an L2 cache.
319 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
320 and is unable to accept a certain write via this interface, it will
321 not progress on read data presented on the read data channel and the
324 The workaround promotes data cache clean instructions to
325 data cache clean-and-invalidate.
326 Please note that this does not necessarily enable the workaround,
327 as it depends on the alternative framework, which will only patch
328 the kernel if an affected CPU is detected.
332 config ARM64_ERRATUM_827319
333 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
335 select ARM64_WORKAROUND_CLEAN_CACHE
337 This option adds an alternative code sequence to work around ARM
338 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
339 master interface and an L2 cache.
341 Under certain conditions this erratum can cause a clean line eviction
342 to occur at the same time as another transaction to the same address
343 on the AMBA 5 CHI interface, which can cause data corruption if the
344 interconnect reorders the two transactions.
346 The workaround promotes data cache clean instructions to
347 data cache clean-and-invalidate.
348 Please note that this does not necessarily enable the workaround,
349 as it depends on the alternative framework, which will only patch
350 the kernel if an affected CPU is detected.
354 config ARM64_ERRATUM_824069
355 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
357 select ARM64_WORKAROUND_CLEAN_CACHE
359 This option adds an alternative code sequence to work around ARM
360 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
361 to a coherent interconnect.
363 If a Cortex-A53 processor is executing a store or prefetch for
364 write instruction at the same time as a processor in another
365 cluster is executing a cache maintenance operation to the same
366 address, then this erratum might cause a clean cache line to be
367 incorrectly marked as dirty.
369 The workaround promotes data cache clean instructions to
370 data cache clean-and-invalidate.
371 Please note that this option does not necessarily enable the
372 workaround, as it depends on the alternative framework, which will
373 only patch the kernel if an affected CPU is detected.
377 config ARM64_ERRATUM_819472
378 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
380 select ARM64_WORKAROUND_CLEAN_CACHE
382 This option adds an alternative code sequence to work around ARM
383 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
384 present when it is connected to a coherent interconnect.
386 If the processor is executing a load and store exclusive sequence at
387 the same time as a processor in another cluster is executing a cache
388 maintenance operation to the same address, then this erratum might
389 cause data corruption.
391 The workaround promotes data cache clean instructions to
392 data cache clean-and-invalidate.
393 Please note that this does not necessarily enable the workaround,
394 as it depends on the alternative framework, which will only patch
395 the kernel if an affected CPU is detected.
399 config ARM64_ERRATUM_832075
400 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
403 This option adds an alternative code sequence to work around ARM
404 erratum 832075 on Cortex-A57 parts up to r1p2.
406 Affected Cortex-A57 parts might deadlock when exclusive load/store
407 instructions to Write-Back memory are mixed with Device loads.
409 The workaround is to promote device loads to use Load-Acquire
411 Please note that this does not necessarily enable the workaround,
412 as it depends on the alternative framework, which will only patch
413 the kernel if an affected CPU is detected.
417 config ARM64_ERRATUM_834220
418 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
422 This option adds an alternative code sequence to work around ARM
423 erratum 834220 on Cortex-A57 parts up to r1p2.
425 Affected Cortex-A57 parts might report a Stage 2 translation
426 fault as the result of a Stage 1 fault for load crossing a
427 page boundary when there is a permission or device memory
428 alignment fault at Stage 1 and a translation fault at Stage 2.
430 The workaround is to verify that the Stage 1 translation
431 doesn't generate a fault before handling the Stage 2 fault.
432 Please note that this does not necessarily enable the workaround,
433 as it depends on the alternative framework, which will only patch
434 the kernel if an affected CPU is detected.
438 config ARM64_ERRATUM_845719
439 bool "Cortex-A53: 845719: a load might read incorrect data"
443 This option adds an alternative code sequence to work around ARM
444 erratum 845719 on Cortex-A53 parts up to r0p4.
446 When running a compat (AArch32) userspace on an affected Cortex-A53
447 part, a load at EL0 from a virtual address that matches the bottom 32
448 bits of the virtual address used by a recent load at (AArch64) EL1
449 might return incorrect data.
451 The workaround is to write the contextidr_el1 register on exception
452 return to a 32-bit task.
453 Please note that this does not necessarily enable the workaround,
454 as it depends on the alternative framework, which will only patch
455 the kernel if an affected CPU is detected.
459 config ARM64_ERRATUM_843419
460 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
462 select ARM64_MODULE_PLTS if MODULES
464 This option links the kernel with '--fix-cortex-a53-843419' and
465 enables PLT support to replace certain ADRP instructions, which can
466 cause subsequent memory accesses to use an incorrect address on
467 Cortex-A53 parts up to r0p4.
471 config ARM64_ERRATUM_1024718
472 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update"
475 This option adds a workaround for ARM Cortex-A55 Erratum 1024718.
477 Affected Cortex-A55 cores (r0p0, r0p1, r1p0) could cause incorrect
478 update of the hardware dirty bit when the DBM/AP bits are updated
479 without a break-before-make. The workaround is to disable the usage
480 of hardware DBM locally on the affected cores. CPUs not affected by
481 this erratum will continue to use the feature.
485 config ARM64_ERRATUM_1418040
486 bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result"
490 This option adds a workaround for ARM Cortex-A76/Neoverse-N1
491 errata 1188873 and 1418040.
493 Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could
494 cause register corruption when accessing the timer registers
495 from AArch32 userspace.
499 config ARM64_ERRATUM_1165522
500 bool "Cortex-A76: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
503 This option adds a workaround for ARM Cortex-A76 erratum 1165522.
505 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with
506 corrupted TLBs by speculating an AT instruction during a guest
511 config ARM64_ERRATUM_1286807
512 bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation"
514 select ARM64_WORKAROUND_REPEAT_TLBI
516 This option adds a workaround for ARM Cortex-A76 erratum 1286807.
518 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual
519 address for a cacheable mapping of a location is being
520 accessed by a core while another core is remapping the virtual
521 address to a new physical page using the recommended
522 break-before-make sequence, then under very rare circumstances
523 TLBI+DSB completes before a read using the translation being
524 invalidated has been observed by other observers. The
525 workaround repeats the TLBI+DSB operation.
529 config ARM64_ERRATUM_1463225
530 bool "Cortex-A76: Software Step might prevent interrupt recognition"
533 This option adds a workaround for Arm Cortex-A76 erratum 1463225.
535 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping
536 of a system call instruction (SVC) can prevent recognition of
537 subsequent interrupts when software stepping is disabled in the
538 exception handler of the system call and either kernel debugging
539 is enabled or VHE is in use.
541 Work around the erratum by triggering a dummy step exception
542 when handling a system call from a task that is being stepped
543 in a VHE configuration of the kernel.
547 config CAVIUM_ERRATUM_22375
548 bool "Cavium erratum 22375, 24313"
551 Enable workaround for errata 22375 and 24313.
553 This implements two gicv3-its errata workarounds for ThunderX. Both
554 with a small impact affecting only ITS table allocation.
556 erratum 22375: only alloc 8MB table size
557 erratum 24313: ignore memory access type
559 The fixes are in ITS initialization and basically ignore memory access
560 type and table size provided by the TYPER and BASER registers.
564 config CAVIUM_ERRATUM_23144
565 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
569 ITS SYNC command hang for cross node io and collections/cpu mapping.
573 config CAVIUM_ERRATUM_23154
574 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
577 The gicv3 of ThunderX requires a modified version for
578 reading the IAR status to ensure data synchronization
579 (access to icc_iar1_el1 is not sync'ed before and after).
583 config CAVIUM_ERRATUM_27456
584 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
587 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
588 instructions may cause the icache to become corrupted if it
589 contains data for a non-current ASID. The fix is to
590 invalidate the icache when changing the mm context.
594 config CAVIUM_ERRATUM_30115
595 bool "Cavium erratum 30115: Guest may disable interrupts in host"
598 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through
599 1.2, and T83 Pass 1.0, KVM guest execution may disable
600 interrupts in host. Trapping both GICv3 group-0 and group-1
601 accesses sidesteps the issue.
605 config QCOM_FALKOR_ERRATUM_1003
606 bool "Falkor E1003: Incorrect translation due to ASID change"
609 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
610 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID
611 in TTBR1_EL1, this situation only occurs in the entry trampoline and
612 then only for entries in the walk cache, since the leaf translation
613 is unchanged. Work around the erratum by invalidating the walk cache
614 entries for the trampoline before entering the kernel proper.
616 config ARM64_WORKAROUND_REPEAT_TLBI
619 config QCOM_FALKOR_ERRATUM_1009
620 bool "Falkor E1009: Prematurely complete a DSB after a TLBI"
622 select ARM64_WORKAROUND_REPEAT_TLBI
624 On Falkor v1, the CPU may prematurely complete a DSB following a
625 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation
626 one more time to fix the issue.
630 config QCOM_QDF2400_ERRATUM_0065
631 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size"
634 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports
635 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have
636 been indicated as 16Bytes (0xf), not 8Bytes (0x7).
640 config SOCIONEXT_SYNQUACER_PREITS
641 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
644 Socionext Synquacer SoCs implement a separate h/w block to generate
645 MSI doorbell writes with non-zero values for the device ID.
649 config HISILICON_ERRATUM_161600802
650 bool "Hip07 161600802: Erroneous redistributor VLPI base"
653 The HiSilicon Hip07 SoC uses the wrong redistributor base
654 when issued ITS commands such as VMOVP and VMAPP, and requires
655 a 128kB offset to be applied to the target address in this commands.
659 config QCOM_FALKOR_ERRATUM_E1041
660 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access"
663 Falkor CPU may speculatively fetch instructions from an improper
664 memory location when MMU translation is changed from SCTLR_ELn[M]=1
665 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem.
669 config FUJITSU_ERRATUM_010001
670 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly"
673 This option adds a workaround for Fujitsu-A64FX erratum E#010001.
674 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory
675 accesses may cause undefined fault (Data abort, DFSC=0b111111).
676 This fault occurs under a specific hardware condition when a
677 load/store instruction performs an address translation using:
678 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1.
679 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1.
680 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1.
681 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1.
683 The workaround is to ensure these bits are clear in TCR_ELx.
684 The workaround only affects the Fujitsu-A64FX.
693 default ARM64_4K_PAGES
695 Page size (translation granule) configuration.
697 config ARM64_4K_PAGES
700 This feature enables 4KB pages support.
702 config ARM64_16K_PAGES
705 The system will use 16KB pages support. AArch32 emulation
706 requires applications compiled with 16K (or a multiple of 16K)
709 config ARM64_64K_PAGES
712 This feature enables 64KB pages support (4KB by default)
713 allowing only two levels of page tables and faster TLB
714 look-up. AArch32 emulation requires applications compiled
715 with 64K aligned segments.
720 prompt "Virtual address space size"
721 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
722 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
723 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
725 Allows choosing one of multiple possible virtual address
726 space sizes. The level of translation table is determined by
727 a combination of page size and virtual address space size.
729 config ARM64_VA_BITS_36
730 bool "36-bit" if EXPERT
731 depends on ARM64_16K_PAGES
733 config ARM64_VA_BITS_39
735 depends on ARM64_4K_PAGES
737 config ARM64_VA_BITS_42
739 depends on ARM64_64K_PAGES
741 config ARM64_VA_BITS_47
743 depends on ARM64_16K_PAGES
745 config ARM64_VA_BITS_48
748 config ARM64_USER_VA_BITS_52
750 depends on ARM64_64K_PAGES && (ARM64_PAN || !ARM64_SW_TTBR0_PAN)
752 Enable 52-bit virtual addressing for userspace when explicitly
753 requested via a hint to mmap(). The kernel will continue to
754 use 48-bit virtual addresses for its own mappings.
756 NOTE: Enabling 52-bit virtual addressing in conjunction with
757 ARMv8.3 Pointer Authentication will result in the PAC being
758 reduced from 7 bits to 3 bits, which may have a significant
759 impact on its susceptibility to brute-force attacks.
761 If unsure, select 48-bit virtual addressing instead.
765 config ARM64_FORCE_52BIT
766 bool "Force 52-bit virtual addresses for userspace"
767 depends on ARM64_USER_VA_BITS_52 && EXPERT
769 For systems with 52-bit userspace VAs enabled, the kernel will attempt
770 to maintain compatibility with older software by providing 48-bit VAs
771 unless a hint is supplied to mmap.
773 This configuration option disables the 48-bit compatibility logic, and
774 forces all userspace addresses to be 52-bit on HW that supports it. One
775 should only enable this configuration option for stress testing userspace
776 memory management code. If unsure say N here.
780 default 36 if ARM64_VA_BITS_36
781 default 39 if ARM64_VA_BITS_39
782 default 42 if ARM64_VA_BITS_42
783 default 47 if ARM64_VA_BITS_47
784 default 48 if ARM64_VA_BITS_48 || ARM64_USER_VA_BITS_52
787 prompt "Physical address space size"
788 default ARM64_PA_BITS_48
790 Choose the maximum physical address range that the kernel will
793 config ARM64_PA_BITS_48
796 config ARM64_PA_BITS_52
797 bool "52-bit (ARMv8.2)"
798 depends on ARM64_64K_PAGES
799 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
801 Enable support for a 52-bit physical address space, introduced as
802 part of the ARMv8.2-LPA extension.
804 With this enabled, the kernel will also continue to work on CPUs that
805 do not support ARMv8.2-LPA, but with some added memory overhead (and
806 minor performance overhead).
812 default 48 if ARM64_PA_BITS_48
813 default 52 if ARM64_PA_BITS_52
815 config CPU_BIG_ENDIAN
816 bool "Build big-endian kernel"
818 Say Y if you plan on running a kernel in big-endian mode.
821 bool "Multi-core scheduler support"
823 Multi-core scheduler support improves the CPU scheduler's decision
824 making when dealing with multi-core CPU chips at a cost of slightly
825 increased overhead in some places. If unsure say N here.
828 bool "SMT scheduler support"
830 Improves the CPU scheduler's decision making when dealing with
831 MultiThreading at a cost of slightly increased overhead in some
832 places. If unsure say N here.
835 int "Maximum number of CPUs (2-4096)"
840 bool "Support for hot-pluggable CPUs"
841 select GENERIC_IRQ_MIGRATION
843 Say Y here to experiment with turning CPUs off and on. CPUs
844 can be controlled through /sys/devices/system/cpu.
846 # Common NUMA Features
848 bool "Numa Memory Allocation and Scheduler Support"
849 select ACPI_NUMA if ACPI
852 Enable NUMA (Non Uniform Memory Access) support.
854 The kernel will try to allocate memory used by a CPU on the
855 local memory of the CPU and add some more
856 NUMA awareness to the kernel.
859 int "Maximum NUMA Nodes (as a power of 2)"
862 depends on NEED_MULTIPLE_NODES
864 Specify the maximum number of NUMA Nodes available on the target
865 system. Increases memory reserved to accommodate various tables.
867 config USE_PERCPU_NUMA_NODE_ID
871 config HAVE_SETUP_PER_CPU_AREA
875 config NEED_PER_CPU_EMBED_FIRST_CHUNK
882 source "kernel/Kconfig.hz"
884 config ARCH_SUPPORTS_DEBUG_PAGEALLOC
887 config ARCH_SPARSEMEM_ENABLE
889 select SPARSEMEM_VMEMMAP_ENABLE
891 config ARCH_SPARSEMEM_DEFAULT
892 def_bool ARCH_SPARSEMEM_ENABLE
894 config ARCH_SELECT_MEMORY_MODEL
895 def_bool ARCH_SPARSEMEM_ENABLE
897 config ARCH_FLATMEM_ENABLE
900 config HAVE_ARCH_PFN_VALID
903 config HW_PERF_EVENTS
907 config SYS_SUPPORTS_HUGETLBFS
910 config ARCH_WANT_HUGE_PMD_SHARE
912 config ARCH_HAS_CACHE_LINE_SIZE
915 config ARCH_ENABLE_SPLIT_PMD_PTLOCK
916 def_bool y if PGTABLE_LEVELS > 2
919 bool "Enable seccomp to safely compute untrusted bytecode"
921 This kernel feature is useful for number crunching applications
922 that may need to compute untrusted bytecode during their
923 execution. By using pipes or other transports made available to
924 the process as file descriptors supporting the read/write
925 syscalls, it's possible to isolate those applications in
926 their own address space using seccomp. Once seccomp is
927 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
928 and the task is only allowed to execute a few safe syscalls
929 defined by each seccomp mode.
932 bool "Enable paravirtualization code"
934 This changes the kernel so it can modify itself when it is run
935 under a hypervisor, potentially improving performance significantly
936 over full virtualization.
938 config PARAVIRT_TIME_ACCOUNTING
939 bool "Paravirtual steal time accounting"
942 Select this option to enable fine granularity task steal time
943 accounting. Time spent executing other tasks in parallel with
944 the current vCPU is discounted from the vCPU power. To account for
945 that, there can be a small performance impact.
947 If in doubt, say N here.
950 depends on PM_SLEEP_SMP
952 bool "kexec system call"
954 kexec is a system call that implements the ability to shutdown your
955 current kernel, and to start another kernel. It is like a reboot
956 but it is independent of the system firmware. And like a reboot
957 you can start any kernel with it, not just Linux.
960 bool "kexec file based system call"
963 This is new version of kexec system call. This system call is
964 file based and takes file descriptors as system call argument
965 for kernel and initramfs as opposed to list of segments as
966 accepted by previous system call.
968 config KEXEC_VERIFY_SIG
969 bool "Verify kernel signature during kexec_file_load() syscall"
970 depends on KEXEC_FILE
972 Select this option to verify a signature with loaded kernel
973 image. If configured, any attempt of loading a image without
974 valid signature will fail.
976 In addition to that option, you need to enable signature
977 verification for the corresponding kernel image type being
978 loaded in order for this to work.
980 config KEXEC_IMAGE_VERIFY_SIG
981 bool "Enable Image signature verification support"
983 depends on KEXEC_VERIFY_SIG
984 depends on EFI && SIGNED_PE_FILE_VERIFICATION
986 Enable Image signature verification support.
988 comment "Support for PE file signature verification disabled"
989 depends on KEXEC_VERIFY_SIG
990 depends on !EFI || !SIGNED_PE_FILE_VERIFICATION
993 bool "Build kdump crash kernel"
995 Generate crash dump after being started by kexec. This should
996 be normally only set in special crash dump kernels which are
997 loaded in the main kernel with kexec-tools into a specially
998 reserved region and then later executed after a crash by
1001 For more details see Documentation/admin-guide/kdump/kdump.rst
1008 bool "Xen guest support on ARM64"
1009 depends on ARM64 && OF
1013 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
1015 config FORCE_MAX_ZONEORDER
1017 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
1018 default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE)
1021 The kernel memory allocator divides physically contiguous memory
1022 blocks into "zones", where each zone is a power of two number of
1023 pages. This option selects the largest power of two that the kernel
1024 keeps in the memory allocator. If you need to allocate very large
1025 blocks of physically contiguous memory, then you may need to
1026 increase this value.
1028 This config option is actually maximum order plus one. For example,
1029 a value of 11 means that the largest free memory block is 2^10 pages.
1031 We make sure that we can allocate upto a HugePage size for each configuration.
1033 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
1035 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
1036 4M allocations matching the default size used by generic code.
1038 config UNMAP_KERNEL_AT_EL0
1039 bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT
1042 Speculation attacks against some high-performance processors can
1043 be used to bypass MMU permission checks and leak kernel data to
1044 userspace. This can be defended against by unmapping the kernel
1045 when running in userspace, mapping it back in on exception entry
1046 via a trampoline page in the vector table.
1050 config HARDEN_BRANCH_PREDICTOR
1051 bool "Harden the branch predictor against aliasing attacks" if EXPERT
1054 Speculation attacks against some high-performance processors rely on
1055 being able to manipulate the branch predictor for a victim context by
1056 executing aliasing branches in the attacker context. Such attacks
1057 can be partially mitigated against by clearing internal branch
1058 predictor state and limiting the prediction logic in some situations.
1060 This config option will take CPU-specific actions to harden the
1061 branch predictor against aliasing attacks and may rely on specific
1062 instruction sequences or control bits being set by the system
1067 config HARDEN_EL2_VECTORS
1068 bool "Harden EL2 vector mapping against system register leak" if EXPERT
1071 Speculation attacks against some high-performance processors can
1072 be used to leak privileged information such as the vector base
1073 register, resulting in a potential defeat of the EL2 layout
1076 This config option will map the vectors to a fixed location,
1077 independent of the EL2 code mapping, so that revealing VBAR_EL2
1078 to an attacker does not give away any extra information. This
1079 only gets enabled on affected CPUs.
1084 bool "Speculative Store Bypass Disable" if EXPERT
1087 This enables mitigation of the bypassing of previous stores
1088 by speculative loads.
1092 config RODATA_FULL_DEFAULT_ENABLED
1093 bool "Apply r/o permissions of VM areas also to their linear aliases"
1096 Apply read-only attributes of VM areas to the linear alias of
1097 the backing pages as well. This prevents code or read-only data
1098 from being modified (inadvertently or intentionally) via another
1099 mapping of the same memory page. This additional enhancement can
1100 be turned off at runtime by passing rodata=[off|on] (and turned on
1101 with rodata=full if this option is set to 'n')
1103 This requires the linear region to be mapped down to pages,
1104 which may adversely affect performance in some cases.
1106 config ARM64_SW_TTBR0_PAN
1107 bool "Emulate Privileged Access Never using TTBR0_EL1 switching"
1109 Enabling this option prevents the kernel from accessing
1110 user-space memory directly by pointing TTBR0_EL1 to a reserved
1111 zeroed area and reserved ASID. The user access routines
1112 restore the valid TTBR0_EL1 temporarily.
1115 bool "Kernel support for 32-bit EL0"
1116 depends on ARM64_4K_PAGES || EXPERT
1117 select COMPAT_BINFMT_ELF if BINFMT_ELF
1119 select OLD_SIGSUSPEND3
1120 select COMPAT_OLD_SIGACTION
1122 This option enables support for a 32-bit EL0 running under a 64-bit
1123 kernel at EL1. AArch32-specific components such as system calls,
1124 the user helper functions, VFP support and the ptrace interface are
1125 handled appropriately by the kernel.
1127 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
1128 that you will only be able to execute AArch32 binaries that were compiled
1129 with page size aligned segments.
1131 If you want to execute 32-bit userspace applications, say Y.
1135 config KUSER_HELPERS
1136 bool "Enable kuser helpers page for 32 bit applications"
1139 Warning: disabling this option may break 32-bit user programs.
1141 Provide kuser helpers to compat tasks. The kernel provides
1142 helper code to userspace in read only form at a fixed location
1143 to allow userspace to be independent of the CPU type fitted to
1144 the system. This permits binaries to be run on ARMv4 through
1145 to ARMv8 without modification.
1147 See Documentation/arm/kernel_user_helpers.rst for details.
1149 However, the fixed address nature of these helpers can be used
1150 by ROP (return orientated programming) authors when creating
1153 If all of the binaries and libraries which run on your platform
1154 are built specifically for your platform, and make no use of
1155 these helpers, then you can turn this option off to hinder
1156 such exploits. However, in that case, if a binary or library
1157 relying on those helpers is run, it will not function correctly.
1159 Say N here only if you are absolutely certain that you do not
1160 need these helpers; otherwise, the safe option is to say Y.
1163 menuconfig ARMV8_DEPRECATED
1164 bool "Emulate deprecated/obsolete ARMv8 instructions"
1167 Legacy software support may require certain instructions
1168 that have been deprecated or obsoleted in the architecture.
1170 Enable this config to enable selective emulation of these
1177 config SWP_EMULATION
1178 bool "Emulate SWP/SWPB instructions"
1180 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
1181 they are always undefined. Say Y here to enable software
1182 emulation of these instructions for userspace using LDXR/STXR.
1184 In some older versions of glibc [<=2.8] SWP is used during futex
1185 trylock() operations with the assumption that the code will not
1186 be preempted. This invalid assumption may be more likely to fail
1187 with SWP emulation enabled, leading to deadlock of the user
1190 NOTE: when accessing uncached shared regions, LDXR/STXR rely
1191 on an external transaction monitoring block called a global
1192 monitor to maintain update atomicity. If your system does not
1193 implement a global monitor, this option can cause programs that
1194 perform SWP operations to uncached memory to deadlock.
1198 config CP15_BARRIER_EMULATION
1199 bool "Emulate CP15 Barrier instructions"
1201 The CP15 barrier instructions - CP15ISB, CP15DSB, and
1202 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
1203 strongly recommended to use the ISB, DSB, and DMB
1204 instructions instead.
1206 Say Y here to enable software emulation of these
1207 instructions for AArch32 userspace code. When this option is
1208 enabled, CP15 barrier usage is traced which can help
1209 identify software that needs updating.
1213 config SETEND_EMULATION
1214 bool "Emulate SETEND instruction"
1216 The SETEND instruction alters the data-endianness of the
1217 AArch32 EL0, and is deprecated in ARMv8.
1219 Say Y here to enable software emulation of the instruction
1220 for AArch32 userspace code.
1222 Note: All the cpus on the system must have mixed endian support at EL0
1223 for this feature to be enabled. If a new CPU - which doesn't support mixed
1224 endian - is hotplugged in after this feature has been enabled, there could
1225 be unexpected results in the applications.
1232 menu "ARMv8.1 architectural features"
1234 config ARM64_HW_AFDBM
1235 bool "Support for hardware updates of the Access and Dirty page flags"
1238 The ARMv8.1 architecture extensions introduce support for
1239 hardware updates of the access and dirty information in page
1240 table entries. When enabled in TCR_EL1 (HA and HD bits) on
1241 capable processors, accesses to pages with PTE_AF cleared will
1242 set this bit instead of raising an access flag fault.
1243 Similarly, writes to read-only pages with the DBM bit set will
1244 clear the read-only bit (AP[2]) instead of raising a
1247 Kernels built with this configuration option enabled continue
1248 to work on pre-ARMv8.1 hardware and the performance impact is
1249 minimal. If unsure, say Y.
1252 bool "Enable support for Privileged Access Never (PAN)"
1255 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
1256 prevents the kernel or hypervisor from accessing user-space (EL0)
1259 Choosing this option will cause any unprotected (not using
1260 copy_to_user et al) memory access to fail with a permission fault.
1262 The feature is detected at runtime, and will remain as a 'nop'
1263 instruction if the cpu does not implement the feature.
1265 config ARM64_LSE_ATOMICS
1266 bool "Atomic instructions"
1269 As part of the Large System Extensions, ARMv8.1 introduces new
1270 atomic instructions that are designed specifically to scale in
1273 Say Y here to make use of these instructions for the in-kernel
1274 atomic routines. This incurs a small overhead on CPUs that do
1275 not support these instructions and requires the kernel to be
1276 built with binutils >= 2.25 in order for the new instructions
1280 bool "Enable support for Virtualization Host Extensions (VHE)"
1283 Virtualization Host Extensions (VHE) allow the kernel to run
1284 directly at EL2 (instead of EL1) on processors that support
1285 it. This leads to better performance for KVM, as they reduce
1286 the cost of the world switch.
1288 Selecting this option allows the VHE feature to be detected
1289 at runtime, and does not affect processors that do not
1290 implement this feature.
1294 menu "ARMv8.2 architectural features"
1297 bool "Enable support for User Access Override (UAO)"
1300 User Access Override (UAO; part of the ARMv8.2 Extensions)
1301 causes the 'unprivileged' variant of the load/store instructions to
1302 be overridden to be privileged.
1304 This option changes get_user() and friends to use the 'unprivileged'
1305 variant of the load/store instructions. This ensures that user-space
1306 really did have access to the supplied memory. When addr_limit is
1307 set to kernel memory the UAO bit will be set, allowing privileged
1308 access to kernel memory.
1310 Choosing this option will cause copy_to_user() et al to use user-space
1313 The feature is detected at runtime, the kernel will use the
1314 regular load/store instructions if the cpu does not implement the
1318 bool "Enable support for persistent memory"
1319 select ARCH_HAS_PMEM_API
1320 select ARCH_HAS_UACCESS_FLUSHCACHE
1322 Say Y to enable support for the persistent memory API based on the
1323 ARMv8.2 DCPoP feature.
1325 The feature is detected at runtime, and the kernel will use DC CVAC
1326 operations if DC CVAP is not supported (following the behaviour of
1327 DC CVAP itself if the system does not define a point of persistence).
1329 config ARM64_RAS_EXTN
1330 bool "Enable support for RAS CPU Extensions"
1333 CPUs that support the Reliability, Availability and Serviceability
1334 (RAS) Extensions, part of ARMv8.2 are able to track faults and
1335 errors, classify them and report them to software.
1337 On CPUs with these extensions system software can use additional
1338 barriers to determine if faults are pending and read the
1339 classification from a new set of registers.
1341 Selecting this feature will allow the kernel to use these barriers
1342 and access the new registers if the system supports the extension.
1343 Platform RAS features may additionally depend on firmware support.
1346 bool "Enable support for Common Not Private (CNP) translations"
1348 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
1350 Common Not Private (CNP) allows translation table entries to
1351 be shared between different PEs in the same inner shareable
1352 domain, so the hardware can use this fact to optimise the
1353 caching of such entries in the TLB.
1355 Selecting this option allows the CNP feature to be detected
1356 at runtime, and does not affect PEs that do not implement
1361 menu "ARMv8.3 architectural features"
1363 config ARM64_PTR_AUTH
1364 bool "Enable support for pointer authentication"
1366 depends on !KVM || ARM64_VHE
1368 Pointer authentication (part of the ARMv8.3 Extensions) provides
1369 instructions for signing and authenticating pointers against secret
1370 keys, which can be used to mitigate Return Oriented Programming (ROP)
1373 This option enables these instructions at EL0 (i.e. for userspace).
1375 Choosing this option will cause the kernel to initialise secret keys
1376 for each process at exec() time, with these keys being
1377 context-switched along with the process.
1379 The feature is detected at runtime. If the feature is not present in
1380 hardware it will not be advertised to userspace/KVM guest nor will it
1381 be enabled. However, KVM guest also require VHE mode and hence
1382 CONFIG_ARM64_VHE=y option to use this feature.
1387 bool "ARM Scalable Vector Extension support"
1389 depends on !KVM || ARM64_VHE
1391 The Scalable Vector Extension (SVE) is an extension to the AArch64
1392 execution state which complements and extends the SIMD functionality
1393 of the base architecture to support much larger vectors and to enable
1394 additional vectorisation opportunities.
1396 To enable use of this extension on CPUs that implement it, say Y.
1398 On CPUs that support the SVE2 extensions, this option will enable
1401 Note that for architectural reasons, firmware _must_ implement SVE
1402 support when running on SVE capable hardware. The required support
1405 * version 1.5 and later of the ARM Trusted Firmware
1406 * the AArch64 boot wrapper since commit 5e1261e08abf
1407 ("bootwrapper: SVE: Enable SVE for EL2 and below").
1409 For other firmware implementations, consult the firmware documentation
1412 If you need the kernel to boot on SVE-capable hardware with broken
1413 firmware, you may need to say N here until you get your firmware
1414 fixed. Otherwise, you may experience firmware panics or lockups when
1415 booting the kernel. If unsure and you are not observing these
1416 symptoms, you should assume that it is safe to say Y.
1418 CPUs that support SVE are architecturally required to support the
1419 Virtualization Host Extensions (VHE), so the kernel makes no
1420 provision for supporting SVE alongside KVM without VHE enabled.
1421 Thus, you will need to enable CONFIG_ARM64_VHE if you want to support
1422 KVM in the same kernel image.
1424 config ARM64_MODULE_PLTS
1425 bool "Use PLTs to allow module memory to spill over into vmalloc area"
1427 select HAVE_MOD_ARCH_SPECIFIC
1429 Allocate PLTs when loading modules so that jumps and calls whose
1430 targets are too far away for their relative offsets to be encoded
1431 in the instructions themselves can be bounced via veneers in the
1432 module's PLT. This allows modules to be allocated in the generic
1433 vmalloc area after the dedicated module memory area has been
1436 When running with address space randomization (KASLR), the module
1437 region itself may be too far away for ordinary relative jumps and
1438 calls, and so in that case, module PLTs are required and cannot be
1441 Specific errata workaround(s) might also force module PLTs to be
1442 enabled (ARM64_ERRATUM_843419).
1444 config ARM64_PSEUDO_NMI
1445 bool "Support for NMI-like interrupts"
1446 select CONFIG_ARM_GIC_V3
1448 Adds support for mimicking Non-Maskable Interrupts through the use of
1449 GIC interrupt priority. This support requires version 3 or later of
1452 This high priority configuration for interrupts needs to be
1453 explicitly enabled by setting the kernel parameter
1454 "irqchip.gicv3_pseudo_nmi" to 1.
1459 config ARM64_DEBUG_PRIORITY_MASKING
1460 bool "Debug interrupt priority masking"
1462 This adds runtime checks to functions enabling/disabling
1463 interrupts when using priority masking. The additional checks verify
1464 the validity of ICC_PMR_EL1 when calling concerned functions.
1472 This builds the kernel as a Position Independent Executable (PIE),
1473 which retains all relocation metadata required to relocate the
1474 kernel binary at runtime to a different virtual address than the
1475 address it was linked at.
1476 Since AArch64 uses the RELA relocation format, this requires a
1477 relocation pass at runtime even if the kernel is loaded at the
1478 same address it was linked at.
1480 config RANDOMIZE_BASE
1481 bool "Randomize the address of the kernel image"
1482 select ARM64_MODULE_PLTS if MODULES
1485 Randomizes the virtual address at which the kernel image is
1486 loaded, as a security feature that deters exploit attempts
1487 relying on knowledge of the location of kernel internals.
1489 It is the bootloader's job to provide entropy, by passing a
1490 random u64 value in /chosen/kaslr-seed at kernel entry.
1492 When booting via the UEFI stub, it will invoke the firmware's
1493 EFI_RNG_PROTOCOL implementation (if available) to supply entropy
1494 to the kernel proper. In addition, it will randomise the physical
1495 location of the kernel Image as well.
1499 config RANDOMIZE_MODULE_REGION_FULL
1500 bool "Randomize the module region over a 4 GB range"
1501 depends on RANDOMIZE_BASE
1504 Randomizes the location of the module region inside a 4 GB window
1505 covering the core kernel. This way, it is less likely for modules
1506 to leak information about the location of core kernel data structures
1507 but it does imply that function calls between modules and the core
1508 kernel will need to be resolved via veneers in the module PLT.
1510 When this option is not set, the module region will be randomized over
1511 a limited range that contains the [_stext, _etext] interval of the
1512 core kernel, so branch relocations are always in range.
1514 config CC_HAVE_STACKPROTECTOR_SYSREG
1515 def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0)
1517 config STACKPROTECTOR_PER_TASK
1519 depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG
1525 config ARM64_ACPI_PARKING_PROTOCOL
1526 bool "Enable support for the ARM64 ACPI parking protocol"
1529 Enable support for the ARM64 ACPI parking protocol. If disabled
1530 the kernel will not allow booting through the ARM64 ACPI parking
1531 protocol even if the corresponding data is present in the ACPI
1535 string "Default kernel command string"
1538 Provide a set of default command-line options at build time by
1539 entering them here. As a minimum, you should specify the the
1540 root device (e.g. root=/dev/nfs).
1542 config CMDLINE_FORCE
1543 bool "Always use the default kernel command string"
1545 Always use the default kernel command string, even if the boot
1546 loader passes other arguments to the kernel.
1547 This is useful if you cannot or don't want to change the
1548 command-line options your boot loader passes to the kernel.
1554 bool "UEFI runtime support"
1555 depends on OF && !CPU_BIG_ENDIAN
1556 depends on KERNEL_MODE_NEON
1557 select ARCH_SUPPORTS_ACPI
1560 select EFI_PARAMS_FROM_FDT
1561 select EFI_RUNTIME_WRAPPERS
1566 This option provides support for runtime services provided
1567 by UEFI firmware (such as non-volatile variables, realtime
1568 clock, and platform reset). A UEFI stub is also provided to
1569 allow the kernel to be booted as an EFI application. This
1570 is only useful on systems that have UEFI firmware.
1573 bool "Enable support for SMBIOS (DMI) tables"
1577 This enables SMBIOS/DMI feature for systems.
1579 This option is only useful on systems that have UEFI firmware.
1580 However, even with this option, the resultant kernel should
1581 continue to boot on existing non-UEFI platforms.
1585 config SYSVIPC_COMPAT
1587 depends on COMPAT && SYSVIPC
1589 config ARCH_ENABLE_HUGEPAGE_MIGRATION
1591 depends on HUGETLB_PAGE && MIGRATION
1593 menu "Power management options"
1595 source "kernel/power/Kconfig"
1597 config ARCH_HIBERNATION_POSSIBLE
1601 config ARCH_HIBERNATION_HEADER
1603 depends on HIBERNATION
1605 config ARCH_SUSPEND_POSSIBLE
1610 menu "CPU Power Management"
1612 source "drivers/cpuidle/Kconfig"
1614 source "drivers/cpufreq/Kconfig"
1618 source "drivers/firmware/Kconfig"
1620 source "drivers/acpi/Kconfig"
1622 source "arch/arm64/kvm/Kconfig"
1625 source "arch/arm64/crypto/Kconfig"