1 # SPDX-License-Identifier: GPL-2.0-only
4 select ACPI_CCA_REQUIRED if ACPI
5 select ACPI_GENERIC_GSI if ACPI
6 select ACPI_GTDT if ACPI
7 select ACPI_IORT if ACPI
8 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
9 select ACPI_MCFG if (ACPI && PCI)
10 select ACPI_SPCR_TABLE if ACPI
11 select ACPI_PPTT if ACPI
12 select ARCH_CLOCKSOURCE_DATA
13 select ARCH_HAS_DEBUG_VIRTUAL
14 select ARCH_HAS_DEVMEM_IS_ALLOWED
15 select ARCH_HAS_DMA_PREP_COHERENT
16 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
17 select ARCH_HAS_FAST_MULTIPLIER
18 select ARCH_HAS_FORTIFY_SOURCE
19 select ARCH_HAS_GCOV_PROFILE_ALL
20 select ARCH_HAS_GIGANTIC_PAGE
22 select ARCH_HAS_KEEPINITRD
23 select ARCH_HAS_MEMBARRIER_SYNC_CORE
24 select ARCH_HAS_PTE_DEVMAP
25 select ARCH_HAS_PTE_SPECIAL
26 select ARCH_HAS_SETUP_DMA_OPS
27 select ARCH_HAS_SET_DIRECT_MAP
28 select ARCH_HAS_SET_MEMORY
29 select ARCH_HAS_STRICT_KERNEL_RWX
30 select ARCH_HAS_STRICT_MODULE_RWX
31 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
32 select ARCH_HAS_SYNC_DMA_FOR_CPU
33 select ARCH_HAS_SYSCALL_WRAPPER
34 select ARCH_HAS_TEARDOWN_DMA_OPS if IOMMU_SUPPORT
35 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
36 select ARCH_HAVE_NMI_SAFE_CMPXCHG
37 select ARCH_INLINE_READ_LOCK if !PREEMPT
38 select ARCH_INLINE_READ_LOCK_BH if !PREEMPT
39 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPT
40 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPT
41 select ARCH_INLINE_READ_UNLOCK if !PREEMPT
42 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPT
43 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPT
44 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPT
45 select ARCH_INLINE_WRITE_LOCK if !PREEMPT
46 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPT
47 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPT
48 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPT
49 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPT
50 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPT
51 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPT
52 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPT
53 select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPT
54 select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPT
55 select ARCH_INLINE_SPIN_LOCK if !PREEMPT
56 select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPT
57 select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPT
58 select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPT
59 select ARCH_INLINE_SPIN_UNLOCK if !PREEMPT
60 select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPT
61 select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPT
62 select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPT
63 select ARCH_KEEP_MEMBLOCK
64 select ARCH_USE_CMPXCHG_LOCKREF
65 select ARCH_USE_QUEUED_RWLOCKS
66 select ARCH_USE_QUEUED_SPINLOCKS
67 select ARCH_SUPPORTS_MEMORY_FAILURE
68 select ARCH_SUPPORTS_ATOMIC_RMW
69 select ARCH_SUPPORTS_INT128 if CC_HAS_INT128 && (GCC_VERSION >= 50000 || CC_IS_CLANG)
70 select ARCH_SUPPORTS_NUMA_BALANCING
71 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT
72 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT
73 select ARCH_WANT_FRAME_POINTERS
74 select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
75 select ARCH_HAS_UBSAN_SANITIZE_ALL
79 select AUDIT_ARCH_COMPAT_GENERIC
80 select ARM_GIC_V2M if PCI
82 select ARM_GIC_V3_ITS if PCI
84 select BUILDTIME_EXTABLE_SORT
85 select CLONE_BACKWARDS
87 select CPU_PM if (SUSPEND || CPU_IDLE)
89 select DCACHE_WORD_ACCESS
90 select DMA_DIRECT_REMAP
93 select GENERIC_ALLOCATOR
94 select GENERIC_ARCH_TOPOLOGY
95 select GENERIC_CLOCKEVENTS
96 select GENERIC_CLOCKEVENTS_BROADCAST
97 select GENERIC_CPU_AUTOPROBE
98 select GENERIC_CPU_VULNERABILITIES
99 select GENERIC_EARLY_IOREMAP
100 select GENERIC_IDLE_POLL_SETUP
101 select GENERIC_IRQ_MULTI_HANDLER
102 select GENERIC_IRQ_PROBE
103 select GENERIC_IRQ_SHOW
104 select GENERIC_IRQ_SHOW_LEVEL
105 select GENERIC_PCI_IOMAP
106 select GENERIC_SCHED_CLOCK
107 select GENERIC_SMP_IDLE_THREAD
108 select GENERIC_STRNCPY_FROM_USER
109 select GENERIC_STRNLEN_USER
110 select GENERIC_TIME_VSYSCALL
111 select GENERIC_GETTIMEOFDAY
112 select HANDLE_DOMAIN_IRQ
113 select HARDIRQS_SW_RESEND
115 select HAVE_ACPI_APEI if (ACPI && EFI)
116 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
117 select HAVE_ARCH_AUDITSYSCALL
118 select HAVE_ARCH_BITREVERSE
119 select HAVE_ARCH_HUGE_VMAP
120 select HAVE_ARCH_JUMP_LABEL
121 select HAVE_ARCH_JUMP_LABEL_RELATIVE
122 select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
123 select HAVE_ARCH_KASAN_SW_TAGS if HAVE_ARCH_KASAN
124 select HAVE_ARCH_KGDB
125 select HAVE_ARCH_MMAP_RND_BITS
126 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
127 select HAVE_ARCH_PREL32_RELOCATIONS
128 select HAVE_ARCH_SECCOMP_FILTER
129 select HAVE_ARCH_STACKLEAK
130 select HAVE_ARCH_THREAD_STRUCT_WHITELIST
131 select HAVE_ARCH_TRACEHOOK
132 select HAVE_ARCH_TRANSPARENT_HUGEPAGE
133 select HAVE_ARCH_VMAP_STACK
134 select HAVE_ARM_SMCCC
135 select HAVE_ASM_MODVERSIONS
137 select HAVE_C_RECORDMCOUNT
138 select HAVE_CMPXCHG_DOUBLE
139 select HAVE_CMPXCHG_LOCAL
140 select HAVE_CONTEXT_TRACKING
141 select HAVE_COPY_THREAD_TLS
142 select HAVE_DEBUG_BUGVERBOSE
143 select HAVE_DEBUG_KMEMLEAK
144 select HAVE_DMA_CONTIGUOUS
145 select HAVE_DYNAMIC_FTRACE
146 select HAVE_DYNAMIC_FTRACE_WITH_REGS \
147 if $(cc-option,-fpatchable-function-entry=2)
148 select HAVE_EFFICIENT_UNALIGNED_ACCESS
150 select HAVE_FTRACE_MCOUNT_RECORD
151 select HAVE_FUNCTION_TRACER
152 select HAVE_FUNCTION_ERROR_INJECTION
153 select HAVE_FUNCTION_GRAPH_TRACER
154 select HAVE_GCC_PLUGINS
155 select HAVE_HW_BREAKPOINT if PERF_EVENTS
156 select HAVE_IRQ_TIME_ACCOUNTING
157 select HAVE_MEMBLOCK_NODE_MAP if NUMA
159 select HAVE_PATA_PLATFORM
160 select HAVE_PERF_EVENTS
161 select HAVE_PERF_REGS
162 select HAVE_PERF_USER_STACK_DUMP
163 select HAVE_REGS_AND_STACK_ACCESS_API
164 select HAVE_FUNCTION_ARG_ACCESS_API
165 select HAVE_RCU_TABLE_FREE
167 select HAVE_STACKPROTECTOR
168 select HAVE_SYSCALL_TRACEPOINTS
170 select HAVE_KRETPROBES
171 select HAVE_GENERIC_VDSO
172 select IOMMU_DMA if IOMMU_SUPPORT
174 select IRQ_FORCED_THREADING
175 select MODULES_USE_ELF_RELA
176 select NEED_DMA_MAP_STATE
177 select NEED_SG_DMA_LENGTH
179 select OF_EARLY_FLATTREE
180 select PCI_DOMAINS_GENERIC if PCI
181 select PCI_ECAM if (ACPI && PCI)
182 select PCI_SYSCALL if PCI
187 select SYSCTL_EXCEPTION_TRACE
188 select THREAD_INFO_IN_TASK
190 ARM 64-bit (AArch64) Linux support.
198 config ARM64_PAGE_SHIFT
200 default 16 if ARM64_64K_PAGES
201 default 14 if ARM64_16K_PAGES
204 config ARM64_CONT_SHIFT
206 default 5 if ARM64_64K_PAGES
207 default 7 if ARM64_16K_PAGES
210 config ARCH_MMAP_RND_BITS_MIN
211 default 14 if ARM64_64K_PAGES
212 default 16 if ARM64_16K_PAGES
215 # max bits determined by the following formula:
216 # VA_BITS - PAGE_SHIFT - 3
217 config ARCH_MMAP_RND_BITS_MAX
218 default 19 if ARM64_VA_BITS=36
219 default 24 if ARM64_VA_BITS=39
220 default 27 if ARM64_VA_BITS=42
221 default 30 if ARM64_VA_BITS=47
222 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
223 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
224 default 33 if ARM64_VA_BITS=48
225 default 14 if ARM64_64K_PAGES
226 default 16 if ARM64_16K_PAGES
229 config ARCH_MMAP_RND_COMPAT_BITS_MIN
230 default 7 if ARM64_64K_PAGES
231 default 9 if ARM64_16K_PAGES
234 config ARCH_MMAP_RND_COMPAT_BITS_MAX
240 config STACKTRACE_SUPPORT
243 config ILLEGAL_POINTER_VALUE
245 default 0xdead000000000000
247 config LOCKDEP_SUPPORT
250 config TRACE_IRQFLAGS_SUPPORT
257 config GENERIC_BUG_RELATIVE_POINTERS
259 depends on GENERIC_BUG
261 config GENERIC_HWEIGHT
267 config GENERIC_CALIBRATE_DELAY
271 bool "Support DMA zone" if EXPERT
275 bool "Support DMA32 zone" if EXPERT
278 config ARCH_ENABLE_MEMORY_HOTPLUG
284 config KERNEL_MODE_NEON
287 config FIX_EARLYCON_MEM
290 config PGTABLE_LEVELS
292 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
293 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
294 default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52)
295 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
296 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
297 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
299 config ARCH_SUPPORTS_UPROBES
302 config ARCH_PROC_KCORE_TEXT
305 config KASAN_SHADOW_OFFSET
308 default 0xdfffa00000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && !KASAN_SW_TAGS
309 default 0xdfffd00000000000 if ARM64_VA_BITS_47 && !KASAN_SW_TAGS
310 default 0xdffffe8000000000 if ARM64_VA_BITS_42 && !KASAN_SW_TAGS
311 default 0xdfffffd000000000 if ARM64_VA_BITS_39 && !KASAN_SW_TAGS
312 default 0xdffffffa00000000 if ARM64_VA_BITS_36 && !KASAN_SW_TAGS
313 default 0xefff900000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && KASAN_SW_TAGS
314 default 0xefffc80000000000 if ARM64_VA_BITS_47 && KASAN_SW_TAGS
315 default 0xeffffe4000000000 if ARM64_VA_BITS_42 && KASAN_SW_TAGS
316 default 0xefffffc800000000 if ARM64_VA_BITS_39 && KASAN_SW_TAGS
317 default 0xeffffff900000000 if ARM64_VA_BITS_36 && KASAN_SW_TAGS
318 default 0xffffffffffffffff
320 source "arch/arm64/Kconfig.platforms"
322 menu "Kernel Features"
324 menu "ARM errata workarounds via the alternatives framework"
326 config ARM64_WORKAROUND_CLEAN_CACHE
329 config ARM64_ERRATUM_826319
330 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
332 select ARM64_WORKAROUND_CLEAN_CACHE
334 This option adds an alternative code sequence to work around ARM
335 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
336 AXI master interface and an L2 cache.
338 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
339 and is unable to accept a certain write via this interface, it will
340 not progress on read data presented on the read data channel and the
343 The workaround promotes data cache clean instructions to
344 data cache clean-and-invalidate.
345 Please note that this does not necessarily enable the workaround,
346 as it depends on the alternative framework, which will only patch
347 the kernel if an affected CPU is detected.
351 config ARM64_ERRATUM_827319
352 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
354 select ARM64_WORKAROUND_CLEAN_CACHE
356 This option adds an alternative code sequence to work around ARM
357 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
358 master interface and an L2 cache.
360 Under certain conditions this erratum can cause a clean line eviction
361 to occur at the same time as another transaction to the same address
362 on the AMBA 5 CHI interface, which can cause data corruption if the
363 interconnect reorders the two transactions.
365 The workaround promotes data cache clean instructions to
366 data cache clean-and-invalidate.
367 Please note that this does not necessarily enable the workaround,
368 as it depends on the alternative framework, which will only patch
369 the kernel if an affected CPU is detected.
373 config ARM64_ERRATUM_824069
374 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
376 select ARM64_WORKAROUND_CLEAN_CACHE
378 This option adds an alternative code sequence to work around ARM
379 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
380 to a coherent interconnect.
382 If a Cortex-A53 processor is executing a store or prefetch for
383 write instruction at the same time as a processor in another
384 cluster is executing a cache maintenance operation to the same
385 address, then this erratum might cause a clean cache line to be
386 incorrectly marked as dirty.
388 The workaround promotes data cache clean instructions to
389 data cache clean-and-invalidate.
390 Please note that this option does not necessarily enable the
391 workaround, as it depends on the alternative framework, which will
392 only patch the kernel if an affected CPU is detected.
396 config ARM64_ERRATUM_819472
397 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
399 select ARM64_WORKAROUND_CLEAN_CACHE
401 This option adds an alternative code sequence to work around ARM
402 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
403 present when it is connected to a coherent interconnect.
405 If the processor is executing a load and store exclusive sequence at
406 the same time as a processor in another cluster is executing a cache
407 maintenance operation to the same address, then this erratum might
408 cause data corruption.
410 The workaround promotes data cache clean instructions to
411 data cache clean-and-invalidate.
412 Please note that this does not necessarily enable the workaround,
413 as it depends on the alternative framework, which will only patch
414 the kernel if an affected CPU is detected.
418 config ARM64_ERRATUM_832075
419 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
422 This option adds an alternative code sequence to work around ARM
423 erratum 832075 on Cortex-A57 parts up to r1p2.
425 Affected Cortex-A57 parts might deadlock when exclusive load/store
426 instructions to Write-Back memory are mixed with Device loads.
428 The workaround is to promote device loads to use Load-Acquire
430 Please note that this does not necessarily enable the workaround,
431 as it depends on the alternative framework, which will only patch
432 the kernel if an affected CPU is detected.
436 config ARM64_ERRATUM_834220
437 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
441 This option adds an alternative code sequence to work around ARM
442 erratum 834220 on Cortex-A57 parts up to r1p2.
444 Affected Cortex-A57 parts might report a Stage 2 translation
445 fault as the result of a Stage 1 fault for load crossing a
446 page boundary when there is a permission or device memory
447 alignment fault at Stage 1 and a translation fault at Stage 2.
449 The workaround is to verify that the Stage 1 translation
450 doesn't generate a fault before handling the Stage 2 fault.
451 Please note that this does not necessarily enable the workaround,
452 as it depends on the alternative framework, which will only patch
453 the kernel if an affected CPU is detected.
457 config ARM64_ERRATUM_845719
458 bool "Cortex-A53: 845719: a load might read incorrect data"
462 This option adds an alternative code sequence to work around ARM
463 erratum 845719 on Cortex-A53 parts up to r0p4.
465 When running a compat (AArch32) userspace on an affected Cortex-A53
466 part, a load at EL0 from a virtual address that matches the bottom 32
467 bits of the virtual address used by a recent load at (AArch64) EL1
468 might return incorrect data.
470 The workaround is to write the contextidr_el1 register on exception
471 return to a 32-bit task.
472 Please note that this does not necessarily enable the workaround,
473 as it depends on the alternative framework, which will only patch
474 the kernel if an affected CPU is detected.
478 config ARM64_ERRATUM_843419
479 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
481 select ARM64_MODULE_PLTS if MODULES
483 This option links the kernel with '--fix-cortex-a53-843419' and
484 enables PLT support to replace certain ADRP instructions, which can
485 cause subsequent memory accesses to use an incorrect address on
486 Cortex-A53 parts up to r0p4.
490 config ARM64_ERRATUM_1024718
491 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update"
494 This option adds a workaround for ARM Cortex-A55 Erratum 1024718.
496 Affected Cortex-A55 cores (r0p0, r0p1, r1p0) could cause incorrect
497 update of the hardware dirty bit when the DBM/AP bits are updated
498 without a break-before-make. The workaround is to disable the usage
499 of hardware DBM locally on the affected cores. CPUs not affected by
500 this erratum will continue to use the feature.
504 config ARM64_ERRATUM_1418040
505 bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result"
509 This option adds a workaround for ARM Cortex-A76/Neoverse-N1
510 errata 1188873 and 1418040.
512 Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could
513 cause register corruption when accessing the timer registers
514 from AArch32 userspace.
518 config ARM64_ERRATUM_1165522
519 bool "Cortex-A76: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
522 This option adds a workaround for ARM Cortex-A76 erratum 1165522.
524 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with
525 corrupted TLBs by speculating an AT instruction during a guest
530 config ARM64_ERRATUM_1286807
531 bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation"
533 select ARM64_WORKAROUND_REPEAT_TLBI
535 This option adds a workaround for ARM Cortex-A76 erratum 1286807.
537 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual
538 address for a cacheable mapping of a location is being
539 accessed by a core while another core is remapping the virtual
540 address to a new physical page using the recommended
541 break-before-make sequence, then under very rare circumstances
542 TLBI+DSB completes before a read using the translation being
543 invalidated has been observed by other observers. The
544 workaround repeats the TLBI+DSB operation.
546 config ARM64_ERRATUM_1319367
547 bool "Cortex-A57/A72: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
550 This option adds work arounds for ARM Cortex-A57 erratum 1319537
551 and A72 erratum 1319367
553 Cortex-A57 and A72 cores could end-up with corrupted TLBs by
554 speculating an AT instruction during a guest context switch.
558 config ARM64_ERRATUM_1463225
559 bool "Cortex-A76: Software Step might prevent interrupt recognition"
562 This option adds a workaround for Arm Cortex-A76 erratum 1463225.
564 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping
565 of a system call instruction (SVC) can prevent recognition of
566 subsequent interrupts when software stepping is disabled in the
567 exception handler of the system call and either kernel debugging
568 is enabled or VHE is in use.
570 Work around the erratum by triggering a dummy step exception
571 when handling a system call from a task that is being stepped
572 in a VHE configuration of the kernel.
576 config ARM64_ERRATUM_1542419
577 bool "Neoverse-N1: workaround mis-ordering of instruction fetches"
580 This option adds a workaround for ARM Neoverse-N1 erratum
583 Affected Neoverse-N1 cores could execute a stale instruction when
584 modified by another CPU. The workaround depends on a firmware
587 Workaround the issue by hiding the DIC feature from EL0. This
588 forces user-space to perform cache maintenance.
592 config CAVIUM_ERRATUM_22375
593 bool "Cavium erratum 22375, 24313"
596 Enable workaround for errata 22375 and 24313.
598 This implements two gicv3-its errata workarounds for ThunderX. Both
599 with a small impact affecting only ITS table allocation.
601 erratum 22375: only alloc 8MB table size
602 erratum 24313: ignore memory access type
604 The fixes are in ITS initialization and basically ignore memory access
605 type and table size provided by the TYPER and BASER registers.
609 config CAVIUM_ERRATUM_23144
610 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
614 ITS SYNC command hang for cross node io and collections/cpu mapping.
618 config CAVIUM_ERRATUM_23154
619 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
622 The gicv3 of ThunderX requires a modified version for
623 reading the IAR status to ensure data synchronization
624 (access to icc_iar1_el1 is not sync'ed before and after).
628 config CAVIUM_ERRATUM_27456
629 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
632 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
633 instructions may cause the icache to become corrupted if it
634 contains data for a non-current ASID. The fix is to
635 invalidate the icache when changing the mm context.
639 config CAVIUM_ERRATUM_30115
640 bool "Cavium erratum 30115: Guest may disable interrupts in host"
643 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through
644 1.2, and T83 Pass 1.0, KVM guest execution may disable
645 interrupts in host. Trapping both GICv3 group-0 and group-1
646 accesses sidesteps the issue.
650 config CAVIUM_TX2_ERRATUM_219
651 bool "Cavium ThunderX2 erratum 219: PRFM between TTBR change and ISB fails"
654 On Cavium ThunderX2, a load, store or prefetch instruction between a
655 TTBR update and the corresponding context synchronizing operation can
656 cause a spurious Data Abort to be delivered to any hardware thread in
659 Work around the issue by avoiding the problematic code sequence and
660 trapping KVM guest TTBRx_EL1 writes to EL2 when SMT is enabled. The
661 trap handler performs the corresponding register access, skips the
662 instruction and ensures context synchronization by virtue of the
667 config QCOM_FALKOR_ERRATUM_1003
668 bool "Falkor E1003: Incorrect translation due to ASID change"
671 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
672 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID
673 in TTBR1_EL1, this situation only occurs in the entry trampoline and
674 then only for entries in the walk cache, since the leaf translation
675 is unchanged. Work around the erratum by invalidating the walk cache
676 entries for the trampoline before entering the kernel proper.
678 config ARM64_WORKAROUND_REPEAT_TLBI
681 config QCOM_FALKOR_ERRATUM_1009
682 bool "Falkor E1009: Prematurely complete a DSB after a TLBI"
684 select ARM64_WORKAROUND_REPEAT_TLBI
686 On Falkor v1, the CPU may prematurely complete a DSB following a
687 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation
688 one more time to fix the issue.
692 config QCOM_QDF2400_ERRATUM_0065
693 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size"
696 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports
697 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have
698 been indicated as 16Bytes (0xf), not 8Bytes (0x7).
702 config SOCIONEXT_SYNQUACER_PREITS
703 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
706 Socionext Synquacer SoCs implement a separate h/w block to generate
707 MSI doorbell writes with non-zero values for the device ID.
711 config HISILICON_ERRATUM_161600802
712 bool "Hip07 161600802: Erroneous redistributor VLPI base"
715 The HiSilicon Hip07 SoC uses the wrong redistributor base
716 when issued ITS commands such as VMOVP and VMAPP, and requires
717 a 128kB offset to be applied to the target address in this commands.
721 config QCOM_FALKOR_ERRATUM_E1041
722 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access"
725 Falkor CPU may speculatively fetch instructions from an improper
726 memory location when MMU translation is changed from SCTLR_ELn[M]=1
727 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem.
731 config FUJITSU_ERRATUM_010001
732 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly"
735 This option adds a workaround for Fujitsu-A64FX erratum E#010001.
736 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory
737 accesses may cause undefined fault (Data abort, DFSC=0b111111).
738 This fault occurs under a specific hardware condition when a
739 load/store instruction performs an address translation using:
740 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1.
741 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1.
742 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1.
743 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1.
745 The workaround is to ensure these bits are clear in TCR_ELx.
746 The workaround only affects the Fujitsu-A64FX.
755 default ARM64_4K_PAGES
757 Page size (translation granule) configuration.
759 config ARM64_4K_PAGES
762 This feature enables 4KB pages support.
764 config ARM64_16K_PAGES
767 The system will use 16KB pages support. AArch32 emulation
768 requires applications compiled with 16K (or a multiple of 16K)
771 config ARM64_64K_PAGES
774 This feature enables 64KB pages support (4KB by default)
775 allowing only two levels of page tables and faster TLB
776 look-up. AArch32 emulation requires applications compiled
777 with 64K aligned segments.
782 prompt "Virtual address space size"
783 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
784 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
785 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
787 Allows choosing one of multiple possible virtual address
788 space sizes. The level of translation table is determined by
789 a combination of page size and virtual address space size.
791 config ARM64_VA_BITS_36
792 bool "36-bit" if EXPERT
793 depends on ARM64_16K_PAGES
795 config ARM64_VA_BITS_39
797 depends on ARM64_4K_PAGES
799 config ARM64_VA_BITS_42
801 depends on ARM64_64K_PAGES
803 config ARM64_VA_BITS_47
805 depends on ARM64_16K_PAGES
807 config ARM64_VA_BITS_48
810 config ARM64_VA_BITS_52
812 depends on ARM64_64K_PAGES && (ARM64_PAN || !ARM64_SW_TTBR0_PAN)
814 Enable 52-bit virtual addressing for userspace when explicitly
815 requested via a hint to mmap(). The kernel will also use 52-bit
816 virtual addresses for its own mappings (provided HW support for
817 this feature is available, otherwise it reverts to 48-bit).
819 NOTE: Enabling 52-bit virtual addressing in conjunction with
820 ARMv8.3 Pointer Authentication will result in the PAC being
821 reduced from 7 bits to 3 bits, which may have a significant
822 impact on its susceptibility to brute-force attacks.
824 If unsure, select 48-bit virtual addressing instead.
828 config ARM64_FORCE_52BIT
829 bool "Force 52-bit virtual addresses for userspace"
830 depends on ARM64_VA_BITS_52 && EXPERT
832 For systems with 52-bit userspace VAs enabled, the kernel will attempt
833 to maintain compatibility with older software by providing 48-bit VAs
834 unless a hint is supplied to mmap.
836 This configuration option disables the 48-bit compatibility logic, and
837 forces all userspace addresses to be 52-bit on HW that supports it. One
838 should only enable this configuration option for stress testing userspace
839 memory management code. If unsure say N here.
843 default 36 if ARM64_VA_BITS_36
844 default 39 if ARM64_VA_BITS_39
845 default 42 if ARM64_VA_BITS_42
846 default 47 if ARM64_VA_BITS_47
847 default 48 if ARM64_VA_BITS_48
848 default 52 if ARM64_VA_BITS_52
851 prompt "Physical address space size"
852 default ARM64_PA_BITS_48
854 Choose the maximum physical address range that the kernel will
857 config ARM64_PA_BITS_48
860 config ARM64_PA_BITS_52
861 bool "52-bit (ARMv8.2)"
862 depends on ARM64_64K_PAGES
863 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
865 Enable support for a 52-bit physical address space, introduced as
866 part of the ARMv8.2-LPA extension.
868 With this enabled, the kernel will also continue to work on CPUs that
869 do not support ARMv8.2-LPA, but with some added memory overhead (and
870 minor performance overhead).
876 default 48 if ARM64_PA_BITS_48
877 default 52 if ARM64_PA_BITS_52
881 default CPU_LITTLE_ENDIAN
883 Select the endianness of data accesses performed by the CPU. Userspace
884 applications will need to be compiled and linked for the endianness
885 that is selected here.
887 config CPU_BIG_ENDIAN
888 bool "Build big-endian kernel"
890 Say Y if you plan on running a kernel with a big-endian userspace.
892 config CPU_LITTLE_ENDIAN
893 bool "Build little-endian kernel"
895 Say Y if you plan on running a kernel with a little-endian userspace.
896 This is usually the case for distributions targeting arm64.
901 bool "Multi-core scheduler support"
903 Multi-core scheduler support improves the CPU scheduler's decision
904 making when dealing with multi-core CPU chips at a cost of slightly
905 increased overhead in some places. If unsure say N here.
908 bool "SMT scheduler support"
910 Improves the CPU scheduler's decision making when dealing with
911 MultiThreading at a cost of slightly increased overhead in some
912 places. If unsure say N here.
915 int "Maximum number of CPUs (2-4096)"
920 bool "Support for hot-pluggable CPUs"
921 select GENERIC_IRQ_MIGRATION
923 Say Y here to experiment with turning CPUs off and on. CPUs
924 can be controlled through /sys/devices/system/cpu.
926 # Common NUMA Features
928 bool "Numa Memory Allocation and Scheduler Support"
929 select ACPI_NUMA if ACPI
932 Enable NUMA (Non Uniform Memory Access) support.
934 The kernel will try to allocate memory used by a CPU on the
935 local memory of the CPU and add some more
936 NUMA awareness to the kernel.
939 int "Maximum NUMA Nodes (as a power of 2)"
942 depends on NEED_MULTIPLE_NODES
944 Specify the maximum number of NUMA Nodes available on the target
945 system. Increases memory reserved to accommodate various tables.
947 config USE_PERCPU_NUMA_NODE_ID
951 config HAVE_SETUP_PER_CPU_AREA
955 config NEED_PER_CPU_EMBED_FIRST_CHUNK
962 source "kernel/Kconfig.hz"
964 config ARCH_SUPPORTS_DEBUG_PAGEALLOC
967 config ARCH_SPARSEMEM_ENABLE
969 select SPARSEMEM_VMEMMAP_ENABLE
971 config ARCH_SPARSEMEM_DEFAULT
972 def_bool ARCH_SPARSEMEM_ENABLE
974 config ARCH_SELECT_MEMORY_MODEL
975 def_bool ARCH_SPARSEMEM_ENABLE
977 config ARCH_FLATMEM_ENABLE
980 config HAVE_ARCH_PFN_VALID
983 config HW_PERF_EVENTS
987 config SYS_SUPPORTS_HUGETLBFS
990 config ARCH_WANT_HUGE_PMD_SHARE
992 config ARCH_HAS_CACHE_LINE_SIZE
995 config ARCH_ENABLE_SPLIT_PMD_PTLOCK
996 def_bool y if PGTABLE_LEVELS > 2
999 bool "Enable seccomp to safely compute untrusted bytecode"
1001 This kernel feature is useful for number crunching applications
1002 that may need to compute untrusted bytecode during their
1003 execution. By using pipes or other transports made available to
1004 the process as file descriptors supporting the read/write
1005 syscalls, it's possible to isolate those applications in
1006 their own address space using seccomp. Once seccomp is
1007 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1008 and the task is only allowed to execute a few safe syscalls
1009 defined by each seccomp mode.
1012 bool "Enable paravirtualization code"
1014 This changes the kernel so it can modify itself when it is run
1015 under a hypervisor, potentially improving performance significantly
1016 over full virtualization.
1018 config PARAVIRT_TIME_ACCOUNTING
1019 bool "Paravirtual steal time accounting"
1022 Select this option to enable fine granularity task steal time
1023 accounting. Time spent executing other tasks in parallel with
1024 the current vCPU is discounted from the vCPU power. To account for
1025 that, there can be a small performance impact.
1027 If in doubt, say N here.
1030 depends on PM_SLEEP_SMP
1032 bool "kexec system call"
1034 kexec is a system call that implements the ability to shutdown your
1035 current kernel, and to start another kernel. It is like a reboot
1036 but it is independent of the system firmware. And like a reboot
1037 you can start any kernel with it, not just Linux.
1040 bool "kexec file based system call"
1043 This is new version of kexec system call. This system call is
1044 file based and takes file descriptors as system call argument
1045 for kernel and initramfs as opposed to list of segments as
1046 accepted by previous system call.
1049 bool "Verify kernel signature during kexec_file_load() syscall"
1050 depends on KEXEC_FILE
1052 Select this option to verify a signature with loaded kernel
1053 image. If configured, any attempt of loading a image without
1054 valid signature will fail.
1056 In addition to that option, you need to enable signature
1057 verification for the corresponding kernel image type being
1058 loaded in order for this to work.
1060 config KEXEC_IMAGE_VERIFY_SIG
1061 bool "Enable Image signature verification support"
1063 depends on KEXEC_SIG
1064 depends on EFI && SIGNED_PE_FILE_VERIFICATION
1066 Enable Image signature verification support.
1068 comment "Support for PE file signature verification disabled"
1069 depends on KEXEC_SIG
1070 depends on !EFI || !SIGNED_PE_FILE_VERIFICATION
1073 bool "Build kdump crash kernel"
1075 Generate crash dump after being started by kexec. This should
1076 be normally only set in special crash dump kernels which are
1077 loaded in the main kernel with kexec-tools into a specially
1078 reserved region and then later executed after a crash by
1081 For more details see Documentation/admin-guide/kdump/kdump.rst
1088 bool "Xen guest support on ARM64"
1089 depends on ARM64 && OF
1093 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
1095 config FORCE_MAX_ZONEORDER
1097 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
1098 default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE)
1101 The kernel memory allocator divides physically contiguous memory
1102 blocks into "zones", where each zone is a power of two number of
1103 pages. This option selects the largest power of two that the kernel
1104 keeps in the memory allocator. If you need to allocate very large
1105 blocks of physically contiguous memory, then you may need to
1106 increase this value.
1108 This config option is actually maximum order plus one. For example,
1109 a value of 11 means that the largest free memory block is 2^10 pages.
1111 We make sure that we can allocate upto a HugePage size for each configuration.
1113 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
1115 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
1116 4M allocations matching the default size used by generic code.
1118 config UNMAP_KERNEL_AT_EL0
1119 bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT
1122 Speculation attacks against some high-performance processors can
1123 be used to bypass MMU permission checks and leak kernel data to
1124 userspace. This can be defended against by unmapping the kernel
1125 when running in userspace, mapping it back in on exception entry
1126 via a trampoline page in the vector table.
1130 config HARDEN_BRANCH_PREDICTOR
1131 bool "Harden the branch predictor against aliasing attacks" if EXPERT
1134 Speculation attacks against some high-performance processors rely on
1135 being able to manipulate the branch predictor for a victim context by
1136 executing aliasing branches in the attacker context. Such attacks
1137 can be partially mitigated against by clearing internal branch
1138 predictor state and limiting the prediction logic in some situations.
1140 This config option will take CPU-specific actions to harden the
1141 branch predictor against aliasing attacks and may rely on specific
1142 instruction sequences or control bits being set by the system
1147 config HARDEN_EL2_VECTORS
1148 bool "Harden EL2 vector mapping against system register leak" if EXPERT
1151 Speculation attacks against some high-performance processors can
1152 be used to leak privileged information such as the vector base
1153 register, resulting in a potential defeat of the EL2 layout
1156 This config option will map the vectors to a fixed location,
1157 independent of the EL2 code mapping, so that revealing VBAR_EL2
1158 to an attacker does not give away any extra information. This
1159 only gets enabled on affected CPUs.
1164 bool "Speculative Store Bypass Disable" if EXPERT
1167 This enables mitigation of the bypassing of previous stores
1168 by speculative loads.
1172 config RODATA_FULL_DEFAULT_ENABLED
1173 bool "Apply r/o permissions of VM areas also to their linear aliases"
1176 Apply read-only attributes of VM areas to the linear alias of
1177 the backing pages as well. This prevents code or read-only data
1178 from being modified (inadvertently or intentionally) via another
1179 mapping of the same memory page. This additional enhancement can
1180 be turned off at runtime by passing rodata=[off|on] (and turned on
1181 with rodata=full if this option is set to 'n')
1183 This requires the linear region to be mapped down to pages,
1184 which may adversely affect performance in some cases.
1186 config ARM64_SW_TTBR0_PAN
1187 bool "Emulate Privileged Access Never using TTBR0_EL1 switching"
1189 Enabling this option prevents the kernel from accessing
1190 user-space memory directly by pointing TTBR0_EL1 to a reserved
1191 zeroed area and reserved ASID. The user access routines
1192 restore the valid TTBR0_EL1 temporarily.
1194 config ARM64_TAGGED_ADDR_ABI
1195 bool "Enable the tagged user addresses syscall ABI"
1198 When this option is enabled, user applications can opt in to a
1199 relaxed ABI via prctl() allowing tagged addresses to be passed
1200 to system calls as pointer arguments. For details, see
1201 Documentation/arm64/tagged-address-abi.rst.
1204 bool "Kernel support for 32-bit EL0"
1205 depends on ARM64_4K_PAGES || EXPERT
1206 select COMPAT_BINFMT_ELF if BINFMT_ELF
1208 select OLD_SIGSUSPEND3
1209 select COMPAT_OLD_SIGACTION
1211 This option enables support for a 32-bit EL0 running under a 64-bit
1212 kernel at EL1. AArch32-specific components such as system calls,
1213 the user helper functions, VFP support and the ptrace interface are
1214 handled appropriately by the kernel.
1216 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
1217 that you will only be able to execute AArch32 binaries that were compiled
1218 with page size aligned segments.
1220 If you want to execute 32-bit userspace applications, say Y.
1224 config KUSER_HELPERS
1225 bool "Enable kuser helpers page for 32-bit applications"
1228 Warning: disabling this option may break 32-bit user programs.
1230 Provide kuser helpers to compat tasks. The kernel provides
1231 helper code to userspace in read only form at a fixed location
1232 to allow userspace to be independent of the CPU type fitted to
1233 the system. This permits binaries to be run on ARMv4 through
1234 to ARMv8 without modification.
1236 See Documentation/arm/kernel_user_helpers.rst for details.
1238 However, the fixed address nature of these helpers can be used
1239 by ROP (return orientated programming) authors when creating
1242 If all of the binaries and libraries which run on your platform
1243 are built specifically for your platform, and make no use of
1244 these helpers, then you can turn this option off to hinder
1245 such exploits. However, in that case, if a binary or library
1246 relying on those helpers is run, it will not function correctly.
1248 Say N here only if you are absolutely certain that you do not
1249 need these helpers; otherwise, the safe option is to say Y.
1252 bool "Enable vDSO for 32-bit applications"
1253 depends on !CPU_BIG_ENDIAN && "$(CROSS_COMPILE_COMPAT)" != ""
1254 select GENERIC_COMPAT_VDSO
1257 Place in the process address space of 32-bit applications an
1258 ELF shared object providing fast implementations of gettimeofday
1261 You must have a 32-bit build of glibc 2.22 or later for programs
1262 to seamlessly take advantage of this.
1264 menuconfig ARMV8_DEPRECATED
1265 bool "Emulate deprecated/obsolete ARMv8 instructions"
1268 Legacy software support may require certain instructions
1269 that have been deprecated or obsoleted in the architecture.
1271 Enable this config to enable selective emulation of these
1278 config SWP_EMULATION
1279 bool "Emulate SWP/SWPB instructions"
1281 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
1282 they are always undefined. Say Y here to enable software
1283 emulation of these instructions for userspace using LDXR/STXR.
1285 In some older versions of glibc [<=2.8] SWP is used during futex
1286 trylock() operations with the assumption that the code will not
1287 be preempted. This invalid assumption may be more likely to fail
1288 with SWP emulation enabled, leading to deadlock of the user
1291 NOTE: when accessing uncached shared regions, LDXR/STXR rely
1292 on an external transaction monitoring block called a global
1293 monitor to maintain update atomicity. If your system does not
1294 implement a global monitor, this option can cause programs that
1295 perform SWP operations to uncached memory to deadlock.
1299 config CP15_BARRIER_EMULATION
1300 bool "Emulate CP15 Barrier instructions"
1302 The CP15 barrier instructions - CP15ISB, CP15DSB, and
1303 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
1304 strongly recommended to use the ISB, DSB, and DMB
1305 instructions instead.
1307 Say Y here to enable software emulation of these
1308 instructions for AArch32 userspace code. When this option is
1309 enabled, CP15 barrier usage is traced which can help
1310 identify software that needs updating.
1314 config SETEND_EMULATION
1315 bool "Emulate SETEND instruction"
1317 The SETEND instruction alters the data-endianness of the
1318 AArch32 EL0, and is deprecated in ARMv8.
1320 Say Y here to enable software emulation of the instruction
1321 for AArch32 userspace code.
1323 Note: All the cpus on the system must have mixed endian support at EL0
1324 for this feature to be enabled. If a new CPU - which doesn't support mixed
1325 endian - is hotplugged in after this feature has been enabled, there could
1326 be unexpected results in the applications.
1333 menu "ARMv8.1 architectural features"
1335 config ARM64_HW_AFDBM
1336 bool "Support for hardware updates of the Access and Dirty page flags"
1339 The ARMv8.1 architecture extensions introduce support for
1340 hardware updates of the access and dirty information in page
1341 table entries. When enabled in TCR_EL1 (HA and HD bits) on
1342 capable processors, accesses to pages with PTE_AF cleared will
1343 set this bit instead of raising an access flag fault.
1344 Similarly, writes to read-only pages with the DBM bit set will
1345 clear the read-only bit (AP[2]) instead of raising a
1348 Kernels built with this configuration option enabled continue
1349 to work on pre-ARMv8.1 hardware and the performance impact is
1350 minimal. If unsure, say Y.
1353 bool "Enable support for Privileged Access Never (PAN)"
1356 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
1357 prevents the kernel or hypervisor from accessing user-space (EL0)
1360 Choosing this option will cause any unprotected (not using
1361 copy_to_user et al) memory access to fail with a permission fault.
1363 The feature is detected at runtime, and will remain as a 'nop'
1364 instruction if the cpu does not implement the feature.
1366 config ARM64_LSE_ATOMICS
1367 bool "Atomic instructions"
1368 depends on JUMP_LABEL
1371 As part of the Large System Extensions, ARMv8.1 introduces new
1372 atomic instructions that are designed specifically to scale in
1375 Say Y here to make use of these instructions for the in-kernel
1376 atomic routines. This incurs a small overhead on CPUs that do
1377 not support these instructions and requires the kernel to be
1378 built with binutils >= 2.25 in order for the new instructions
1382 bool "Enable support for Virtualization Host Extensions (VHE)"
1385 Virtualization Host Extensions (VHE) allow the kernel to run
1386 directly at EL2 (instead of EL1) on processors that support
1387 it. This leads to better performance for KVM, as they reduce
1388 the cost of the world switch.
1390 Selecting this option allows the VHE feature to be detected
1391 at runtime, and does not affect processors that do not
1392 implement this feature.
1396 menu "ARMv8.2 architectural features"
1399 bool "Enable support for User Access Override (UAO)"
1402 User Access Override (UAO; part of the ARMv8.2 Extensions)
1403 causes the 'unprivileged' variant of the load/store instructions to
1404 be overridden to be privileged.
1406 This option changes get_user() and friends to use the 'unprivileged'
1407 variant of the load/store instructions. This ensures that user-space
1408 really did have access to the supplied memory. When addr_limit is
1409 set to kernel memory the UAO bit will be set, allowing privileged
1410 access to kernel memory.
1412 Choosing this option will cause copy_to_user() et al to use user-space
1415 The feature is detected at runtime, the kernel will use the
1416 regular load/store instructions if the cpu does not implement the
1420 bool "Enable support for persistent memory"
1421 select ARCH_HAS_PMEM_API
1422 select ARCH_HAS_UACCESS_FLUSHCACHE
1424 Say Y to enable support for the persistent memory API based on the
1425 ARMv8.2 DCPoP feature.
1427 The feature is detected at runtime, and the kernel will use DC CVAC
1428 operations if DC CVAP is not supported (following the behaviour of
1429 DC CVAP itself if the system does not define a point of persistence).
1431 config ARM64_RAS_EXTN
1432 bool "Enable support for RAS CPU Extensions"
1435 CPUs that support the Reliability, Availability and Serviceability
1436 (RAS) Extensions, part of ARMv8.2 are able to track faults and
1437 errors, classify them and report them to software.
1439 On CPUs with these extensions system software can use additional
1440 barriers to determine if faults are pending and read the
1441 classification from a new set of registers.
1443 Selecting this feature will allow the kernel to use these barriers
1444 and access the new registers if the system supports the extension.
1445 Platform RAS features may additionally depend on firmware support.
1448 bool "Enable support for Common Not Private (CNP) translations"
1450 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
1452 Common Not Private (CNP) allows translation table entries to
1453 be shared between different PEs in the same inner shareable
1454 domain, so the hardware can use this fact to optimise the
1455 caching of such entries in the TLB.
1457 Selecting this option allows the CNP feature to be detected
1458 at runtime, and does not affect PEs that do not implement
1463 menu "ARMv8.3 architectural features"
1465 config ARM64_PTR_AUTH
1466 bool "Enable support for pointer authentication"
1468 depends on !KVM || ARM64_VHE
1470 Pointer authentication (part of the ARMv8.3 Extensions) provides
1471 instructions for signing and authenticating pointers against secret
1472 keys, which can be used to mitigate Return Oriented Programming (ROP)
1475 This option enables these instructions at EL0 (i.e. for userspace).
1477 Choosing this option will cause the kernel to initialise secret keys
1478 for each process at exec() time, with these keys being
1479 context-switched along with the process.
1481 The feature is detected at runtime. If the feature is not present in
1482 hardware it will not be advertised to userspace/KVM guest nor will it
1483 be enabled. However, KVM guest also require VHE mode and hence
1484 CONFIG_ARM64_VHE=y option to use this feature.
1489 bool "ARM Scalable Vector Extension support"
1491 depends on !KVM || ARM64_VHE
1493 The Scalable Vector Extension (SVE) is an extension to the AArch64
1494 execution state which complements and extends the SIMD functionality
1495 of the base architecture to support much larger vectors and to enable
1496 additional vectorisation opportunities.
1498 To enable use of this extension on CPUs that implement it, say Y.
1500 On CPUs that support the SVE2 extensions, this option will enable
1503 Note that for architectural reasons, firmware _must_ implement SVE
1504 support when running on SVE capable hardware. The required support
1507 * version 1.5 and later of the ARM Trusted Firmware
1508 * the AArch64 boot wrapper since commit 5e1261e08abf
1509 ("bootwrapper: SVE: Enable SVE for EL2 and below").
1511 For other firmware implementations, consult the firmware documentation
1514 If you need the kernel to boot on SVE-capable hardware with broken
1515 firmware, you may need to say N here until you get your firmware
1516 fixed. Otherwise, you may experience firmware panics or lockups when
1517 booting the kernel. If unsure and you are not observing these
1518 symptoms, you should assume that it is safe to say Y.
1520 CPUs that support SVE are architecturally required to support the
1521 Virtualization Host Extensions (VHE), so the kernel makes no
1522 provision for supporting SVE alongside KVM without VHE enabled.
1523 Thus, you will need to enable CONFIG_ARM64_VHE if you want to support
1524 KVM in the same kernel image.
1526 config ARM64_MODULE_PLTS
1527 bool "Use PLTs to allow module memory to spill over into vmalloc area"
1529 select HAVE_MOD_ARCH_SPECIFIC
1531 Allocate PLTs when loading modules so that jumps and calls whose
1532 targets are too far away for their relative offsets to be encoded
1533 in the instructions themselves can be bounced via veneers in the
1534 module's PLT. This allows modules to be allocated in the generic
1535 vmalloc area after the dedicated module memory area has been
1538 When running with address space randomization (KASLR), the module
1539 region itself may be too far away for ordinary relative jumps and
1540 calls, and so in that case, module PLTs are required and cannot be
1543 Specific errata workaround(s) might also force module PLTs to be
1544 enabled (ARM64_ERRATUM_843419).
1546 config ARM64_PSEUDO_NMI
1547 bool "Support for NMI-like interrupts"
1548 select CONFIG_ARM_GIC_V3
1550 Adds support for mimicking Non-Maskable Interrupts through the use of
1551 GIC interrupt priority. This support requires version 3 or later of
1554 This high priority configuration for interrupts needs to be
1555 explicitly enabled by setting the kernel parameter
1556 "irqchip.gicv3_pseudo_nmi" to 1.
1561 config ARM64_DEBUG_PRIORITY_MASKING
1562 bool "Debug interrupt priority masking"
1564 This adds runtime checks to functions enabling/disabling
1565 interrupts when using priority masking. The additional checks verify
1566 the validity of ICC_PMR_EL1 when calling concerned functions.
1573 select ARCH_HAS_RELR
1575 This builds the kernel as a Position Independent Executable (PIE),
1576 which retains all relocation metadata required to relocate the
1577 kernel binary at runtime to a different virtual address than the
1578 address it was linked at.
1579 Since AArch64 uses the RELA relocation format, this requires a
1580 relocation pass at runtime even if the kernel is loaded at the
1581 same address it was linked at.
1583 config RANDOMIZE_BASE
1584 bool "Randomize the address of the kernel image"
1585 select ARM64_MODULE_PLTS if MODULES
1588 Randomizes the virtual address at which the kernel image is
1589 loaded, as a security feature that deters exploit attempts
1590 relying on knowledge of the location of kernel internals.
1592 It is the bootloader's job to provide entropy, by passing a
1593 random u64 value in /chosen/kaslr-seed at kernel entry.
1595 When booting via the UEFI stub, it will invoke the firmware's
1596 EFI_RNG_PROTOCOL implementation (if available) to supply entropy
1597 to the kernel proper. In addition, it will randomise the physical
1598 location of the kernel Image as well.
1602 config RANDOMIZE_MODULE_REGION_FULL
1603 bool "Randomize the module region over a 4 GB range"
1604 depends on RANDOMIZE_BASE
1607 Randomizes the location of the module region inside a 4 GB window
1608 covering the core kernel. This way, it is less likely for modules
1609 to leak information about the location of core kernel data structures
1610 but it does imply that function calls between modules and the core
1611 kernel will need to be resolved via veneers in the module PLT.
1613 When this option is not set, the module region will be randomized over
1614 a limited range that contains the [_stext, _etext] interval of the
1615 core kernel, so branch relocations are always in range.
1617 config CC_HAVE_STACKPROTECTOR_SYSREG
1618 def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0)
1620 config STACKPROTECTOR_PER_TASK
1622 depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG
1628 config ARM64_ACPI_PARKING_PROTOCOL
1629 bool "Enable support for the ARM64 ACPI parking protocol"
1632 Enable support for the ARM64 ACPI parking protocol. If disabled
1633 the kernel will not allow booting through the ARM64 ACPI parking
1634 protocol even if the corresponding data is present in the ACPI
1638 string "Default kernel command string"
1641 Provide a set of default command-line options at build time by
1642 entering them here. As a minimum, you should specify the the
1643 root device (e.g. root=/dev/nfs).
1645 config CMDLINE_FORCE
1646 bool "Always use the default kernel command string"
1647 depends on CMDLINE != ""
1649 Always use the default kernel command string, even if the boot
1650 loader passes other arguments to the kernel.
1651 This is useful if you cannot or don't want to change the
1652 command-line options your boot loader passes to the kernel.
1658 bool "UEFI runtime support"
1659 depends on OF && !CPU_BIG_ENDIAN
1660 depends on KERNEL_MODE_NEON
1661 select ARCH_SUPPORTS_ACPI
1664 select EFI_PARAMS_FROM_FDT
1665 select EFI_RUNTIME_WRAPPERS
1670 This option provides support for runtime services provided
1671 by UEFI firmware (such as non-volatile variables, realtime
1672 clock, and platform reset). A UEFI stub is also provided to
1673 allow the kernel to be booted as an EFI application. This
1674 is only useful on systems that have UEFI firmware.
1677 bool "Enable support for SMBIOS (DMI) tables"
1681 This enables SMBIOS/DMI feature for systems.
1683 This option is only useful on systems that have UEFI firmware.
1684 However, even with this option, the resultant kernel should
1685 continue to boot on existing non-UEFI platforms.
1689 config SYSVIPC_COMPAT
1691 depends on COMPAT && SYSVIPC
1693 config ARCH_ENABLE_HUGEPAGE_MIGRATION
1695 depends on HUGETLB_PAGE && MIGRATION
1697 menu "Power management options"
1699 source "kernel/power/Kconfig"
1701 config ARCH_HIBERNATION_POSSIBLE
1705 config ARCH_HIBERNATION_HEADER
1707 depends on HIBERNATION
1709 config ARCH_SUSPEND_POSSIBLE
1714 menu "CPU Power Management"
1716 source "drivers/cpuidle/Kconfig"
1718 source "drivers/cpufreq/Kconfig"
1722 source "drivers/firmware/Kconfig"
1724 source "drivers/acpi/Kconfig"
1726 source "arch/arm64/kvm/Kconfig"
1729 source "arch/arm64/crypto/Kconfig"