3 select ACPI_CCA_REQUIRED if ACPI
4 select ACPI_GENERIC_GSI if ACPI
5 select ACPI_GTDT if ACPI
6 select ACPI_IORT if ACPI
7 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
8 select ACPI_MCFG if ACPI
9 select ACPI_SPCR_TABLE if ACPI
10 select ACPI_PPTT if ACPI
11 select ARCH_CLOCKSOURCE_DATA
12 select ARCH_HAS_DEBUG_VIRTUAL
13 select ARCH_HAS_DEVMEM_IS_ALLOWED
14 select ARCH_HAS_DMA_COHERENT_TO_PFN
15 select ARCH_HAS_DMA_MMAP_PGPROT
16 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
17 select ARCH_HAS_ELF_RANDOMIZE
18 select ARCH_HAS_FAST_MULTIPLIER
19 select ARCH_HAS_FORTIFY_SOURCE
20 select ARCH_HAS_GCOV_PROFILE_ALL
21 select ARCH_HAS_GIGANTIC_PAGE if (MEMORY_ISOLATION && COMPACTION) || CMA
23 select ARCH_HAS_MEMBARRIER_SYNC_CORE
24 select ARCH_HAS_PTE_SPECIAL
25 select ARCH_HAS_SET_MEMORY
26 select ARCH_HAS_SG_CHAIN
27 select ARCH_HAS_STRICT_KERNEL_RWX
28 select ARCH_HAS_STRICT_MODULE_RWX
29 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
30 select ARCH_HAS_SYNC_DMA_FOR_CPU
31 select ARCH_HAS_SYSCALL_WRAPPER
32 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
33 select ARCH_HAVE_NMI_SAFE_CMPXCHG
34 select ARCH_INLINE_READ_LOCK if !PREEMPT
35 select ARCH_INLINE_READ_LOCK_BH if !PREEMPT
36 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPT
37 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPT
38 select ARCH_INLINE_READ_UNLOCK if !PREEMPT
39 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPT
40 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPT
41 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPT
42 select ARCH_INLINE_WRITE_LOCK if !PREEMPT
43 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPT
44 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPT
45 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPT
46 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPT
47 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPT
48 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPT
49 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPT
50 select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPT
51 select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPT
52 select ARCH_INLINE_SPIN_LOCK if !PREEMPT
53 select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPT
54 select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPT
55 select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPT
56 select ARCH_INLINE_SPIN_UNLOCK if !PREEMPT
57 select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPT
58 select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPT
59 select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPT
60 select ARCH_USE_CMPXCHG_LOCKREF
61 select ARCH_USE_QUEUED_RWLOCKS
62 select ARCH_USE_QUEUED_SPINLOCKS
63 select ARCH_SUPPORTS_MEMORY_FAILURE
64 select ARCH_SUPPORTS_ATOMIC_RMW
65 select ARCH_SUPPORTS_INT128 if GCC_VERSION >= 50000 || CC_IS_CLANG
66 select ARCH_SUPPORTS_NUMA_BALANCING
67 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
68 select ARCH_WANT_FRAME_POINTERS
69 select ARCH_HAS_UBSAN_SANITIZE_ALL
73 select AUDIT_ARCH_COMPAT_GENERIC
74 select ARM_GIC_V2M if PCI
76 select ARM_GIC_V3_ITS if PCI
78 select BUILDTIME_EXTABLE_SORT
79 select CLONE_BACKWARDS
81 select CPU_PM if (SUSPEND || CPU_IDLE)
83 select DCACHE_WORD_ACCESS
87 select GENERIC_ALLOCATOR
88 select GENERIC_ARCH_TOPOLOGY
89 select GENERIC_CLOCKEVENTS
90 select GENERIC_CLOCKEVENTS_BROADCAST
91 select GENERIC_CPU_AUTOPROBE
92 select GENERIC_EARLY_IOREMAP
93 select GENERIC_IDLE_POLL_SETUP
94 select GENERIC_IRQ_MULTI_HANDLER
95 select GENERIC_IRQ_PROBE
96 select GENERIC_IRQ_SHOW
97 select GENERIC_IRQ_SHOW_LEVEL
98 select GENERIC_PCI_IOMAP
99 select GENERIC_SCHED_CLOCK
100 select GENERIC_SMP_IDLE_THREAD
101 select GENERIC_STRNCPY_FROM_USER
102 select GENERIC_STRNLEN_USER
103 select GENERIC_TIME_VSYSCALL
104 select HANDLE_DOMAIN_IRQ
105 select HARDIRQS_SW_RESEND
107 select HAVE_ACPI_APEI if (ACPI && EFI)
108 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
109 select HAVE_ARCH_AUDITSYSCALL
110 select HAVE_ARCH_BITREVERSE
111 select HAVE_ARCH_HUGE_VMAP
112 select HAVE_ARCH_JUMP_LABEL
113 select HAVE_ARCH_JUMP_LABEL_RELATIVE
114 select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
115 select HAVE_ARCH_KGDB
116 select HAVE_ARCH_MMAP_RND_BITS
117 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
118 select HAVE_ARCH_PREL32_RELOCATIONS
119 select HAVE_ARCH_SECCOMP_FILTER
120 select HAVE_ARCH_STACKLEAK
121 select HAVE_ARCH_THREAD_STRUCT_WHITELIST
122 select HAVE_ARCH_TRACEHOOK
123 select HAVE_ARCH_TRANSPARENT_HUGEPAGE
124 select HAVE_ARCH_VMAP_STACK
125 select HAVE_ARM_SMCCC
127 select HAVE_C_RECORDMCOUNT
128 select HAVE_CMPXCHG_DOUBLE
129 select HAVE_CMPXCHG_LOCAL
130 select HAVE_CONTEXT_TRACKING
131 select HAVE_DEBUG_BUGVERBOSE
132 select HAVE_DEBUG_KMEMLEAK
133 select HAVE_DMA_CONTIGUOUS
134 select HAVE_DYNAMIC_FTRACE
135 select HAVE_EFFICIENT_UNALIGNED_ACCESS
136 select HAVE_FTRACE_MCOUNT_RECORD
137 select HAVE_FUNCTION_TRACER
138 select HAVE_FUNCTION_GRAPH_TRACER
139 select HAVE_GCC_PLUGINS
140 select HAVE_GENERIC_DMA_COHERENT
141 select HAVE_HW_BREAKPOINT if PERF_EVENTS
142 select HAVE_IRQ_TIME_ACCOUNTING
143 select HAVE_MEMBLOCK_NODE_MAP if NUMA
145 select HAVE_PATA_PLATFORM
146 select HAVE_PERF_EVENTS
147 select HAVE_PERF_REGS
148 select HAVE_PERF_USER_STACK_DUMP
149 select HAVE_REGS_AND_STACK_ACCESS_API
150 select HAVE_RCU_TABLE_FREE
151 select HAVE_RCU_TABLE_INVALIDATE
153 select HAVE_STACKPROTECTOR
154 select HAVE_SYSCALL_TRACEPOINTS
156 select HAVE_KRETPROBES
157 select IOMMU_DMA if IOMMU_SUPPORT
159 select IRQ_FORCED_THREADING
160 select MODULES_USE_ELF_RELA
161 select MULTI_IRQ_HANDLER
162 select NEED_DMA_MAP_STATE
163 select NEED_SG_DMA_LENGTH
165 select OF_EARLY_FLATTREE
166 select OF_RESERVED_MEM
167 select PCI_ECAM if ACPI
173 select SYSCTL_EXCEPTION_TRACE
174 select THREAD_INFO_IN_TASK
176 ARM 64-bit (AArch64) Linux support.
184 config ARM64_PAGE_SHIFT
186 default 16 if ARM64_64K_PAGES
187 default 14 if ARM64_16K_PAGES
190 config ARM64_CONT_SHIFT
192 default 5 if ARM64_64K_PAGES
193 default 7 if ARM64_16K_PAGES
196 config ARCH_MMAP_RND_BITS_MIN
197 default 14 if ARM64_64K_PAGES
198 default 16 if ARM64_16K_PAGES
201 # max bits determined by the following formula:
202 # VA_BITS - PAGE_SHIFT - 3
203 config ARCH_MMAP_RND_BITS_MAX
204 default 19 if ARM64_VA_BITS=36
205 default 24 if ARM64_VA_BITS=39
206 default 27 if ARM64_VA_BITS=42
207 default 30 if ARM64_VA_BITS=47
208 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
209 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
210 default 33 if ARM64_VA_BITS=48
211 default 14 if ARM64_64K_PAGES
212 default 16 if ARM64_16K_PAGES
215 config ARCH_MMAP_RND_COMPAT_BITS_MIN
216 default 7 if ARM64_64K_PAGES
217 default 9 if ARM64_16K_PAGES
220 config ARCH_MMAP_RND_COMPAT_BITS_MAX
226 config STACKTRACE_SUPPORT
229 config ILLEGAL_POINTER_VALUE
231 default 0xdead000000000000
233 config LOCKDEP_SUPPORT
236 config TRACE_IRQFLAGS_SUPPORT
239 config RWSEM_XCHGADD_ALGORITHM
246 config GENERIC_BUG_RELATIVE_POINTERS
248 depends on GENERIC_BUG
250 config GENERIC_HWEIGHT
256 config GENERIC_CALIBRATE_DELAY
262 config HAVE_GENERIC_GUP
268 config KERNEL_MODE_NEON
271 config FIX_EARLYCON_MEM
274 config PGTABLE_LEVELS
276 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
277 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
278 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
279 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
280 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
281 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
283 config ARCH_SUPPORTS_UPROBES
286 config ARCH_PROC_KCORE_TEXT
289 source "arch/arm64/Kconfig.platforms"
294 config PCI_DOMAINS_GENERIC
300 menu "Kernel Features"
302 menu "ARM errata workarounds via the alternatives framework"
304 config ARM64_ERRATUM_826319
305 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
308 This option adds an alternative code sequence to work around ARM
309 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
310 AXI master interface and an L2 cache.
312 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
313 and is unable to accept a certain write via this interface, it will
314 not progress on read data presented on the read data channel and the
317 The workaround promotes data cache clean instructions to
318 data cache clean-and-invalidate.
319 Please note that this does not necessarily enable the workaround,
320 as it depends on the alternative framework, which will only patch
321 the kernel if an affected CPU is detected.
325 config ARM64_ERRATUM_827319
326 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
329 This option adds an alternative code sequence to work around ARM
330 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
331 master interface and an L2 cache.
333 Under certain conditions this erratum can cause a clean line eviction
334 to occur at the same time as another transaction to the same address
335 on the AMBA 5 CHI interface, which can cause data corruption if the
336 interconnect reorders the two transactions.
338 The workaround promotes data cache clean instructions to
339 data cache clean-and-invalidate.
340 Please note that this does not necessarily enable the workaround,
341 as it depends on the alternative framework, which will only patch
342 the kernel if an affected CPU is detected.
346 config ARM64_ERRATUM_824069
347 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
350 This option adds an alternative code sequence to work around ARM
351 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
352 to a coherent interconnect.
354 If a Cortex-A53 processor is executing a store or prefetch for
355 write instruction at the same time as a processor in another
356 cluster is executing a cache maintenance operation to the same
357 address, then this erratum might cause a clean cache line to be
358 incorrectly marked as dirty.
360 The workaround promotes data cache clean instructions to
361 data cache clean-and-invalidate.
362 Please note that this option does not necessarily enable the
363 workaround, as it depends on the alternative framework, which will
364 only patch the kernel if an affected CPU is detected.
368 config ARM64_ERRATUM_819472
369 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
372 This option adds an alternative code sequence to work around ARM
373 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
374 present when it is connected to a coherent interconnect.
376 If the processor is executing a load and store exclusive sequence at
377 the same time as a processor in another cluster is executing a cache
378 maintenance operation to the same address, then this erratum might
379 cause data corruption.
381 The workaround promotes data cache clean instructions to
382 data cache clean-and-invalidate.
383 Please note that this does not necessarily enable the workaround,
384 as it depends on the alternative framework, which will only patch
385 the kernel if an affected CPU is detected.
389 config ARM64_ERRATUM_832075
390 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
393 This option adds an alternative code sequence to work around ARM
394 erratum 832075 on Cortex-A57 parts up to r1p2.
396 Affected Cortex-A57 parts might deadlock when exclusive load/store
397 instructions to Write-Back memory are mixed with Device loads.
399 The workaround is to promote device loads to use Load-Acquire
401 Please note that this does not necessarily enable the workaround,
402 as it depends on the alternative framework, which will only patch
403 the kernel if an affected CPU is detected.
407 config ARM64_ERRATUM_834220
408 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
412 This option adds an alternative code sequence to work around ARM
413 erratum 834220 on Cortex-A57 parts up to r1p2.
415 Affected Cortex-A57 parts might report a Stage 2 translation
416 fault as the result of a Stage 1 fault for load crossing a
417 page boundary when there is a permission or device memory
418 alignment fault at Stage 1 and a translation fault at Stage 2.
420 The workaround is to verify that the Stage 1 translation
421 doesn't generate a fault before handling the Stage 2 fault.
422 Please note that this does not necessarily enable the workaround,
423 as it depends on the alternative framework, which will only patch
424 the kernel if an affected CPU is detected.
428 config ARM64_ERRATUM_845719
429 bool "Cortex-A53: 845719: a load might read incorrect data"
433 This option adds an alternative code sequence to work around ARM
434 erratum 845719 on Cortex-A53 parts up to r0p4.
436 When running a compat (AArch32) userspace on an affected Cortex-A53
437 part, a load at EL0 from a virtual address that matches the bottom 32
438 bits of the virtual address used by a recent load at (AArch64) EL1
439 might return incorrect data.
441 The workaround is to write the contextidr_el1 register on exception
442 return to a 32-bit task.
443 Please note that this does not necessarily enable the workaround,
444 as it depends on the alternative framework, which will only patch
445 the kernel if an affected CPU is detected.
449 config ARM64_ERRATUM_843419
450 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
452 select ARM64_MODULE_PLTS if MODULES
454 This option links the kernel with '--fix-cortex-a53-843419' and
455 enables PLT support to replace certain ADRP instructions, which can
456 cause subsequent memory accesses to use an incorrect address on
457 Cortex-A53 parts up to r0p4.
461 config ARM64_ERRATUM_1024718
462 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update"
465 This option adds work around for Arm Cortex-A55 Erratum 1024718.
467 Affected Cortex-A55 cores (r0p0, r0p1, r1p0) could cause incorrect
468 update of the hardware dirty bit when the DBM/AP bits are updated
469 without a break-before-make. The work around is to disable the usage
470 of hardware DBM locally on the affected cores. CPUs not affected by
471 erratum will continue to use the feature.
475 config ARM64_ERRATUM_1188873
476 bool "Cortex-A76: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result"
478 select ARM_ARCH_TIMER_OOL_WORKAROUND
480 This option adds work arounds for ARM Cortex-A76 erratum 1188873
482 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could cause
483 register corruption when accessing the timer registers from
488 config CAVIUM_ERRATUM_22375
489 bool "Cavium erratum 22375, 24313"
492 Enable workaround for erratum 22375, 24313.
494 This implements two gicv3-its errata workarounds for ThunderX. Both
495 with small impact affecting only ITS table allocation.
497 erratum 22375: only alloc 8MB table size
498 erratum 24313: ignore memory access type
500 The fixes are in ITS initialization and basically ignore memory access
501 type and table size provided by the TYPER and BASER registers.
505 config CAVIUM_ERRATUM_23144
506 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
510 ITS SYNC command hang for cross node io and collections/cpu mapping.
514 config CAVIUM_ERRATUM_23154
515 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
518 The gicv3 of ThunderX requires a modified version for
519 reading the IAR status to ensure data synchronization
520 (access to icc_iar1_el1 is not sync'ed before and after).
524 config CAVIUM_ERRATUM_27456
525 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
528 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
529 instructions may cause the icache to become corrupted if it
530 contains data for a non-current ASID. The fix is to
531 invalidate the icache when changing the mm context.
535 config CAVIUM_ERRATUM_30115
536 bool "Cavium erratum 30115: Guest may disable interrupts in host"
539 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through
540 1.2, and T83 Pass 1.0, KVM guest execution may disable
541 interrupts in host. Trapping both GICv3 group-0 and group-1
542 accesses sidesteps the issue.
546 config QCOM_FALKOR_ERRATUM_1003
547 bool "Falkor E1003: Incorrect translation due to ASID change"
550 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
551 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID
552 in TTBR1_EL1, this situation only occurs in the entry trampoline and
553 then only for entries in the walk cache, since the leaf translation
554 is unchanged. Work around the erratum by invalidating the walk cache
555 entries for the trampoline before entering the kernel proper.
557 config QCOM_FALKOR_ERRATUM_1009
558 bool "Falkor E1009: Prematurely complete a DSB after a TLBI"
561 On Falkor v1, the CPU may prematurely complete a DSB following a
562 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation
563 one more time to fix the issue.
567 config QCOM_QDF2400_ERRATUM_0065
568 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size"
571 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports
572 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have
573 been indicated as 16Bytes (0xf), not 8Bytes (0x7).
577 config SOCIONEXT_SYNQUACER_PREITS
578 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
581 Socionext Synquacer SoCs implement a separate h/w block to generate
582 MSI doorbell writes with non-zero values for the device ID.
586 config HISILICON_ERRATUM_161600802
587 bool "Hip07 161600802: Erroneous redistributor VLPI base"
590 The HiSilicon Hip07 SoC usees the wrong redistributor base
591 when issued ITS commands such as VMOVP and VMAPP, and requires
592 a 128kB offset to be applied to the target address in this commands.
596 config QCOM_FALKOR_ERRATUM_E1041
597 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access"
600 Falkor CPU may speculatively fetch instructions from an improper
601 memory location when MMU translation is changed from SCTLR_ELn[M]=1
602 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem.
611 default ARM64_4K_PAGES
613 Page size (translation granule) configuration.
615 config ARM64_4K_PAGES
618 This feature enables 4KB pages support.
620 config ARM64_16K_PAGES
623 The system will use 16KB pages support. AArch32 emulation
624 requires applications compiled with 16K (or a multiple of 16K)
627 config ARM64_64K_PAGES
630 This feature enables 64KB pages support (4KB by default)
631 allowing only two levels of page tables and faster TLB
632 look-up. AArch32 emulation requires applications compiled
633 with 64K aligned segments.
638 prompt "Virtual address space size"
639 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
640 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
641 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
643 Allows choosing one of multiple possible virtual address
644 space sizes. The level of translation table is determined by
645 a combination of page size and virtual address space size.
647 config ARM64_VA_BITS_36
648 bool "36-bit" if EXPERT
649 depends on ARM64_16K_PAGES
651 config ARM64_VA_BITS_39
653 depends on ARM64_4K_PAGES
655 config ARM64_VA_BITS_42
657 depends on ARM64_64K_PAGES
659 config ARM64_VA_BITS_47
661 depends on ARM64_16K_PAGES
663 config ARM64_VA_BITS_48
670 default 36 if ARM64_VA_BITS_36
671 default 39 if ARM64_VA_BITS_39
672 default 42 if ARM64_VA_BITS_42
673 default 47 if ARM64_VA_BITS_47
674 default 48 if ARM64_VA_BITS_48
677 prompt "Physical address space size"
678 default ARM64_PA_BITS_48
680 Choose the maximum physical address range that the kernel will
683 config ARM64_PA_BITS_48
686 config ARM64_PA_BITS_52
687 bool "52-bit (ARMv8.2)"
688 depends on ARM64_64K_PAGES
689 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
691 Enable support for a 52-bit physical address space, introduced as
692 part of the ARMv8.2-LPA extension.
694 With this enabled, the kernel will also continue to work on CPUs that
695 do not support ARMv8.2-LPA, but with some added memory overhead (and
696 minor performance overhead).
702 default 48 if ARM64_PA_BITS_48
703 default 52 if ARM64_PA_BITS_52
705 config CPU_BIG_ENDIAN
706 bool "Build big-endian kernel"
708 Say Y if you plan on running a kernel in big-endian mode.
711 bool "Multi-core scheduler support"
713 Multi-core scheduler support improves the CPU scheduler's decision
714 making when dealing with multi-core CPU chips at a cost of slightly
715 increased overhead in some places. If unsure say N here.
718 bool "SMT scheduler support"
720 Improves the CPU scheduler's decision making when dealing with
721 MultiThreading at a cost of slightly increased overhead in some
722 places. If unsure say N here.
725 int "Maximum number of CPUs (2-4096)"
727 # These have to remain sorted largest to smallest
731 bool "Support for hot-pluggable CPUs"
732 select GENERIC_IRQ_MIGRATION
734 Say Y here to experiment with turning CPUs off and on. CPUs
735 can be controlled through /sys/devices/system/cpu.
737 # Common NUMA Features
739 bool "Numa Memory Allocation and Scheduler Support"
740 select ACPI_NUMA if ACPI
743 Enable NUMA (Non Uniform Memory Access) support.
745 The kernel will try to allocate memory used by a CPU on the
746 local memory of the CPU and add some more
747 NUMA awareness to the kernel.
750 int "Maximum NUMA Nodes (as a power of 2)"
753 depends on NEED_MULTIPLE_NODES
755 Specify the maximum number of NUMA Nodes available on the target
756 system. Increases memory reserved to accommodate various tables.
758 config USE_PERCPU_NUMA_NODE_ID
762 config HAVE_SETUP_PER_CPU_AREA
766 config NEED_PER_CPU_EMBED_FIRST_CHUNK
773 source kernel/Kconfig.hz
775 config ARCH_SUPPORTS_DEBUG_PAGEALLOC
778 config ARCH_SPARSEMEM_ENABLE
780 select SPARSEMEM_VMEMMAP_ENABLE
782 config ARCH_SPARSEMEM_DEFAULT
783 def_bool ARCH_SPARSEMEM_ENABLE
785 config ARCH_SELECT_MEMORY_MODEL
786 def_bool ARCH_SPARSEMEM_ENABLE
788 config ARCH_FLATMEM_ENABLE
791 config HAVE_ARCH_PFN_VALID
794 config HW_PERF_EVENTS
798 config SYS_SUPPORTS_HUGETLBFS
801 config ARCH_WANT_HUGE_PMD_SHARE
802 def_bool y if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
804 config ARCH_HAS_CACHE_LINE_SIZE
808 bool "Enable seccomp to safely compute untrusted bytecode"
810 This kernel feature is useful for number crunching applications
811 that may need to compute untrusted bytecode during their
812 execution. By using pipes or other transports made available to
813 the process as file descriptors supporting the read/write
814 syscalls, it's possible to isolate those applications in
815 their own address space using seccomp. Once seccomp is
816 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
817 and the task is only allowed to execute a few safe syscalls
818 defined by each seccomp mode.
821 bool "Enable paravirtualization code"
823 This changes the kernel so it can modify itself when it is run
824 under a hypervisor, potentially improving performance significantly
825 over full virtualization.
827 config PARAVIRT_TIME_ACCOUNTING
828 bool "Paravirtual steal time accounting"
832 Select this option to enable fine granularity task steal time
833 accounting. Time spent executing other tasks in parallel with
834 the current vCPU is discounted from the vCPU power. To account for
835 that, there can be a small performance impact.
837 If in doubt, say N here.
840 depends on PM_SLEEP_SMP
842 bool "kexec system call"
844 kexec is a system call that implements the ability to shutdown your
845 current kernel, and to start another kernel. It is like a reboot
846 but it is independent of the system firmware. And like a reboot
847 you can start any kernel with it, not just Linux.
850 bool "Build kdump crash kernel"
852 Generate crash dump after being started by kexec. This should
853 be normally only set in special crash dump kernels which are
854 loaded in the main kernel with kexec-tools into a specially
855 reserved region and then later executed after a crash by
858 For more details see Documentation/kdump/kdump.txt
865 bool "Xen guest support on ARM64"
866 depends on ARM64 && OF
870 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
872 config FORCE_MAX_ZONEORDER
874 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
875 default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE)
878 The kernel memory allocator divides physically contiguous memory
879 blocks into "zones", where each zone is a power of two number of
880 pages. This option selects the largest power of two that the kernel
881 keeps in the memory allocator. If you need to allocate very large
882 blocks of physically contiguous memory, then you may need to
885 This config option is actually maximum order plus one. For example,
886 a value of 11 means that the largest free memory block is 2^10 pages.
888 We make sure that we can allocate upto a HugePage size for each configuration.
890 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
892 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
893 4M allocations matching the default size used by generic code.
895 config UNMAP_KERNEL_AT_EL0
896 bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT
899 Speculation attacks against some high-performance processors can
900 be used to bypass MMU permission checks and leak kernel data to
901 userspace. This can be defended against by unmapping the kernel
902 when running in userspace, mapping it back in on exception entry
903 via a trampoline page in the vector table.
907 config HARDEN_BRANCH_PREDICTOR
908 bool "Harden the branch predictor against aliasing attacks" if EXPERT
911 Speculation attacks against some high-performance processors rely on
912 being able to manipulate the branch predictor for a victim context by
913 executing aliasing branches in the attacker context. Such attacks
914 can be partially mitigated against by clearing internal branch
915 predictor state and limiting the prediction logic in some situations.
917 This config option will take CPU-specific actions to harden the
918 branch predictor against aliasing attacks and may rely on specific
919 instruction sequences or control bits being set by the system
924 config HARDEN_EL2_VECTORS
925 bool "Harden EL2 vector mapping against system register leak" if EXPERT
928 Speculation attacks against some high-performance processors can
929 be used to leak privileged information such as the vector base
930 register, resulting in a potential defeat of the EL2 layout
933 This config option will map the vectors to a fixed location,
934 independent of the EL2 code mapping, so that revealing VBAR_EL2
935 to an attacker does not give away any extra information. This
936 only gets enabled on affected CPUs.
941 bool "Speculative Store Bypass Disable" if EXPERT
944 This enables mitigation of the bypassing of previous stores
945 by speculative loads.
949 menuconfig ARMV8_DEPRECATED
950 bool "Emulate deprecated/obsolete ARMv8 instructions"
954 Legacy software support may require certain instructions
955 that have been deprecated or obsoleted in the architecture.
957 Enable this config to enable selective emulation of these
965 bool "Emulate SWP/SWPB instructions"
967 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
968 they are always undefined. Say Y here to enable software
969 emulation of these instructions for userspace using LDXR/STXR.
971 In some older versions of glibc [<=2.8] SWP is used during futex
972 trylock() operations with the assumption that the code will not
973 be preempted. This invalid assumption may be more likely to fail
974 with SWP emulation enabled, leading to deadlock of the user
977 NOTE: when accessing uncached shared regions, LDXR/STXR rely
978 on an external transaction monitoring block called a global
979 monitor to maintain update atomicity. If your system does not
980 implement a global monitor, this option can cause programs that
981 perform SWP operations to uncached memory to deadlock.
985 config CP15_BARRIER_EMULATION
986 bool "Emulate CP15 Barrier instructions"
988 The CP15 barrier instructions - CP15ISB, CP15DSB, and
989 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
990 strongly recommended to use the ISB, DSB, and DMB
991 instructions instead.
993 Say Y here to enable software emulation of these
994 instructions for AArch32 userspace code. When this option is
995 enabled, CP15 barrier usage is traced which can help
996 identify software that needs updating.
1000 config SETEND_EMULATION
1001 bool "Emulate SETEND instruction"
1003 The SETEND instruction alters the data-endianness of the
1004 AArch32 EL0, and is deprecated in ARMv8.
1006 Say Y here to enable software emulation of the instruction
1007 for AArch32 userspace code.
1009 Note: All the cpus on the system must have mixed endian support at EL0
1010 for this feature to be enabled. If a new CPU - which doesn't support mixed
1011 endian - is hotplugged in after this feature has been enabled, there could
1012 be unexpected results in the applications.
1017 config ARM64_SW_TTBR0_PAN
1018 bool "Emulate Privileged Access Never using TTBR0_EL1 switching"
1020 Enabling this option prevents the kernel from accessing
1021 user-space memory directly by pointing TTBR0_EL1 to a reserved
1022 zeroed area and reserved ASID. The user access routines
1023 restore the valid TTBR0_EL1 temporarily.
1025 menu "ARMv8.1 architectural features"
1027 config ARM64_HW_AFDBM
1028 bool "Support for hardware updates of the Access and Dirty page flags"
1031 The ARMv8.1 architecture extensions introduce support for
1032 hardware updates of the access and dirty information in page
1033 table entries. When enabled in TCR_EL1 (HA and HD bits) on
1034 capable processors, accesses to pages with PTE_AF cleared will
1035 set this bit instead of raising an access flag fault.
1036 Similarly, writes to read-only pages with the DBM bit set will
1037 clear the read-only bit (AP[2]) instead of raising a
1040 Kernels built with this configuration option enabled continue
1041 to work on pre-ARMv8.1 hardware and the performance impact is
1042 minimal. If unsure, say Y.
1045 bool "Enable support for Privileged Access Never (PAN)"
1048 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
1049 prevents the kernel or hypervisor from accessing user-space (EL0)
1052 Choosing this option will cause any unprotected (not using
1053 copy_to_user et al) memory access to fail with a permission fault.
1055 The feature is detected at runtime, and will remain as a 'nop'
1056 instruction if the cpu does not implement the feature.
1058 config ARM64_LSE_ATOMICS
1059 bool "Atomic instructions"
1062 As part of the Large System Extensions, ARMv8.1 introduces new
1063 atomic instructions that are designed specifically to scale in
1066 Say Y here to make use of these instructions for the in-kernel
1067 atomic routines. This incurs a small overhead on CPUs that do
1068 not support these instructions and requires the kernel to be
1069 built with binutils >= 2.25 in order for the new instructions
1073 bool "Enable support for Virtualization Host Extensions (VHE)"
1076 Virtualization Host Extensions (VHE) allow the kernel to run
1077 directly at EL2 (instead of EL1) on processors that support
1078 it. This leads to better performance for KVM, as they reduce
1079 the cost of the world switch.
1081 Selecting this option allows the VHE feature to be detected
1082 at runtime, and does not affect processors that do not
1083 implement this feature.
1087 menu "ARMv8.2 architectural features"
1090 bool "Enable support for User Access Override (UAO)"
1093 User Access Override (UAO; part of the ARMv8.2 Extensions)
1094 causes the 'unprivileged' variant of the load/store instructions to
1095 be overridden to be privileged.
1097 This option changes get_user() and friends to use the 'unprivileged'
1098 variant of the load/store instructions. This ensures that user-space
1099 really did have access to the supplied memory. When addr_limit is
1100 set to kernel memory the UAO bit will be set, allowing privileged
1101 access to kernel memory.
1103 Choosing this option will cause copy_to_user() et al to use user-space
1106 The feature is detected at runtime, the kernel will use the
1107 regular load/store instructions if the cpu does not implement the
1111 bool "Enable support for persistent memory"
1112 select ARCH_HAS_PMEM_API
1113 select ARCH_HAS_UACCESS_FLUSHCACHE
1115 Say Y to enable support for the persistent memory API based on the
1116 ARMv8.2 DCPoP feature.
1118 The feature is detected at runtime, and the kernel will use DC CVAC
1119 operations if DC CVAP is not supported (following the behaviour of
1120 DC CVAP itself if the system does not define a point of persistence).
1122 config ARM64_RAS_EXTN
1123 bool "Enable support for RAS CPU Extensions"
1126 CPUs that support the Reliability, Availability and Serviceability
1127 (RAS) Extensions, part of ARMv8.2 are able to track faults and
1128 errors, classify them and report them to software.
1130 On CPUs with these extensions system software can use additional
1131 barriers to determine if faults are pending and read the
1132 classification from a new set of registers.
1134 Selecting this feature will allow the kernel to use these barriers
1135 and access the new registers if the system supports the extension.
1136 Platform RAS features may additionally depend on firmware support.
1139 bool "Enable support for Common Not Private (CNP) translations"
1141 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
1143 Common Not Private (CNP) allows translation table entries to
1144 be shared between different PEs in the same inner shareable
1145 domain, so the hardware can use this fact to optimise the
1146 caching of such entries in the TLB.
1148 Selecting this option allows the CNP feature to be detected
1149 at runtime, and does not affect PEs that do not implement
1155 bool "ARM Scalable Vector Extension support"
1157 depends on !KVM || ARM64_VHE
1159 The Scalable Vector Extension (SVE) is an extension to the AArch64
1160 execution state which complements and extends the SIMD functionality
1161 of the base architecture to support much larger vectors and to enable
1162 additional vectorisation opportunities.
1164 To enable use of this extension on CPUs that implement it, say Y.
1166 Note that for architectural reasons, firmware _must_ implement SVE
1167 support when running on SVE capable hardware. The required support
1170 * version 1.5 and later of the ARM Trusted Firmware
1171 * the AArch64 boot wrapper since commit 5e1261e08abf
1172 ("bootwrapper: SVE: Enable SVE for EL2 and below").
1174 For other firmware implementations, consult the firmware documentation
1177 If you need the kernel to boot on SVE-capable hardware with broken
1178 firmware, you may need to say N here until you get your firmware
1179 fixed. Otherwise, you may experience firmware panics or lockups when
1180 booting the kernel. If unsure and you are not observing these
1181 symptoms, you should assume that it is safe to say Y.
1183 CPUs that support SVE are architecturally required to support the
1184 Virtualization Host Extensions (VHE), so the kernel makes no
1185 provision for supporting SVE alongside KVM without VHE enabled.
1186 Thus, you will need to enable CONFIG_ARM64_VHE if you want to support
1187 KVM in the same kernel image.
1189 config ARM64_MODULE_PLTS
1191 select HAVE_MOD_ARCH_SPECIFIC
1196 This builds the kernel as a Position Independent Executable (PIE),
1197 which retains all relocation metadata required to relocate the
1198 kernel binary at runtime to a different virtual address than the
1199 address it was linked at.
1200 Since AArch64 uses the RELA relocation format, this requires a
1201 relocation pass at runtime even if the kernel is loaded at the
1202 same address it was linked at.
1204 config RANDOMIZE_BASE
1205 bool "Randomize the address of the kernel image"
1206 select ARM64_MODULE_PLTS if MODULES
1209 Randomizes the virtual address at which the kernel image is
1210 loaded, as a security feature that deters exploit attempts
1211 relying on knowledge of the location of kernel internals.
1213 It is the bootloader's job to provide entropy, by passing a
1214 random u64 value in /chosen/kaslr-seed at kernel entry.
1216 When booting via the UEFI stub, it will invoke the firmware's
1217 EFI_RNG_PROTOCOL implementation (if available) to supply entropy
1218 to the kernel proper. In addition, it will randomise the physical
1219 location of the kernel Image as well.
1223 config RANDOMIZE_MODULE_REGION_FULL
1224 bool "Randomize the module region over a 4 GB range"
1225 depends on RANDOMIZE_BASE
1228 Randomizes the location of the module region inside a 4 GB window
1229 covering the core kernel. This way, it is less likely for modules
1230 to leak information about the location of core kernel data structures
1231 but it does imply that function calls between modules and the core
1232 kernel will need to be resolved via veneers in the module PLT.
1234 When this option is not set, the module region will be randomized over
1235 a limited range that contains the [_stext, _etext] interval of the
1236 core kernel, so branch relocations are always in range.
1242 config ARM64_ACPI_PARKING_PROTOCOL
1243 bool "Enable support for the ARM64 ACPI parking protocol"
1246 Enable support for the ARM64 ACPI parking protocol. If disabled
1247 the kernel will not allow booting through the ARM64 ACPI parking
1248 protocol even if the corresponding data is present in the ACPI
1252 string "Default kernel command string"
1255 Provide a set of default command-line options at build time by
1256 entering them here. As a minimum, you should specify the the
1257 root device (e.g. root=/dev/nfs).
1259 config CMDLINE_FORCE
1260 bool "Always use the default kernel command string"
1262 Always use the default kernel command string, even if the boot
1263 loader passes other arguments to the kernel.
1264 This is useful if you cannot or don't want to change the
1265 command-line options your boot loader passes to the kernel.
1271 bool "UEFI runtime support"
1272 depends on OF && !CPU_BIG_ENDIAN
1273 depends on KERNEL_MODE_NEON
1274 select ARCH_SUPPORTS_ACPI
1277 select EFI_PARAMS_FROM_FDT
1278 select EFI_RUNTIME_WRAPPERS
1283 This option provides support for runtime services provided
1284 by UEFI firmware (such as non-volatile variables, realtime
1285 clock, and platform reset). A UEFI stub is also provided to
1286 allow the kernel to be booted as an EFI application. This
1287 is only useful on systems that have UEFI firmware.
1290 bool "Enable support for SMBIOS (DMI) tables"
1294 This enables SMBIOS/DMI feature for systems.
1296 This option is only useful on systems that have UEFI firmware.
1297 However, even with this option, the resultant kernel should
1298 continue to boot on existing non-UEFI platforms.
1303 bool "Kernel support for 32-bit EL0"
1304 depends on ARM64_4K_PAGES || EXPERT
1305 select COMPAT_BINFMT_ELF if BINFMT_ELF
1307 select OLD_SIGSUSPEND3
1308 select COMPAT_OLD_SIGACTION
1310 This option enables support for a 32-bit EL0 running under a 64-bit
1311 kernel at EL1. AArch32-specific components such as system calls,
1312 the user helper functions, VFP support and the ptrace interface are
1313 handled appropriately by the kernel.
1315 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
1316 that you will only be able to execute AArch32 binaries that were compiled
1317 with page size aligned segments.
1319 If you want to execute 32-bit userspace applications, say Y.
1321 config SYSVIPC_COMPAT
1323 depends on COMPAT && SYSVIPC
1325 menu "Power management options"
1327 source "kernel/power/Kconfig"
1329 config ARCH_HIBERNATION_POSSIBLE
1333 config ARCH_HIBERNATION_HEADER
1335 depends on HIBERNATION
1337 config ARCH_SUSPEND_POSSIBLE
1342 menu "CPU Power Management"
1344 source "drivers/cpuidle/Kconfig"
1346 source "drivers/cpufreq/Kconfig"
1350 source "drivers/firmware/Kconfig"
1352 source "drivers/acpi/Kconfig"
1354 source "arch/arm64/kvm/Kconfig"
1357 source "arch/arm64/crypto/Kconfig"