3 select ACPI_CCA_REQUIRED if ACPI
4 select ACPI_GENERIC_GSI if ACPI
5 select ACPI_GTDT if ACPI
6 select ACPI_IORT if ACPI
7 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
8 select ACPI_MCFG if ACPI
9 select ACPI_SPCR_TABLE if ACPI
10 select ACPI_PPTT if ACPI
11 select ARCH_CLOCKSOURCE_DATA
12 select ARCH_HAS_DEBUG_VIRTUAL
13 select ARCH_HAS_DEVMEM_IS_ALLOWED
14 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
15 select ARCH_HAS_ELF_RANDOMIZE
16 select ARCH_HAS_FAST_MULTIPLIER
17 select ARCH_HAS_FORTIFY_SOURCE
18 select ARCH_HAS_GCOV_PROFILE_ALL
19 select ARCH_HAS_GIGANTIC_PAGE if (MEMORY_ISOLATION && COMPACTION) || CMA
21 select ARCH_HAS_MEMBARRIER_SYNC_CORE
22 select ARCH_HAS_PTE_SPECIAL
23 select ARCH_HAS_SET_MEMORY
24 select ARCH_HAS_SG_CHAIN
25 select ARCH_HAS_STRICT_KERNEL_RWX
26 select ARCH_HAS_STRICT_MODULE_RWX
27 select ARCH_HAS_SYSCALL_WRAPPER
28 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
29 select ARCH_HAVE_NMI_SAFE_CMPXCHG
30 select ARCH_INLINE_READ_LOCK if !PREEMPT
31 select ARCH_INLINE_READ_LOCK_BH if !PREEMPT
32 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPT
33 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPT
34 select ARCH_INLINE_READ_UNLOCK if !PREEMPT
35 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPT
36 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPT
37 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPT
38 select ARCH_INLINE_WRITE_LOCK if !PREEMPT
39 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPT
40 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPT
41 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPT
42 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPT
43 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPT
44 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPT
45 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPT
46 select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPT
47 select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPT
48 select ARCH_INLINE_SPIN_LOCK if !PREEMPT
49 select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPT
50 select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPT
51 select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPT
52 select ARCH_INLINE_SPIN_UNLOCK if !PREEMPT
53 select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPT
54 select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPT
55 select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPT
56 select ARCH_USE_CMPXCHG_LOCKREF
57 select ARCH_USE_QUEUED_RWLOCKS
58 select ARCH_USE_QUEUED_SPINLOCKS
59 select ARCH_SUPPORTS_MEMORY_FAILURE
60 select ARCH_SUPPORTS_ATOMIC_RMW
61 select ARCH_SUPPORTS_INT128 if GCC_VERSION >= 50000 || CC_IS_CLANG
62 select ARCH_SUPPORTS_NUMA_BALANCING
63 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
64 select ARCH_WANT_FRAME_POINTERS
65 select ARCH_HAS_UBSAN_SANITIZE_ALL
69 select AUDIT_ARCH_COMPAT_GENERIC
70 select ARM_GIC_V2M if PCI
72 select ARM_GIC_V3_ITS if PCI
74 select BUILDTIME_EXTABLE_SORT
75 select CLONE_BACKWARDS
77 select CPU_PM if (SUSPEND || CPU_IDLE)
78 select DCACHE_WORD_ACCESS
82 select GENERIC_ALLOCATOR
83 select GENERIC_ARCH_TOPOLOGY
84 select GENERIC_CLOCKEVENTS
85 select GENERIC_CLOCKEVENTS_BROADCAST
86 select GENERIC_CPU_AUTOPROBE
87 select GENERIC_EARLY_IOREMAP
88 select GENERIC_IDLE_POLL_SETUP
89 select GENERIC_IRQ_MULTI_HANDLER
90 select GENERIC_IRQ_PROBE
91 select GENERIC_IRQ_SHOW
92 select GENERIC_IRQ_SHOW_LEVEL
93 select GENERIC_PCI_IOMAP
94 select GENERIC_SCHED_CLOCK
95 select GENERIC_SMP_IDLE_THREAD
96 select GENERIC_STRNCPY_FROM_USER
97 select GENERIC_STRNLEN_USER
98 select GENERIC_TIME_VSYSCALL
99 select HANDLE_DOMAIN_IRQ
100 select HARDIRQS_SW_RESEND
101 select HAVE_ACPI_APEI if (ACPI && EFI)
102 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
103 select HAVE_ARCH_AUDITSYSCALL
104 select HAVE_ARCH_BITREVERSE
105 select HAVE_ARCH_HUGE_VMAP
106 select HAVE_ARCH_JUMP_LABEL
107 select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
108 select HAVE_ARCH_KGDB
109 select HAVE_ARCH_MMAP_RND_BITS
110 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
111 select HAVE_ARCH_SECCOMP_FILTER
112 select HAVE_ARCH_STACKLEAK
113 select HAVE_ARCH_THREAD_STRUCT_WHITELIST
114 select HAVE_ARCH_TRACEHOOK
115 select HAVE_ARCH_TRANSPARENT_HUGEPAGE
116 select HAVE_ARCH_VMAP_STACK
117 select HAVE_ARM_SMCCC
119 select HAVE_C_RECORDMCOUNT
120 select HAVE_CMPXCHG_DOUBLE
121 select HAVE_CMPXCHG_LOCAL
122 select HAVE_CONTEXT_TRACKING
123 select HAVE_DEBUG_BUGVERBOSE
124 select HAVE_DEBUG_KMEMLEAK
125 select HAVE_DMA_CONTIGUOUS
126 select HAVE_DYNAMIC_FTRACE
127 select HAVE_EFFICIENT_UNALIGNED_ACCESS
128 select HAVE_FTRACE_MCOUNT_RECORD
129 select HAVE_FUNCTION_TRACER
130 select HAVE_FUNCTION_GRAPH_TRACER
131 select HAVE_GCC_PLUGINS
132 select HAVE_GENERIC_DMA_COHERENT
133 select HAVE_HW_BREAKPOINT if PERF_EVENTS
134 select HAVE_IRQ_TIME_ACCOUNTING
136 select HAVE_MEMBLOCK_NODE_MAP if NUMA
138 select HAVE_PATA_PLATFORM
139 select HAVE_PERF_EVENTS
140 select HAVE_PERF_REGS
141 select HAVE_PERF_USER_STACK_DUMP
142 select HAVE_REGS_AND_STACK_ACCESS_API
143 select HAVE_RCU_TABLE_FREE
145 select HAVE_STACKPROTECTOR
146 select HAVE_SYSCALL_TRACEPOINTS
148 select HAVE_KRETPROBES
149 select IOMMU_DMA if IOMMU_SUPPORT
151 select IRQ_FORCED_THREADING
152 select MODULES_USE_ELF_RELA
153 select MULTI_IRQ_HANDLER
154 select NEED_DMA_MAP_STATE
155 select NEED_SG_DMA_LENGTH
158 select OF_EARLY_FLATTREE
159 select OF_RESERVED_MEM
160 select PCI_ECAM if ACPI
166 select SYSCTL_EXCEPTION_TRACE
167 select THREAD_INFO_IN_TASK
169 ARM 64-bit (AArch64) Linux support.
177 config ARM64_PAGE_SHIFT
179 default 16 if ARM64_64K_PAGES
180 default 14 if ARM64_16K_PAGES
183 config ARM64_CONT_SHIFT
185 default 5 if ARM64_64K_PAGES
186 default 7 if ARM64_16K_PAGES
189 config ARCH_MMAP_RND_BITS_MIN
190 default 14 if ARM64_64K_PAGES
191 default 16 if ARM64_16K_PAGES
194 # max bits determined by the following formula:
195 # VA_BITS - PAGE_SHIFT - 3
196 config ARCH_MMAP_RND_BITS_MAX
197 default 19 if ARM64_VA_BITS=36
198 default 24 if ARM64_VA_BITS=39
199 default 27 if ARM64_VA_BITS=42
200 default 30 if ARM64_VA_BITS=47
201 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
202 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
203 default 33 if ARM64_VA_BITS=48
204 default 14 if ARM64_64K_PAGES
205 default 16 if ARM64_16K_PAGES
208 config ARCH_MMAP_RND_COMPAT_BITS_MIN
209 default 7 if ARM64_64K_PAGES
210 default 9 if ARM64_16K_PAGES
213 config ARCH_MMAP_RND_COMPAT_BITS_MAX
219 config STACKTRACE_SUPPORT
222 config ILLEGAL_POINTER_VALUE
224 default 0xdead000000000000
226 config LOCKDEP_SUPPORT
229 config TRACE_IRQFLAGS_SUPPORT
232 config RWSEM_XCHGADD_ALGORITHM
239 config GENERIC_BUG_RELATIVE_POINTERS
241 depends on GENERIC_BUG
243 config GENERIC_HWEIGHT
249 config GENERIC_CALIBRATE_DELAY
255 config HAVE_GENERIC_GUP
261 config KERNEL_MODE_NEON
264 config FIX_EARLYCON_MEM
267 config PGTABLE_LEVELS
269 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
270 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
271 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
272 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
273 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
274 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
276 config ARCH_SUPPORTS_UPROBES
279 config ARCH_PROC_KCORE_TEXT
282 source "arch/arm64/Kconfig.platforms"
289 This feature enables support for PCI bus system. If you say Y
290 here, the kernel will include drivers and infrastructure code
291 to support PCI bus devices.
296 config PCI_DOMAINS_GENERIC
302 source "drivers/pci/Kconfig"
306 menu "Kernel Features"
308 menu "ARM errata workarounds via the alternatives framework"
310 config ARM64_ERRATUM_826319
311 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
314 This option adds an alternative code sequence to work around ARM
315 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
316 AXI master interface and an L2 cache.
318 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
319 and is unable to accept a certain write via this interface, it will
320 not progress on read data presented on the read data channel and the
323 The workaround promotes data cache clean instructions to
324 data cache clean-and-invalidate.
325 Please note that this does not necessarily enable the workaround,
326 as it depends on the alternative framework, which will only patch
327 the kernel if an affected CPU is detected.
331 config ARM64_ERRATUM_827319
332 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
335 This option adds an alternative code sequence to work around ARM
336 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
337 master interface and an L2 cache.
339 Under certain conditions this erratum can cause a clean line eviction
340 to occur at the same time as another transaction to the same address
341 on the AMBA 5 CHI interface, which can cause data corruption if the
342 interconnect reorders the two transactions.
344 The workaround promotes data cache clean instructions to
345 data cache clean-and-invalidate.
346 Please note that this does not necessarily enable the workaround,
347 as it depends on the alternative framework, which will only patch
348 the kernel if an affected CPU is detected.
352 config ARM64_ERRATUM_824069
353 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
356 This option adds an alternative code sequence to work around ARM
357 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
358 to a coherent interconnect.
360 If a Cortex-A53 processor is executing a store or prefetch for
361 write instruction at the same time as a processor in another
362 cluster is executing a cache maintenance operation to the same
363 address, then this erratum might cause a clean cache line to be
364 incorrectly marked as dirty.
366 The workaround promotes data cache clean instructions to
367 data cache clean-and-invalidate.
368 Please note that this option does not necessarily enable the
369 workaround, as it depends on the alternative framework, which will
370 only patch the kernel if an affected CPU is detected.
374 config ARM64_ERRATUM_819472
375 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
378 This option adds an alternative code sequence to work around ARM
379 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
380 present when it is connected to a coherent interconnect.
382 If the processor is executing a load and store exclusive sequence at
383 the same time as a processor in another cluster is executing a cache
384 maintenance operation to the same address, then this erratum might
385 cause data corruption.
387 The workaround promotes data cache clean instructions to
388 data cache clean-and-invalidate.
389 Please note that this does not necessarily enable the workaround,
390 as it depends on the alternative framework, which will only patch
391 the kernel if an affected CPU is detected.
395 config ARM64_ERRATUM_832075
396 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
399 This option adds an alternative code sequence to work around ARM
400 erratum 832075 on Cortex-A57 parts up to r1p2.
402 Affected Cortex-A57 parts might deadlock when exclusive load/store
403 instructions to Write-Back memory are mixed with Device loads.
405 The workaround is to promote device loads to use Load-Acquire
407 Please note that this does not necessarily enable the workaround,
408 as it depends on the alternative framework, which will only patch
409 the kernel if an affected CPU is detected.
413 config ARM64_ERRATUM_834220
414 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
418 This option adds an alternative code sequence to work around ARM
419 erratum 834220 on Cortex-A57 parts up to r1p2.
421 Affected Cortex-A57 parts might report a Stage 2 translation
422 fault as the result of a Stage 1 fault for load crossing a
423 page boundary when there is a permission or device memory
424 alignment fault at Stage 1 and a translation fault at Stage 2.
426 The workaround is to verify that the Stage 1 translation
427 doesn't generate a fault before handling the Stage 2 fault.
428 Please note that this does not necessarily enable the workaround,
429 as it depends on the alternative framework, which will only patch
430 the kernel if an affected CPU is detected.
434 config ARM64_ERRATUM_845719
435 bool "Cortex-A53: 845719: a load might read incorrect data"
439 This option adds an alternative code sequence to work around ARM
440 erratum 845719 on Cortex-A53 parts up to r0p4.
442 When running a compat (AArch32) userspace on an affected Cortex-A53
443 part, a load at EL0 from a virtual address that matches the bottom 32
444 bits of the virtual address used by a recent load at (AArch64) EL1
445 might return incorrect data.
447 The workaround is to write the contextidr_el1 register on exception
448 return to a 32-bit task.
449 Please note that this does not necessarily enable the workaround,
450 as it depends on the alternative framework, which will only patch
451 the kernel if an affected CPU is detected.
455 config ARM64_ERRATUM_843419
456 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
458 select ARM64_MODULE_PLTS if MODULES
460 This option links the kernel with '--fix-cortex-a53-843419' and
461 enables PLT support to replace certain ADRP instructions, which can
462 cause subsequent memory accesses to use an incorrect address on
463 Cortex-A53 parts up to r0p4.
467 config ARM64_ERRATUM_1024718
468 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update"
471 This option adds work around for Arm Cortex-A55 Erratum 1024718.
473 Affected Cortex-A55 cores (r0p0, r0p1, r1p0) could cause incorrect
474 update of the hardware dirty bit when the DBM/AP bits are updated
475 without a break-before-make. The work around is to disable the usage
476 of hardware DBM locally on the affected cores. CPUs not affected by
477 erratum will continue to use the feature.
481 config CAVIUM_ERRATUM_22375
482 bool "Cavium erratum 22375, 24313"
485 Enable workaround for erratum 22375, 24313.
487 This implements two gicv3-its errata workarounds for ThunderX. Both
488 with small impact affecting only ITS table allocation.
490 erratum 22375: only alloc 8MB table size
491 erratum 24313: ignore memory access type
493 The fixes are in ITS initialization and basically ignore memory access
494 type and table size provided by the TYPER and BASER registers.
498 config CAVIUM_ERRATUM_23144
499 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
503 ITS SYNC command hang for cross node io and collections/cpu mapping.
507 config CAVIUM_ERRATUM_23154
508 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
511 The gicv3 of ThunderX requires a modified version for
512 reading the IAR status to ensure data synchronization
513 (access to icc_iar1_el1 is not sync'ed before and after).
517 config CAVIUM_ERRATUM_27456
518 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
521 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
522 instructions may cause the icache to become corrupted if it
523 contains data for a non-current ASID. The fix is to
524 invalidate the icache when changing the mm context.
528 config CAVIUM_ERRATUM_30115
529 bool "Cavium erratum 30115: Guest may disable interrupts in host"
532 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through
533 1.2, and T83 Pass 1.0, KVM guest execution may disable
534 interrupts in host. Trapping both GICv3 group-0 and group-1
535 accesses sidesteps the issue.
539 config QCOM_FALKOR_ERRATUM_1003
540 bool "Falkor E1003: Incorrect translation due to ASID change"
543 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
544 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID
545 in TTBR1_EL1, this situation only occurs in the entry trampoline and
546 then only for entries in the walk cache, since the leaf translation
547 is unchanged. Work around the erratum by invalidating the walk cache
548 entries for the trampoline before entering the kernel proper.
550 config QCOM_FALKOR_ERRATUM_1009
551 bool "Falkor E1009: Prematurely complete a DSB after a TLBI"
554 On Falkor v1, the CPU may prematurely complete a DSB following a
555 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation
556 one more time to fix the issue.
560 config QCOM_QDF2400_ERRATUM_0065
561 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size"
564 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports
565 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have
566 been indicated as 16Bytes (0xf), not 8Bytes (0x7).
570 config SOCIONEXT_SYNQUACER_PREITS
571 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
574 Socionext Synquacer SoCs implement a separate h/w block to generate
575 MSI doorbell writes with non-zero values for the device ID.
579 config HISILICON_ERRATUM_161600802
580 bool "Hip07 161600802: Erroneous redistributor VLPI base"
583 The HiSilicon Hip07 SoC usees the wrong redistributor base
584 when issued ITS commands such as VMOVP and VMAPP, and requires
585 a 128kB offset to be applied to the target address in this commands.
589 config QCOM_FALKOR_ERRATUM_E1041
590 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access"
593 Falkor CPU may speculatively fetch instructions from an improper
594 memory location when MMU translation is changed from SCTLR_ELn[M]=1
595 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem.
604 default ARM64_4K_PAGES
606 Page size (translation granule) configuration.
608 config ARM64_4K_PAGES
611 This feature enables 4KB pages support.
613 config ARM64_16K_PAGES
616 The system will use 16KB pages support. AArch32 emulation
617 requires applications compiled with 16K (or a multiple of 16K)
620 config ARM64_64K_PAGES
623 This feature enables 64KB pages support (4KB by default)
624 allowing only two levels of page tables and faster TLB
625 look-up. AArch32 emulation requires applications compiled
626 with 64K aligned segments.
631 prompt "Virtual address space size"
632 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
633 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
634 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
636 Allows choosing one of multiple possible virtual address
637 space sizes. The level of translation table is determined by
638 a combination of page size and virtual address space size.
640 config ARM64_VA_BITS_36
641 bool "36-bit" if EXPERT
642 depends on ARM64_16K_PAGES
644 config ARM64_VA_BITS_39
646 depends on ARM64_4K_PAGES
648 config ARM64_VA_BITS_42
650 depends on ARM64_64K_PAGES
652 config ARM64_VA_BITS_47
654 depends on ARM64_16K_PAGES
656 config ARM64_VA_BITS_48
663 default 36 if ARM64_VA_BITS_36
664 default 39 if ARM64_VA_BITS_39
665 default 42 if ARM64_VA_BITS_42
666 default 47 if ARM64_VA_BITS_47
667 default 48 if ARM64_VA_BITS_48
670 prompt "Physical address space size"
671 default ARM64_PA_BITS_48
673 Choose the maximum physical address range that the kernel will
676 config ARM64_PA_BITS_48
679 config ARM64_PA_BITS_52
680 bool "52-bit (ARMv8.2)"
681 depends on ARM64_64K_PAGES
682 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
684 Enable support for a 52-bit physical address space, introduced as
685 part of the ARMv8.2-LPA extension.
687 With this enabled, the kernel will also continue to work on CPUs that
688 do not support ARMv8.2-LPA, but with some added memory overhead (and
689 minor performance overhead).
695 default 48 if ARM64_PA_BITS_48
696 default 52 if ARM64_PA_BITS_52
698 config CPU_BIG_ENDIAN
699 bool "Build big-endian kernel"
701 Say Y if you plan on running a kernel in big-endian mode.
704 bool "Multi-core scheduler support"
706 Multi-core scheduler support improves the CPU scheduler's decision
707 making when dealing with multi-core CPU chips at a cost of slightly
708 increased overhead in some places. If unsure say N here.
711 bool "SMT scheduler support"
713 Improves the CPU scheduler's decision making when dealing with
714 MultiThreading at a cost of slightly increased overhead in some
715 places. If unsure say N here.
718 int "Maximum number of CPUs (2-4096)"
720 # These have to remain sorted largest to smallest
724 bool "Support for hot-pluggable CPUs"
725 select GENERIC_IRQ_MIGRATION
727 Say Y here to experiment with turning CPUs off and on. CPUs
728 can be controlled through /sys/devices/system/cpu.
730 # Common NUMA Features
732 bool "Numa Memory Allocation and Scheduler Support"
733 select ACPI_NUMA if ACPI
736 Enable NUMA (Non Uniform Memory Access) support.
738 The kernel will try to allocate memory used by a CPU on the
739 local memory of the CPU and add some more
740 NUMA awareness to the kernel.
743 int "Maximum NUMA Nodes (as a power of 2)"
746 depends on NEED_MULTIPLE_NODES
748 Specify the maximum number of NUMA Nodes available on the target
749 system. Increases memory reserved to accommodate various tables.
751 config USE_PERCPU_NUMA_NODE_ID
755 config HAVE_SETUP_PER_CPU_AREA
759 config NEED_PER_CPU_EMBED_FIRST_CHUNK
767 source kernel/Kconfig.hz
769 config ARCH_SUPPORTS_DEBUG_PAGEALLOC
772 config ARCH_HAS_HOLES_MEMORYMODEL
773 def_bool y if SPARSEMEM
775 config ARCH_SPARSEMEM_ENABLE
777 select SPARSEMEM_VMEMMAP_ENABLE
779 config ARCH_SPARSEMEM_DEFAULT
780 def_bool ARCH_SPARSEMEM_ENABLE
782 config ARCH_SELECT_MEMORY_MODEL
783 def_bool ARCH_SPARSEMEM_ENABLE
785 config ARCH_FLATMEM_ENABLE
788 config HAVE_ARCH_PFN_VALID
789 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
791 config HW_PERF_EVENTS
795 config SYS_SUPPORTS_HUGETLBFS
798 config ARCH_WANT_HUGE_PMD_SHARE
799 def_bool y if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
801 config ARCH_HAS_CACHE_LINE_SIZE
805 bool "Enable seccomp to safely compute untrusted bytecode"
807 This kernel feature is useful for number crunching applications
808 that may need to compute untrusted bytecode during their
809 execution. By using pipes or other transports made available to
810 the process as file descriptors supporting the read/write
811 syscalls, it's possible to isolate those applications in
812 their own address space using seccomp. Once seccomp is
813 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
814 and the task is only allowed to execute a few safe syscalls
815 defined by each seccomp mode.
818 bool "Enable paravirtualization code"
820 This changes the kernel so it can modify itself when it is run
821 under a hypervisor, potentially improving performance significantly
822 over full virtualization.
824 config PARAVIRT_TIME_ACCOUNTING
825 bool "Paravirtual steal time accounting"
829 Select this option to enable fine granularity task steal time
830 accounting. Time spent executing other tasks in parallel with
831 the current vCPU is discounted from the vCPU power. To account for
832 that, there can be a small performance impact.
834 If in doubt, say N here.
837 depends on PM_SLEEP_SMP
839 bool "kexec system call"
841 kexec is a system call that implements the ability to shutdown your
842 current kernel, and to start another kernel. It is like a reboot
843 but it is independent of the system firmware. And like a reboot
844 you can start any kernel with it, not just Linux.
847 bool "Build kdump crash kernel"
849 Generate crash dump after being started by kexec. This should
850 be normally only set in special crash dump kernels which are
851 loaded in the main kernel with kexec-tools into a specially
852 reserved region and then later executed after a crash by
855 For more details see Documentation/kdump/kdump.txt
862 bool "Xen guest support on ARM64"
863 depends on ARM64 && OF
867 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
869 config FORCE_MAX_ZONEORDER
871 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
872 default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE)
875 The kernel memory allocator divides physically contiguous memory
876 blocks into "zones", where each zone is a power of two number of
877 pages. This option selects the largest power of two that the kernel
878 keeps in the memory allocator. If you need to allocate very large
879 blocks of physically contiguous memory, then you may need to
882 This config option is actually maximum order plus one. For example,
883 a value of 11 means that the largest free memory block is 2^10 pages.
885 We make sure that we can allocate upto a HugePage size for each configuration.
887 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
889 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
890 4M allocations matching the default size used by generic code.
892 config UNMAP_KERNEL_AT_EL0
893 bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT
896 Speculation attacks against some high-performance processors can
897 be used to bypass MMU permission checks and leak kernel data to
898 userspace. This can be defended against by unmapping the kernel
899 when running in userspace, mapping it back in on exception entry
900 via a trampoline page in the vector table.
904 config HARDEN_BRANCH_PREDICTOR
905 bool "Harden the branch predictor against aliasing attacks" if EXPERT
908 Speculation attacks against some high-performance processors rely on
909 being able to manipulate the branch predictor for a victim context by
910 executing aliasing branches in the attacker context. Such attacks
911 can be partially mitigated against by clearing internal branch
912 predictor state and limiting the prediction logic in some situations.
914 This config option will take CPU-specific actions to harden the
915 branch predictor against aliasing attacks and may rely on specific
916 instruction sequences or control bits being set by the system
921 config HARDEN_EL2_VECTORS
922 bool "Harden EL2 vector mapping against system register leak" if EXPERT
925 Speculation attacks against some high-performance processors can
926 be used to leak privileged information such as the vector base
927 register, resulting in a potential defeat of the EL2 layout
930 This config option will map the vectors to a fixed location,
931 independent of the EL2 code mapping, so that revealing VBAR_EL2
932 to an attacker does not give away any extra information. This
933 only gets enabled on affected CPUs.
938 bool "Speculative Store Bypass Disable" if EXPERT
941 This enables mitigation of the bypassing of previous stores
942 by speculative loads.
946 menuconfig ARMV8_DEPRECATED
947 bool "Emulate deprecated/obsolete ARMv8 instructions"
951 Legacy software support may require certain instructions
952 that have been deprecated or obsoleted in the architecture.
954 Enable this config to enable selective emulation of these
962 bool "Emulate SWP/SWPB instructions"
964 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
965 they are always undefined. Say Y here to enable software
966 emulation of these instructions for userspace using LDXR/STXR.
968 In some older versions of glibc [<=2.8] SWP is used during futex
969 trylock() operations with the assumption that the code will not
970 be preempted. This invalid assumption may be more likely to fail
971 with SWP emulation enabled, leading to deadlock of the user
974 NOTE: when accessing uncached shared regions, LDXR/STXR rely
975 on an external transaction monitoring block called a global
976 monitor to maintain update atomicity. If your system does not
977 implement a global monitor, this option can cause programs that
978 perform SWP operations to uncached memory to deadlock.
982 config CP15_BARRIER_EMULATION
983 bool "Emulate CP15 Barrier instructions"
985 The CP15 barrier instructions - CP15ISB, CP15DSB, and
986 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
987 strongly recommended to use the ISB, DSB, and DMB
988 instructions instead.
990 Say Y here to enable software emulation of these
991 instructions for AArch32 userspace code. When this option is
992 enabled, CP15 barrier usage is traced which can help
993 identify software that needs updating.
997 config SETEND_EMULATION
998 bool "Emulate SETEND instruction"
1000 The SETEND instruction alters the data-endianness of the
1001 AArch32 EL0, and is deprecated in ARMv8.
1003 Say Y here to enable software emulation of the instruction
1004 for AArch32 userspace code.
1006 Note: All the cpus on the system must have mixed endian support at EL0
1007 for this feature to be enabled. If a new CPU - which doesn't support mixed
1008 endian - is hotplugged in after this feature has been enabled, there could
1009 be unexpected results in the applications.
1014 config ARM64_SW_TTBR0_PAN
1015 bool "Emulate Privileged Access Never using TTBR0_EL1 switching"
1017 Enabling this option prevents the kernel from accessing
1018 user-space memory directly by pointing TTBR0_EL1 to a reserved
1019 zeroed area and reserved ASID. The user access routines
1020 restore the valid TTBR0_EL1 temporarily.
1022 menu "ARMv8.1 architectural features"
1024 config ARM64_HW_AFDBM
1025 bool "Support for hardware updates of the Access and Dirty page flags"
1028 The ARMv8.1 architecture extensions introduce support for
1029 hardware updates of the access and dirty information in page
1030 table entries. When enabled in TCR_EL1 (HA and HD bits) on
1031 capable processors, accesses to pages with PTE_AF cleared will
1032 set this bit instead of raising an access flag fault.
1033 Similarly, writes to read-only pages with the DBM bit set will
1034 clear the read-only bit (AP[2]) instead of raising a
1037 Kernels built with this configuration option enabled continue
1038 to work on pre-ARMv8.1 hardware and the performance impact is
1039 minimal. If unsure, say Y.
1042 bool "Enable support for Privileged Access Never (PAN)"
1045 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
1046 prevents the kernel or hypervisor from accessing user-space (EL0)
1049 Choosing this option will cause any unprotected (not using
1050 copy_to_user et al) memory access to fail with a permission fault.
1052 The feature is detected at runtime, and will remain as a 'nop'
1053 instruction if the cpu does not implement the feature.
1055 config ARM64_LSE_ATOMICS
1056 bool "Atomic instructions"
1059 As part of the Large System Extensions, ARMv8.1 introduces new
1060 atomic instructions that are designed specifically to scale in
1063 Say Y here to make use of these instructions for the in-kernel
1064 atomic routines. This incurs a small overhead on CPUs that do
1065 not support these instructions and requires the kernel to be
1066 built with binutils >= 2.25 in order for the new instructions
1070 bool "Enable support for Virtualization Host Extensions (VHE)"
1073 Virtualization Host Extensions (VHE) allow the kernel to run
1074 directly at EL2 (instead of EL1) on processors that support
1075 it. This leads to better performance for KVM, as they reduce
1076 the cost of the world switch.
1078 Selecting this option allows the VHE feature to be detected
1079 at runtime, and does not affect processors that do not
1080 implement this feature.
1084 menu "ARMv8.2 architectural features"
1087 bool "Enable support for User Access Override (UAO)"
1090 User Access Override (UAO; part of the ARMv8.2 Extensions)
1091 causes the 'unprivileged' variant of the load/store instructions to
1092 be overridden to be privileged.
1094 This option changes get_user() and friends to use the 'unprivileged'
1095 variant of the load/store instructions. This ensures that user-space
1096 really did have access to the supplied memory. When addr_limit is
1097 set to kernel memory the UAO bit will be set, allowing privileged
1098 access to kernel memory.
1100 Choosing this option will cause copy_to_user() et al to use user-space
1103 The feature is detected at runtime, the kernel will use the
1104 regular load/store instructions if the cpu does not implement the
1108 bool "Enable support for persistent memory"
1109 select ARCH_HAS_PMEM_API
1110 select ARCH_HAS_UACCESS_FLUSHCACHE
1112 Say Y to enable support for the persistent memory API based on the
1113 ARMv8.2 DCPoP feature.
1115 The feature is detected at runtime, and the kernel will use DC CVAC
1116 operations if DC CVAP is not supported (following the behaviour of
1117 DC CVAP itself if the system does not define a point of persistence).
1119 config ARM64_RAS_EXTN
1120 bool "Enable support for RAS CPU Extensions"
1123 CPUs that support the Reliability, Availability and Serviceability
1124 (RAS) Extensions, part of ARMv8.2 are able to track faults and
1125 errors, classify them and report them to software.
1127 On CPUs with these extensions system software can use additional
1128 barriers to determine if faults are pending and read the
1129 classification from a new set of registers.
1131 Selecting this feature will allow the kernel to use these barriers
1132 and access the new registers if the system supports the extension.
1133 Platform RAS features may additionally depend on firmware support.
1138 bool "ARM Scalable Vector Extension support"
1140 depends on !KVM || ARM64_VHE
1142 The Scalable Vector Extension (SVE) is an extension to the AArch64
1143 execution state which complements and extends the SIMD functionality
1144 of the base architecture to support much larger vectors and to enable
1145 additional vectorisation opportunities.
1147 To enable use of this extension on CPUs that implement it, say Y.
1149 Note that for architectural reasons, firmware _must_ implement SVE
1150 support when running on SVE capable hardware. The required support
1153 * version 1.5 and later of the ARM Trusted Firmware
1154 * the AArch64 boot wrapper since commit 5e1261e08abf
1155 ("bootwrapper: SVE: Enable SVE for EL2 and below").
1157 For other firmware implementations, consult the firmware documentation
1160 If you need the kernel to boot on SVE-capable hardware with broken
1161 firmware, you may need to say N here until you get your firmware
1162 fixed. Otherwise, you may experience firmware panics or lockups when
1163 booting the kernel. If unsure and you are not observing these
1164 symptoms, you should assume that it is safe to say Y.
1166 CPUs that support SVE are architecturally required to support the
1167 Virtualization Host Extensions (VHE), so the kernel makes no
1168 provision for supporting SVE alongside KVM without VHE enabled.
1169 Thus, you will need to enable CONFIG_ARM64_VHE if you want to support
1170 KVM in the same kernel image.
1172 config ARM64_MODULE_PLTS
1174 select HAVE_MOD_ARCH_SPECIFIC
1179 This builds the kernel as a Position Independent Executable (PIE),
1180 which retains all relocation metadata required to relocate the
1181 kernel binary at runtime to a different virtual address than the
1182 address it was linked at.
1183 Since AArch64 uses the RELA relocation format, this requires a
1184 relocation pass at runtime even if the kernel is loaded at the
1185 same address it was linked at.
1187 config RANDOMIZE_BASE
1188 bool "Randomize the address of the kernel image"
1189 select ARM64_MODULE_PLTS if MODULES
1192 Randomizes the virtual address at which the kernel image is
1193 loaded, as a security feature that deters exploit attempts
1194 relying on knowledge of the location of kernel internals.
1196 It is the bootloader's job to provide entropy, by passing a
1197 random u64 value in /chosen/kaslr-seed at kernel entry.
1199 When booting via the UEFI stub, it will invoke the firmware's
1200 EFI_RNG_PROTOCOL implementation (if available) to supply entropy
1201 to the kernel proper. In addition, it will randomise the physical
1202 location of the kernel Image as well.
1206 config RANDOMIZE_MODULE_REGION_FULL
1207 bool "Randomize the module region over a 4 GB range"
1208 depends on RANDOMIZE_BASE
1211 Randomizes the location of the module region inside a 4 GB window
1212 covering the core kernel. This way, it is less likely for modules
1213 to leak information about the location of core kernel data structures
1214 but it does imply that function calls between modules and the core
1215 kernel will need to be resolved via veneers in the module PLT.
1217 When this option is not set, the module region will be randomized over
1218 a limited range that contains the [_stext, _etext] interval of the
1219 core kernel, so branch relocations are always in range.
1225 config ARM64_ACPI_PARKING_PROTOCOL
1226 bool "Enable support for the ARM64 ACPI parking protocol"
1229 Enable support for the ARM64 ACPI parking protocol. If disabled
1230 the kernel will not allow booting through the ARM64 ACPI parking
1231 protocol even if the corresponding data is present in the ACPI
1235 string "Default kernel command string"
1238 Provide a set of default command-line options at build time by
1239 entering them here. As a minimum, you should specify the the
1240 root device (e.g. root=/dev/nfs).
1242 config CMDLINE_FORCE
1243 bool "Always use the default kernel command string"
1245 Always use the default kernel command string, even if the boot
1246 loader passes other arguments to the kernel.
1247 This is useful if you cannot or don't want to change the
1248 command-line options your boot loader passes to the kernel.
1254 bool "UEFI runtime support"
1255 depends on OF && !CPU_BIG_ENDIAN
1256 depends on KERNEL_MODE_NEON
1257 select ARCH_SUPPORTS_ACPI
1260 select EFI_PARAMS_FROM_FDT
1261 select EFI_RUNTIME_WRAPPERS
1266 This option provides support for runtime services provided
1267 by UEFI firmware (such as non-volatile variables, realtime
1268 clock, and platform reset). A UEFI stub is also provided to
1269 allow the kernel to be booted as an EFI application. This
1270 is only useful on systems that have UEFI firmware.
1273 bool "Enable support for SMBIOS (DMI) tables"
1277 This enables SMBIOS/DMI feature for systems.
1279 This option is only useful on systems that have UEFI firmware.
1280 However, even with this option, the resultant kernel should
1281 continue to boot on existing non-UEFI platforms.
1286 bool "Kernel support for 32-bit EL0"
1287 depends on ARM64_4K_PAGES || EXPERT
1288 select COMPAT_BINFMT_ELF if BINFMT_ELF
1290 select OLD_SIGSUSPEND3
1291 select COMPAT_OLD_SIGACTION
1293 This option enables support for a 32-bit EL0 running under a 64-bit
1294 kernel at EL1. AArch32-specific components such as system calls,
1295 the user helper functions, VFP support and the ptrace interface are
1296 handled appropriately by the kernel.
1298 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
1299 that you will only be able to execute AArch32 binaries that were compiled
1300 with page size aligned segments.
1302 If you want to execute 32-bit userspace applications, say Y.
1304 config SYSVIPC_COMPAT
1306 depends on COMPAT && SYSVIPC
1308 menu "Power management options"
1310 source "kernel/power/Kconfig"
1312 config ARCH_HIBERNATION_POSSIBLE
1316 config ARCH_HIBERNATION_HEADER
1318 depends on HIBERNATION
1320 config ARCH_SUSPEND_POSSIBLE
1325 menu "CPU Power Management"
1327 source "drivers/cpuidle/Kconfig"
1329 source "drivers/cpufreq/Kconfig"
1333 source "drivers/firmware/Kconfig"
1335 source "drivers/acpi/Kconfig"
1337 source "arch/arm64/kvm/Kconfig"
1340 source "arch/arm64/crypto/Kconfig"