3 select ACPI_CCA_REQUIRED if ACPI
4 select ACPI_GENERIC_GSI if ACPI
5 select ACPI_GTDT if ACPI
6 select ACPI_IORT if ACPI
7 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
8 select ACPI_MCFG if (ACPI && PCI)
9 select ACPI_SPCR_TABLE if ACPI
10 select ACPI_PPTT if ACPI
11 select ARCH_CLOCKSOURCE_DATA
12 select ARCH_HAS_DEBUG_VIRTUAL
13 select ARCH_HAS_DEVMEM_IS_ALLOWED
14 select ARCH_HAS_DMA_COHERENT_TO_PFN
15 select ARCH_HAS_DMA_MMAP_PGPROT
16 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
17 select ARCH_HAS_ELF_RANDOMIZE
18 select ARCH_HAS_FAST_MULTIPLIER
19 select ARCH_HAS_FORTIFY_SOURCE
20 select ARCH_HAS_GCOV_PROFILE_ALL
21 select ARCH_HAS_GIGANTIC_PAGE if (MEMORY_ISOLATION && COMPACTION) || CMA
23 select ARCH_HAS_MEMBARRIER_SYNC_CORE
24 select ARCH_HAS_PTE_SPECIAL
25 select ARCH_HAS_SETUP_DMA_OPS
26 select ARCH_HAS_SET_MEMORY
27 select ARCH_HAS_STRICT_KERNEL_RWX
28 select ARCH_HAS_STRICT_MODULE_RWX
29 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
30 select ARCH_HAS_SYNC_DMA_FOR_CPU
31 select ARCH_HAS_SYSCALL_WRAPPER
32 select ARCH_HAS_TEARDOWN_DMA_OPS if IOMMU_SUPPORT
33 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
34 select ARCH_HAVE_NMI_SAFE_CMPXCHG
35 select ARCH_INLINE_READ_LOCK if !PREEMPT
36 select ARCH_INLINE_READ_LOCK_BH if !PREEMPT
37 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPT
38 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPT
39 select ARCH_INLINE_READ_UNLOCK if !PREEMPT
40 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPT
41 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPT
42 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPT
43 select ARCH_INLINE_WRITE_LOCK if !PREEMPT
44 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPT
45 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPT
46 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPT
47 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPT
48 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPT
49 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPT
50 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPT
51 select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPT
52 select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPT
53 select ARCH_INLINE_SPIN_LOCK if !PREEMPT
54 select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPT
55 select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPT
56 select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPT
57 select ARCH_INLINE_SPIN_UNLOCK if !PREEMPT
58 select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPT
59 select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPT
60 select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPT
61 select ARCH_USE_CMPXCHG_LOCKREF
62 select ARCH_USE_QUEUED_RWLOCKS
63 select ARCH_USE_QUEUED_SPINLOCKS
64 select ARCH_SUPPORTS_MEMORY_FAILURE
65 select ARCH_SUPPORTS_ATOMIC_RMW
66 select ARCH_SUPPORTS_INT128 if GCC_VERSION >= 50000 || CC_IS_CLANG
67 select ARCH_SUPPORTS_NUMA_BALANCING
68 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
69 select ARCH_WANT_FRAME_POINTERS
70 select ARCH_HAS_UBSAN_SANITIZE_ALL
74 select AUDIT_ARCH_COMPAT_GENERIC
75 select ARM_GIC_V2M if PCI
77 select ARM_GIC_V3_ITS if PCI
79 select BUILDTIME_EXTABLE_SORT
80 select CLONE_BACKWARDS
82 select CPU_PM if (SUSPEND || CPU_IDLE)
84 select DCACHE_WORD_ACCESS
85 select DMA_DIRECT_REMAP
88 select GENERIC_ALLOCATOR
89 select GENERIC_ARCH_TOPOLOGY
90 select GENERIC_CLOCKEVENTS
91 select GENERIC_CLOCKEVENTS_BROADCAST
92 select GENERIC_CPU_AUTOPROBE
93 select GENERIC_EARLY_IOREMAP
94 select GENERIC_IDLE_POLL_SETUP
95 select GENERIC_IRQ_MULTI_HANDLER
96 select GENERIC_IRQ_PROBE
97 select GENERIC_IRQ_SHOW
98 select GENERIC_IRQ_SHOW_LEVEL
99 select GENERIC_PCI_IOMAP
100 select GENERIC_SCHED_CLOCK
101 select GENERIC_SMP_IDLE_THREAD
102 select GENERIC_STRNCPY_FROM_USER
103 select GENERIC_STRNLEN_USER
104 select GENERIC_TIME_VSYSCALL
105 select HANDLE_DOMAIN_IRQ
106 select HARDIRQS_SW_RESEND
108 select HAVE_ACPI_APEI if (ACPI && EFI)
109 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
110 select HAVE_ARCH_AUDITSYSCALL
111 select HAVE_ARCH_BITREVERSE
112 select HAVE_ARCH_HUGE_VMAP
113 select HAVE_ARCH_JUMP_LABEL
114 select HAVE_ARCH_JUMP_LABEL_RELATIVE
115 select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
116 select HAVE_ARCH_KASAN_SW_TAGS if HAVE_ARCH_KASAN
117 select HAVE_ARCH_KGDB
118 select HAVE_ARCH_MMAP_RND_BITS
119 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
120 select HAVE_ARCH_PREL32_RELOCATIONS
121 select HAVE_ARCH_SECCOMP_FILTER
122 select HAVE_ARCH_STACKLEAK
123 select HAVE_ARCH_THREAD_STRUCT_WHITELIST
124 select HAVE_ARCH_TRACEHOOK
125 select HAVE_ARCH_TRANSPARENT_HUGEPAGE
126 select HAVE_ARCH_VMAP_STACK
127 select HAVE_ARM_SMCCC
129 select HAVE_C_RECORDMCOUNT
130 select HAVE_CMPXCHG_DOUBLE
131 select HAVE_CMPXCHG_LOCAL
132 select HAVE_CONTEXT_TRACKING
133 select HAVE_DEBUG_BUGVERBOSE
134 select HAVE_DEBUG_KMEMLEAK
135 select HAVE_DMA_CONTIGUOUS
136 select HAVE_DYNAMIC_FTRACE
137 select HAVE_EFFICIENT_UNALIGNED_ACCESS
138 select HAVE_FTRACE_MCOUNT_RECORD
139 select HAVE_FUNCTION_TRACER
140 select HAVE_FUNCTION_GRAPH_TRACER
141 select HAVE_GCC_PLUGINS
142 select HAVE_HW_BREAKPOINT if PERF_EVENTS
143 select HAVE_IRQ_TIME_ACCOUNTING
144 select HAVE_MEMBLOCK_NODE_MAP if NUMA
146 select HAVE_PATA_PLATFORM
147 select HAVE_PERF_EVENTS
148 select HAVE_PERF_REGS
149 select HAVE_PERF_USER_STACK_DUMP
150 select HAVE_REGS_AND_STACK_ACCESS_API
151 select HAVE_RCU_TABLE_FREE
152 select HAVE_RCU_TABLE_INVALIDATE
154 select HAVE_STACKPROTECTOR
155 select HAVE_SYSCALL_TRACEPOINTS
157 select HAVE_KRETPROBES
158 select IOMMU_DMA if IOMMU_SUPPORT
160 select IRQ_FORCED_THREADING
161 select MODULES_USE_ELF_RELA
162 select NEED_DMA_MAP_STATE
163 select NEED_SG_DMA_LENGTH
165 select OF_EARLY_FLATTREE
166 select PCI_DOMAINS_GENERIC if PCI
167 select PCI_ECAM if (ACPI && PCI)
168 select PCI_SYSCALL if PCI
174 select SYSCTL_EXCEPTION_TRACE
175 select THREAD_INFO_IN_TASK
177 ARM 64-bit (AArch64) Linux support.
185 config ARM64_PAGE_SHIFT
187 default 16 if ARM64_64K_PAGES
188 default 14 if ARM64_16K_PAGES
191 config ARM64_CONT_SHIFT
193 default 5 if ARM64_64K_PAGES
194 default 7 if ARM64_16K_PAGES
197 config ARCH_MMAP_RND_BITS_MIN
198 default 14 if ARM64_64K_PAGES
199 default 16 if ARM64_16K_PAGES
202 # max bits determined by the following formula:
203 # VA_BITS - PAGE_SHIFT - 3
204 config ARCH_MMAP_RND_BITS_MAX
205 default 19 if ARM64_VA_BITS=36
206 default 24 if ARM64_VA_BITS=39
207 default 27 if ARM64_VA_BITS=42
208 default 30 if ARM64_VA_BITS=47
209 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
210 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
211 default 33 if ARM64_VA_BITS=48
212 default 14 if ARM64_64K_PAGES
213 default 16 if ARM64_16K_PAGES
216 config ARCH_MMAP_RND_COMPAT_BITS_MIN
217 default 7 if ARM64_64K_PAGES
218 default 9 if ARM64_16K_PAGES
221 config ARCH_MMAP_RND_COMPAT_BITS_MAX
227 config STACKTRACE_SUPPORT
230 config ILLEGAL_POINTER_VALUE
232 default 0xdead000000000000
234 config LOCKDEP_SUPPORT
237 config TRACE_IRQFLAGS_SUPPORT
240 config RWSEM_XCHGADD_ALGORITHM
247 config GENERIC_BUG_RELATIVE_POINTERS
249 depends on GENERIC_BUG
251 config GENERIC_HWEIGHT
257 config GENERIC_CALIBRATE_DELAY
263 config HAVE_GENERIC_GUP
266 config ARCH_ENABLE_MEMORY_HOTPLUG
272 config KERNEL_MODE_NEON
275 config FIX_EARLYCON_MEM
278 config PGTABLE_LEVELS
280 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
281 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
282 default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_USER_VA_BITS_52)
283 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
284 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
285 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
287 config ARCH_SUPPORTS_UPROBES
290 config ARCH_PROC_KCORE_TEXT
293 source "arch/arm64/Kconfig.platforms"
295 menu "Kernel Features"
297 menu "ARM errata workarounds via the alternatives framework"
299 config ARM64_WORKAROUND_CLEAN_CACHE
302 config ARM64_ERRATUM_826319
303 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
305 select ARM64_WORKAROUND_CLEAN_CACHE
307 This option adds an alternative code sequence to work around ARM
308 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
309 AXI master interface and an L2 cache.
311 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
312 and is unable to accept a certain write via this interface, it will
313 not progress on read data presented on the read data channel and the
316 The workaround promotes data cache clean instructions to
317 data cache clean-and-invalidate.
318 Please note that this does not necessarily enable the workaround,
319 as it depends on the alternative framework, which will only patch
320 the kernel if an affected CPU is detected.
324 config ARM64_ERRATUM_827319
325 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
327 select ARM64_WORKAROUND_CLEAN_CACHE
329 This option adds an alternative code sequence to work around ARM
330 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
331 master interface and an L2 cache.
333 Under certain conditions this erratum can cause a clean line eviction
334 to occur at the same time as another transaction to the same address
335 on the AMBA 5 CHI interface, which can cause data corruption if the
336 interconnect reorders the two transactions.
338 The workaround promotes data cache clean instructions to
339 data cache clean-and-invalidate.
340 Please note that this does not necessarily enable the workaround,
341 as it depends on the alternative framework, which will only patch
342 the kernel if an affected CPU is detected.
346 config ARM64_ERRATUM_824069
347 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
349 select ARM64_WORKAROUND_CLEAN_CACHE
351 This option adds an alternative code sequence to work around ARM
352 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
353 to a coherent interconnect.
355 If a Cortex-A53 processor is executing a store or prefetch for
356 write instruction at the same time as a processor in another
357 cluster is executing a cache maintenance operation to the same
358 address, then this erratum might cause a clean cache line to be
359 incorrectly marked as dirty.
361 The workaround promotes data cache clean instructions to
362 data cache clean-and-invalidate.
363 Please note that this option does not necessarily enable the
364 workaround, as it depends on the alternative framework, which will
365 only patch the kernel if an affected CPU is detected.
369 config ARM64_ERRATUM_819472
370 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
372 select ARM64_WORKAROUND_CLEAN_CACHE
374 This option adds an alternative code sequence to work around ARM
375 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
376 present when it is connected to a coherent interconnect.
378 If the processor is executing a load and store exclusive sequence at
379 the same time as a processor in another cluster is executing a cache
380 maintenance operation to the same address, then this erratum might
381 cause data corruption.
383 The workaround promotes data cache clean instructions to
384 data cache clean-and-invalidate.
385 Please note that this does not necessarily enable the workaround,
386 as it depends on the alternative framework, which will only patch
387 the kernel if an affected CPU is detected.
391 config ARM64_ERRATUM_832075
392 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
395 This option adds an alternative code sequence to work around ARM
396 erratum 832075 on Cortex-A57 parts up to r1p2.
398 Affected Cortex-A57 parts might deadlock when exclusive load/store
399 instructions to Write-Back memory are mixed with Device loads.
401 The workaround is to promote device loads to use Load-Acquire
403 Please note that this does not necessarily enable the workaround,
404 as it depends on the alternative framework, which will only patch
405 the kernel if an affected CPU is detected.
409 config ARM64_ERRATUM_834220
410 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
414 This option adds an alternative code sequence to work around ARM
415 erratum 834220 on Cortex-A57 parts up to r1p2.
417 Affected Cortex-A57 parts might report a Stage 2 translation
418 fault as the result of a Stage 1 fault for load crossing a
419 page boundary when there is a permission or device memory
420 alignment fault at Stage 1 and a translation fault at Stage 2.
422 The workaround is to verify that the Stage 1 translation
423 doesn't generate a fault before handling the Stage 2 fault.
424 Please note that this does not necessarily enable the workaround,
425 as it depends on the alternative framework, which will only patch
426 the kernel if an affected CPU is detected.
430 config ARM64_ERRATUM_845719
431 bool "Cortex-A53: 845719: a load might read incorrect data"
435 This option adds an alternative code sequence to work around ARM
436 erratum 845719 on Cortex-A53 parts up to r0p4.
438 When running a compat (AArch32) userspace on an affected Cortex-A53
439 part, a load at EL0 from a virtual address that matches the bottom 32
440 bits of the virtual address used by a recent load at (AArch64) EL1
441 might return incorrect data.
443 The workaround is to write the contextidr_el1 register on exception
444 return to a 32-bit task.
445 Please note that this does not necessarily enable the workaround,
446 as it depends on the alternative framework, which will only patch
447 the kernel if an affected CPU is detected.
451 config ARM64_ERRATUM_843419
452 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
454 select ARM64_MODULE_PLTS if MODULES
456 This option links the kernel with '--fix-cortex-a53-843419' and
457 enables PLT support to replace certain ADRP instructions, which can
458 cause subsequent memory accesses to use an incorrect address on
459 Cortex-A53 parts up to r0p4.
463 config ARM64_ERRATUM_1024718
464 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update"
467 This option adds work around for Arm Cortex-A55 Erratum 1024718.
469 Affected Cortex-A55 cores (r0p0, r0p1, r1p0) could cause incorrect
470 update of the hardware dirty bit when the DBM/AP bits are updated
471 without a break-before-make. The work around is to disable the usage
472 of hardware DBM locally on the affected cores. CPUs not affected by
473 erratum will continue to use the feature.
477 config ARM64_ERRATUM_1188873
478 bool "Cortex-A76: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result"
480 select ARM_ARCH_TIMER_OOL_WORKAROUND
482 This option adds work arounds for ARM Cortex-A76 erratum 1188873
484 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could cause
485 register corruption when accessing the timer registers from
490 config ARM64_ERRATUM_1165522
491 bool "Cortex-A76: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
494 This option adds work arounds for ARM Cortex-A76 erratum 1165522
496 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with
497 corrupted TLBs by speculating an AT instruction during a guest
502 config ARM64_ERRATUM_1286807
503 bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation"
505 select ARM64_WORKAROUND_REPEAT_TLBI
507 This option adds workaround for ARM Cortex-A76 erratum 1286807
509 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual
510 address for a cacheable mapping of a location is being
511 accessed by a core while another core is remapping the virtual
512 address to a new physical page using the recommended
513 break-before-make sequence, then under very rare circumstances
514 TLBI+DSB completes before a read using the translation being
515 invalidated has been observed by other observers. The
516 workaround repeats the TLBI+DSB operation.
520 config CAVIUM_ERRATUM_22375
521 bool "Cavium erratum 22375, 24313"
524 Enable workaround for erratum 22375, 24313.
526 This implements two gicv3-its errata workarounds for ThunderX. Both
527 with small impact affecting only ITS table allocation.
529 erratum 22375: only alloc 8MB table size
530 erratum 24313: ignore memory access type
532 The fixes are in ITS initialization and basically ignore memory access
533 type and table size provided by the TYPER and BASER registers.
537 config CAVIUM_ERRATUM_23144
538 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
542 ITS SYNC command hang for cross node io and collections/cpu mapping.
546 config CAVIUM_ERRATUM_23154
547 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
550 The gicv3 of ThunderX requires a modified version for
551 reading the IAR status to ensure data synchronization
552 (access to icc_iar1_el1 is not sync'ed before and after).
556 config CAVIUM_ERRATUM_27456
557 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
560 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
561 instructions may cause the icache to become corrupted if it
562 contains data for a non-current ASID. The fix is to
563 invalidate the icache when changing the mm context.
567 config CAVIUM_ERRATUM_30115
568 bool "Cavium erratum 30115: Guest may disable interrupts in host"
571 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through
572 1.2, and T83 Pass 1.0, KVM guest execution may disable
573 interrupts in host. Trapping both GICv3 group-0 and group-1
574 accesses sidesteps the issue.
578 config QCOM_FALKOR_ERRATUM_1003
579 bool "Falkor E1003: Incorrect translation due to ASID change"
582 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
583 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID
584 in TTBR1_EL1, this situation only occurs in the entry trampoline and
585 then only for entries in the walk cache, since the leaf translation
586 is unchanged. Work around the erratum by invalidating the walk cache
587 entries for the trampoline before entering the kernel proper.
589 config ARM64_WORKAROUND_REPEAT_TLBI
592 Enable the repeat TLBI workaround for Falkor erratum 1009 and
593 Cortex-A76 erratum 1286807.
595 config QCOM_FALKOR_ERRATUM_1009
596 bool "Falkor E1009: Prematurely complete a DSB after a TLBI"
598 select ARM64_WORKAROUND_REPEAT_TLBI
600 On Falkor v1, the CPU may prematurely complete a DSB following a
601 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation
602 one more time to fix the issue.
606 config QCOM_QDF2400_ERRATUM_0065
607 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size"
610 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports
611 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have
612 been indicated as 16Bytes (0xf), not 8Bytes (0x7).
616 config SOCIONEXT_SYNQUACER_PREITS
617 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
620 Socionext Synquacer SoCs implement a separate h/w block to generate
621 MSI doorbell writes with non-zero values for the device ID.
625 config HISILICON_ERRATUM_161600802
626 bool "Hip07 161600802: Erroneous redistributor VLPI base"
629 The HiSilicon Hip07 SoC usees the wrong redistributor base
630 when issued ITS commands such as VMOVP and VMAPP, and requires
631 a 128kB offset to be applied to the target address in this commands.
635 config QCOM_FALKOR_ERRATUM_E1041
636 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access"
639 Falkor CPU may speculatively fetch instructions from an improper
640 memory location when MMU translation is changed from SCTLR_ELn[M]=1
641 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem.
645 config FUJITSU_ERRATUM_010001
646 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly"
649 This option adds workaround for Fujitsu-A64FX erratum E#010001.
650 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory
651 accesses may cause undefined fault (Data abort, DFSC=0b111111).
652 This fault occurs under a specific hardware condition when a
653 load/store instruction performs an address translation using:
654 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1.
655 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1.
656 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1.
657 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1.
659 The workaround is to ensure these bits are clear in TCR_ELx.
660 The workaround only affect the Fujitsu-A64FX.
669 default ARM64_4K_PAGES
671 Page size (translation granule) configuration.
673 config ARM64_4K_PAGES
676 This feature enables 4KB pages support.
678 config ARM64_16K_PAGES
681 The system will use 16KB pages support. AArch32 emulation
682 requires applications compiled with 16K (or a multiple of 16K)
685 config ARM64_64K_PAGES
688 This feature enables 64KB pages support (4KB by default)
689 allowing only two levels of page tables and faster TLB
690 look-up. AArch32 emulation requires applications compiled
691 with 64K aligned segments.
696 prompt "Virtual address space size"
697 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
698 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
699 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
701 Allows choosing one of multiple possible virtual address
702 space sizes. The level of translation table is determined by
703 a combination of page size and virtual address space size.
705 config ARM64_VA_BITS_36
706 bool "36-bit" if EXPERT
707 depends on ARM64_16K_PAGES
709 config ARM64_VA_BITS_39
711 depends on ARM64_4K_PAGES
713 config ARM64_VA_BITS_42
715 depends on ARM64_64K_PAGES
717 config ARM64_VA_BITS_47
719 depends on ARM64_16K_PAGES
721 config ARM64_VA_BITS_48
724 config ARM64_USER_VA_BITS_52
726 depends on ARM64_64K_PAGES && (ARM64_PAN || !ARM64_SW_TTBR0_PAN)
728 Enable 52-bit virtual addressing for userspace when explicitly
729 requested via a hint to mmap(). The kernel will continue to
730 use 48-bit virtual addresses for its own mappings.
732 NOTE: Enabling 52-bit virtual addressing in conjunction with
733 ARMv8.3 Pointer Authentication will result in the PAC being
734 reduced from 7 bits to 3 bits, which may have a significant
735 impact on its susceptibility to brute-force attacks.
737 If unsure, select 48-bit virtual addressing instead.
741 config ARM64_FORCE_52BIT
742 bool "Force 52-bit virtual addresses for userspace"
743 depends on ARM64_USER_VA_BITS_52 && EXPERT
745 For systems with 52-bit userspace VAs enabled, the kernel will attempt
746 to maintain compatibility with older software by providing 48-bit VAs
747 unless a hint is supplied to mmap.
749 This configuration option disables the 48-bit compatibility logic, and
750 forces all userspace addresses to be 52-bit on HW that supports it. One
751 should only enable this configuration option for stress testing userspace
752 memory management code. If unsure say N here.
756 default 36 if ARM64_VA_BITS_36
757 default 39 if ARM64_VA_BITS_39
758 default 42 if ARM64_VA_BITS_42
759 default 47 if ARM64_VA_BITS_47
760 default 48 if ARM64_VA_BITS_48 || ARM64_USER_VA_BITS_52
763 prompt "Physical address space size"
764 default ARM64_PA_BITS_48
766 Choose the maximum physical address range that the kernel will
769 config ARM64_PA_BITS_48
772 config ARM64_PA_BITS_52
773 bool "52-bit (ARMv8.2)"
774 depends on ARM64_64K_PAGES
775 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
777 Enable support for a 52-bit physical address space, introduced as
778 part of the ARMv8.2-LPA extension.
780 With this enabled, the kernel will also continue to work on CPUs that
781 do not support ARMv8.2-LPA, but with some added memory overhead (and
782 minor performance overhead).
788 default 48 if ARM64_PA_BITS_48
789 default 52 if ARM64_PA_BITS_52
791 config CPU_BIG_ENDIAN
792 bool "Build big-endian kernel"
794 Say Y if you plan on running a kernel in big-endian mode.
797 bool "Multi-core scheduler support"
799 Multi-core scheduler support improves the CPU scheduler's decision
800 making when dealing with multi-core CPU chips at a cost of slightly
801 increased overhead in some places. If unsure say N here.
804 bool "SMT scheduler support"
806 Improves the CPU scheduler's decision making when dealing with
807 MultiThreading at a cost of slightly increased overhead in some
808 places. If unsure say N here.
811 int "Maximum number of CPUs (2-4096)"
816 bool "Support for hot-pluggable CPUs"
817 select GENERIC_IRQ_MIGRATION
819 Say Y here to experiment with turning CPUs off and on. CPUs
820 can be controlled through /sys/devices/system/cpu.
822 # Common NUMA Features
824 bool "Numa Memory Allocation and Scheduler Support"
825 select ACPI_NUMA if ACPI
828 Enable NUMA (Non Uniform Memory Access) support.
830 The kernel will try to allocate memory used by a CPU on the
831 local memory of the CPU and add some more
832 NUMA awareness to the kernel.
835 int "Maximum NUMA Nodes (as a power of 2)"
838 depends on NEED_MULTIPLE_NODES
840 Specify the maximum number of NUMA Nodes available on the target
841 system. Increases memory reserved to accommodate various tables.
843 config USE_PERCPU_NUMA_NODE_ID
847 config HAVE_SETUP_PER_CPU_AREA
851 config NEED_PER_CPU_EMBED_FIRST_CHUNK
858 source "kernel/Kconfig.hz"
860 config ARCH_SUPPORTS_DEBUG_PAGEALLOC
863 config ARCH_SPARSEMEM_ENABLE
865 select SPARSEMEM_VMEMMAP_ENABLE
867 config ARCH_SPARSEMEM_DEFAULT
868 def_bool ARCH_SPARSEMEM_ENABLE
870 config ARCH_SELECT_MEMORY_MODEL
871 def_bool ARCH_SPARSEMEM_ENABLE
873 config ARCH_FLATMEM_ENABLE
876 config HAVE_ARCH_PFN_VALID
879 config HW_PERF_EVENTS
883 config SYS_SUPPORTS_HUGETLBFS
886 config ARCH_WANT_HUGE_PMD_SHARE
887 def_bool y if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
889 config ARCH_HAS_CACHE_LINE_SIZE
893 bool "Enable seccomp to safely compute untrusted bytecode"
895 This kernel feature is useful for number crunching applications
896 that may need to compute untrusted bytecode during their
897 execution. By using pipes or other transports made available to
898 the process as file descriptors supporting the read/write
899 syscalls, it's possible to isolate those applications in
900 their own address space using seccomp. Once seccomp is
901 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
902 and the task is only allowed to execute a few safe syscalls
903 defined by each seccomp mode.
906 bool "Enable paravirtualization code"
908 This changes the kernel so it can modify itself when it is run
909 under a hypervisor, potentially improving performance significantly
910 over full virtualization.
912 config PARAVIRT_TIME_ACCOUNTING
913 bool "Paravirtual steal time accounting"
917 Select this option to enable fine granularity task steal time
918 accounting. Time spent executing other tasks in parallel with
919 the current vCPU is discounted from the vCPU power. To account for
920 that, there can be a small performance impact.
922 If in doubt, say N here.
925 depends on PM_SLEEP_SMP
927 bool "kexec system call"
929 kexec is a system call that implements the ability to shutdown your
930 current kernel, and to start another kernel. It is like a reboot
931 but it is independent of the system firmware. And like a reboot
932 you can start any kernel with it, not just Linux.
935 bool "kexec file based system call"
938 This is new version of kexec system call. This system call is
939 file based and takes file descriptors as system call argument
940 for kernel and initramfs as opposed to list of segments as
941 accepted by previous system call.
943 config KEXEC_VERIFY_SIG
944 bool "Verify kernel signature during kexec_file_load() syscall"
945 depends on KEXEC_FILE
947 Select this option to verify a signature with loaded kernel
948 image. If configured, any attempt of loading a image without
949 valid signature will fail.
951 In addition to that option, you need to enable signature
952 verification for the corresponding kernel image type being
953 loaded in order for this to work.
955 config KEXEC_IMAGE_VERIFY_SIG
956 bool "Enable Image signature verification support"
958 depends on KEXEC_VERIFY_SIG
959 depends on EFI && SIGNED_PE_FILE_VERIFICATION
961 Enable Image signature verification support.
963 comment "Support for PE file signature verification disabled"
964 depends on KEXEC_VERIFY_SIG
965 depends on !EFI || !SIGNED_PE_FILE_VERIFICATION
968 bool "Build kdump crash kernel"
970 Generate crash dump after being started by kexec. This should
971 be normally only set in special crash dump kernels which are
972 loaded in the main kernel with kexec-tools into a specially
973 reserved region and then later executed after a crash by
976 For more details see Documentation/kdump/kdump.txt
983 bool "Xen guest support on ARM64"
984 depends on ARM64 && OF
988 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
990 config FORCE_MAX_ZONEORDER
992 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
993 default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE)
996 The kernel memory allocator divides physically contiguous memory
997 blocks into "zones", where each zone is a power of two number of
998 pages. This option selects the largest power of two that the kernel
999 keeps in the memory allocator. If you need to allocate very large
1000 blocks of physically contiguous memory, then you may need to
1001 increase this value.
1003 This config option is actually maximum order plus one. For example,
1004 a value of 11 means that the largest free memory block is 2^10 pages.
1006 We make sure that we can allocate upto a HugePage size for each configuration.
1008 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
1010 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
1011 4M allocations matching the default size used by generic code.
1013 config UNMAP_KERNEL_AT_EL0
1014 bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT
1017 Speculation attacks against some high-performance processors can
1018 be used to bypass MMU permission checks and leak kernel data to
1019 userspace. This can be defended against by unmapping the kernel
1020 when running in userspace, mapping it back in on exception entry
1021 via a trampoline page in the vector table.
1025 config HARDEN_BRANCH_PREDICTOR
1026 bool "Harden the branch predictor against aliasing attacks" if EXPERT
1029 Speculation attacks against some high-performance processors rely on
1030 being able to manipulate the branch predictor for a victim context by
1031 executing aliasing branches in the attacker context. Such attacks
1032 can be partially mitigated against by clearing internal branch
1033 predictor state and limiting the prediction logic in some situations.
1035 This config option will take CPU-specific actions to harden the
1036 branch predictor against aliasing attacks and may rely on specific
1037 instruction sequences or control bits being set by the system
1042 config HARDEN_EL2_VECTORS
1043 bool "Harden EL2 vector mapping against system register leak" if EXPERT
1046 Speculation attacks against some high-performance processors can
1047 be used to leak privileged information such as the vector base
1048 register, resulting in a potential defeat of the EL2 layout
1051 This config option will map the vectors to a fixed location,
1052 independent of the EL2 code mapping, so that revealing VBAR_EL2
1053 to an attacker does not give away any extra information. This
1054 only gets enabled on affected CPUs.
1059 bool "Speculative Store Bypass Disable" if EXPERT
1062 This enables mitigation of the bypassing of previous stores
1063 by speculative loads.
1067 config RODATA_FULL_DEFAULT_ENABLED
1068 bool "Apply r/o permissions of VM areas also to their linear aliases"
1071 Apply read-only attributes of VM areas to the linear alias of
1072 the backing pages as well. This prevents code or read-only data
1073 from being modified (inadvertently or intentionally) via another
1074 mapping of the same memory page. This additional enhancement can
1075 be turned off at runtime by passing rodata=[off|on] (and turned on
1076 with rodata=full if this option is set to 'n')
1078 This requires the linear region to be mapped down to pages,
1079 which may adversely affect performance in some cases.
1081 menuconfig ARMV8_DEPRECATED
1082 bool "Emulate deprecated/obsolete ARMv8 instructions"
1086 Legacy software support may require certain instructions
1087 that have been deprecated or obsoleted in the architecture.
1089 Enable this config to enable selective emulation of these
1096 config SWP_EMULATION
1097 bool "Emulate SWP/SWPB instructions"
1099 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
1100 they are always undefined. Say Y here to enable software
1101 emulation of these instructions for userspace using LDXR/STXR.
1103 In some older versions of glibc [<=2.8] SWP is used during futex
1104 trylock() operations with the assumption that the code will not
1105 be preempted. This invalid assumption may be more likely to fail
1106 with SWP emulation enabled, leading to deadlock of the user
1109 NOTE: when accessing uncached shared regions, LDXR/STXR rely
1110 on an external transaction monitoring block called a global
1111 monitor to maintain update atomicity. If your system does not
1112 implement a global monitor, this option can cause programs that
1113 perform SWP operations to uncached memory to deadlock.
1117 config CP15_BARRIER_EMULATION
1118 bool "Emulate CP15 Barrier instructions"
1120 The CP15 barrier instructions - CP15ISB, CP15DSB, and
1121 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
1122 strongly recommended to use the ISB, DSB, and DMB
1123 instructions instead.
1125 Say Y here to enable software emulation of these
1126 instructions for AArch32 userspace code. When this option is
1127 enabled, CP15 barrier usage is traced which can help
1128 identify software that needs updating.
1132 config SETEND_EMULATION
1133 bool "Emulate SETEND instruction"
1135 The SETEND instruction alters the data-endianness of the
1136 AArch32 EL0, and is deprecated in ARMv8.
1138 Say Y here to enable software emulation of the instruction
1139 for AArch32 userspace code.
1141 Note: All the cpus on the system must have mixed endian support at EL0
1142 for this feature to be enabled. If a new CPU - which doesn't support mixed
1143 endian - is hotplugged in after this feature has been enabled, there could
1144 be unexpected results in the applications.
1149 config ARM64_SW_TTBR0_PAN
1150 bool "Emulate Privileged Access Never using TTBR0_EL1 switching"
1152 Enabling this option prevents the kernel from accessing
1153 user-space memory directly by pointing TTBR0_EL1 to a reserved
1154 zeroed area and reserved ASID. The user access routines
1155 restore the valid TTBR0_EL1 temporarily.
1157 menu "ARMv8.1 architectural features"
1159 config ARM64_HW_AFDBM
1160 bool "Support for hardware updates of the Access and Dirty page flags"
1163 The ARMv8.1 architecture extensions introduce support for
1164 hardware updates of the access and dirty information in page
1165 table entries. When enabled in TCR_EL1 (HA and HD bits) on
1166 capable processors, accesses to pages with PTE_AF cleared will
1167 set this bit instead of raising an access flag fault.
1168 Similarly, writes to read-only pages with the DBM bit set will
1169 clear the read-only bit (AP[2]) instead of raising a
1172 Kernels built with this configuration option enabled continue
1173 to work on pre-ARMv8.1 hardware and the performance impact is
1174 minimal. If unsure, say Y.
1177 bool "Enable support for Privileged Access Never (PAN)"
1180 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
1181 prevents the kernel or hypervisor from accessing user-space (EL0)
1184 Choosing this option will cause any unprotected (not using
1185 copy_to_user et al) memory access to fail with a permission fault.
1187 The feature is detected at runtime, and will remain as a 'nop'
1188 instruction if the cpu does not implement the feature.
1190 config ARM64_LSE_ATOMICS
1191 bool "Atomic instructions"
1194 As part of the Large System Extensions, ARMv8.1 introduces new
1195 atomic instructions that are designed specifically to scale in
1198 Say Y here to make use of these instructions for the in-kernel
1199 atomic routines. This incurs a small overhead on CPUs that do
1200 not support these instructions and requires the kernel to be
1201 built with binutils >= 2.25 in order for the new instructions
1205 bool "Enable support for Virtualization Host Extensions (VHE)"
1208 Virtualization Host Extensions (VHE) allow the kernel to run
1209 directly at EL2 (instead of EL1) on processors that support
1210 it. This leads to better performance for KVM, as they reduce
1211 the cost of the world switch.
1213 Selecting this option allows the VHE feature to be detected
1214 at runtime, and does not affect processors that do not
1215 implement this feature.
1219 menu "ARMv8.2 architectural features"
1222 bool "Enable support for User Access Override (UAO)"
1225 User Access Override (UAO; part of the ARMv8.2 Extensions)
1226 causes the 'unprivileged' variant of the load/store instructions to
1227 be overridden to be privileged.
1229 This option changes get_user() and friends to use the 'unprivileged'
1230 variant of the load/store instructions. This ensures that user-space
1231 really did have access to the supplied memory. When addr_limit is
1232 set to kernel memory the UAO bit will be set, allowing privileged
1233 access to kernel memory.
1235 Choosing this option will cause copy_to_user() et al to use user-space
1238 The feature is detected at runtime, the kernel will use the
1239 regular load/store instructions if the cpu does not implement the
1243 bool "Enable support for persistent memory"
1244 select ARCH_HAS_PMEM_API
1245 select ARCH_HAS_UACCESS_FLUSHCACHE
1247 Say Y to enable support for the persistent memory API based on the
1248 ARMv8.2 DCPoP feature.
1250 The feature is detected at runtime, and the kernel will use DC CVAC
1251 operations if DC CVAP is not supported (following the behaviour of
1252 DC CVAP itself if the system does not define a point of persistence).
1254 config ARM64_RAS_EXTN
1255 bool "Enable support for RAS CPU Extensions"
1258 CPUs that support the Reliability, Availability and Serviceability
1259 (RAS) Extensions, part of ARMv8.2 are able to track faults and
1260 errors, classify them and report them to software.
1262 On CPUs with these extensions system software can use additional
1263 barriers to determine if faults are pending and read the
1264 classification from a new set of registers.
1266 Selecting this feature will allow the kernel to use these barriers
1267 and access the new registers if the system supports the extension.
1268 Platform RAS features may additionally depend on firmware support.
1271 bool "Enable support for Common Not Private (CNP) translations"
1273 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
1275 Common Not Private (CNP) allows translation table entries to
1276 be shared between different PEs in the same inner shareable
1277 domain, so the hardware can use this fact to optimise the
1278 caching of such entries in the TLB.
1280 Selecting this option allows the CNP feature to be detected
1281 at runtime, and does not affect PEs that do not implement
1286 menu "ARMv8.3 architectural features"
1288 config ARM64_PTR_AUTH
1289 bool "Enable support for pointer authentication"
1292 Pointer authentication (part of the ARMv8.3 Extensions) provides
1293 instructions for signing and authenticating pointers against secret
1294 keys, which can be used to mitigate Return Oriented Programming (ROP)
1297 This option enables these instructions at EL0 (i.e. for userspace).
1299 Choosing this option will cause the kernel to initialise secret keys
1300 for each process at exec() time, with these keys being
1301 context-switched along with the process.
1303 The feature is detected at runtime. If the feature is not present in
1304 hardware it will not be advertised to userspace nor will it be
1310 bool "ARM Scalable Vector Extension support"
1312 depends on !KVM || ARM64_VHE
1314 The Scalable Vector Extension (SVE) is an extension to the AArch64
1315 execution state which complements and extends the SIMD functionality
1316 of the base architecture to support much larger vectors and to enable
1317 additional vectorisation opportunities.
1319 To enable use of this extension on CPUs that implement it, say Y.
1321 Note that for architectural reasons, firmware _must_ implement SVE
1322 support when running on SVE capable hardware. The required support
1325 * version 1.5 and later of the ARM Trusted Firmware
1326 * the AArch64 boot wrapper since commit 5e1261e08abf
1327 ("bootwrapper: SVE: Enable SVE for EL2 and below").
1329 For other firmware implementations, consult the firmware documentation
1332 If you need the kernel to boot on SVE-capable hardware with broken
1333 firmware, you may need to say N here until you get your firmware
1334 fixed. Otherwise, you may experience firmware panics or lockups when
1335 booting the kernel. If unsure and you are not observing these
1336 symptoms, you should assume that it is safe to say Y.
1338 CPUs that support SVE are architecturally required to support the
1339 Virtualization Host Extensions (VHE), so the kernel makes no
1340 provision for supporting SVE alongside KVM without VHE enabled.
1341 Thus, you will need to enable CONFIG_ARM64_VHE if you want to support
1342 KVM in the same kernel image.
1344 config ARM64_MODULE_PLTS
1346 select HAVE_MOD_ARCH_SPECIFIC
1348 config ARM64_PSEUDO_NMI
1349 bool "Support for NMI-like interrupts"
1350 select CONFIG_ARM_GIC_V3
1352 Adds support for mimicking Non-Maskable Interrupts through the use of
1353 GIC interrupt priority. This support requires version 3 or later of
1356 This high priority configuration for interrupts needs to be
1357 explicitly enabled by setting the kernel parameter
1358 "irqchip.gicv3_pseudo_nmi" to 1.
1365 This builds the kernel as a Position Independent Executable (PIE),
1366 which retains all relocation metadata required to relocate the
1367 kernel binary at runtime to a different virtual address than the
1368 address it was linked at.
1369 Since AArch64 uses the RELA relocation format, this requires a
1370 relocation pass at runtime even if the kernel is loaded at the
1371 same address it was linked at.
1373 config RANDOMIZE_BASE
1374 bool "Randomize the address of the kernel image"
1375 select ARM64_MODULE_PLTS if MODULES
1378 Randomizes the virtual address at which the kernel image is
1379 loaded, as a security feature that deters exploit attempts
1380 relying on knowledge of the location of kernel internals.
1382 It is the bootloader's job to provide entropy, by passing a
1383 random u64 value in /chosen/kaslr-seed at kernel entry.
1385 When booting via the UEFI stub, it will invoke the firmware's
1386 EFI_RNG_PROTOCOL implementation (if available) to supply entropy
1387 to the kernel proper. In addition, it will randomise the physical
1388 location of the kernel Image as well.
1392 config RANDOMIZE_MODULE_REGION_FULL
1393 bool "Randomize the module region over a 4 GB range"
1394 depends on RANDOMIZE_BASE
1397 Randomizes the location of the module region inside a 4 GB window
1398 covering the core kernel. This way, it is less likely for modules
1399 to leak information about the location of core kernel data structures
1400 but it does imply that function calls between modules and the core
1401 kernel will need to be resolved via veneers in the module PLT.
1403 When this option is not set, the module region will be randomized over
1404 a limited range that contains the [_stext, _etext] interval of the
1405 core kernel, so branch relocations are always in range.
1407 config CC_HAVE_STACKPROTECTOR_SYSREG
1408 def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0)
1410 config STACKPROTECTOR_PER_TASK
1412 depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG
1418 config ARM64_ACPI_PARKING_PROTOCOL
1419 bool "Enable support for the ARM64 ACPI parking protocol"
1422 Enable support for the ARM64 ACPI parking protocol. If disabled
1423 the kernel will not allow booting through the ARM64 ACPI parking
1424 protocol even if the corresponding data is present in the ACPI
1428 string "Default kernel command string"
1431 Provide a set of default command-line options at build time by
1432 entering them here. As a minimum, you should specify the the
1433 root device (e.g. root=/dev/nfs).
1435 config CMDLINE_FORCE
1436 bool "Always use the default kernel command string"
1438 Always use the default kernel command string, even if the boot
1439 loader passes other arguments to the kernel.
1440 This is useful if you cannot or don't want to change the
1441 command-line options your boot loader passes to the kernel.
1447 bool "UEFI runtime support"
1448 depends on OF && !CPU_BIG_ENDIAN
1449 depends on KERNEL_MODE_NEON
1450 select ARCH_SUPPORTS_ACPI
1453 select EFI_PARAMS_FROM_FDT
1454 select EFI_RUNTIME_WRAPPERS
1459 This option provides support for runtime services provided
1460 by UEFI firmware (such as non-volatile variables, realtime
1461 clock, and platform reset). A UEFI stub is also provided to
1462 allow the kernel to be booted as an EFI application. This
1463 is only useful on systems that have UEFI firmware.
1466 bool "Enable support for SMBIOS (DMI) tables"
1470 This enables SMBIOS/DMI feature for systems.
1472 This option is only useful on systems that have UEFI firmware.
1473 However, even with this option, the resultant kernel should
1474 continue to boot on existing non-UEFI platforms.
1479 bool "Kernel support for 32-bit EL0"
1480 depends on ARM64_4K_PAGES || EXPERT
1481 select COMPAT_BINFMT_ELF if BINFMT_ELF
1483 select OLD_SIGSUSPEND3
1484 select COMPAT_OLD_SIGACTION
1486 This option enables support for a 32-bit EL0 running under a 64-bit
1487 kernel at EL1. AArch32-specific components such as system calls,
1488 the user helper functions, VFP support and the ptrace interface are
1489 handled appropriately by the kernel.
1491 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
1492 that you will only be able to execute AArch32 binaries that were compiled
1493 with page size aligned segments.
1495 If you want to execute 32-bit userspace applications, say Y.
1497 config SYSVIPC_COMPAT
1499 depends on COMPAT && SYSVIPC
1501 config ARCH_ENABLE_HUGEPAGE_MIGRATION
1503 depends on HUGETLB_PAGE && MIGRATION
1505 menu "Power management options"
1507 source "kernel/power/Kconfig"
1509 config ARCH_HIBERNATION_POSSIBLE
1513 config ARCH_HIBERNATION_HEADER
1515 depends on HIBERNATION
1517 config ARCH_SUSPEND_POSSIBLE
1522 menu "CPU Power Management"
1524 source "drivers/cpuidle/Kconfig"
1526 source "drivers/cpufreq/Kconfig"
1530 source "drivers/firmware/Kconfig"
1532 source "drivers/acpi/Kconfig"
1534 source "arch/arm64/kvm/Kconfig"
1537 source "arch/arm64/crypto/Kconfig"