3 select ACPI_CCA_REQUIRED if ACPI
4 select ACPI_GENERIC_GSI if ACPI
5 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
6 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
7 select ARCH_HAS_ELF_RANDOMIZE
8 select ARCH_HAS_GCOV_PROFILE_ALL
9 select ARCH_HAS_SG_CHAIN
10 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
11 select ARCH_USE_CMPXCHG_LOCKREF
12 select ARCH_SUPPORTS_ATOMIC_RMW
13 select ARCH_WANT_OPTIONAL_GPIOLIB
14 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
15 select ARCH_WANT_FRAME_POINTERS
19 select AUDIT_ARCH_COMPAT_GENERIC
20 select ARM_GIC_V2M if PCI_MSI
22 select ARM_GIC_V3_ITS if PCI_MSI
24 select BUILDTIME_EXTABLE_SORT
25 select CLONE_BACKWARDS
27 select CPU_PM if (SUSPEND || CPU_IDLE)
28 select DCACHE_WORD_ACCESS
31 select GENERIC_ALLOCATOR
32 select GENERIC_CLOCKEVENTS
33 select GENERIC_CLOCKEVENTS_BROADCAST
34 select GENERIC_CPU_AUTOPROBE
35 select GENERIC_EARLY_IOREMAP
36 select GENERIC_IDLE_POLL_SETUP
37 select GENERIC_IRQ_PROBE
38 select GENERIC_IRQ_SHOW
39 select GENERIC_IRQ_SHOW_LEVEL
40 select GENERIC_PCI_IOMAP
41 select GENERIC_SCHED_CLOCK
42 select GENERIC_SMP_IDLE_THREAD
43 select GENERIC_STRNCPY_FROM_USER
44 select GENERIC_STRNLEN_USER
45 select GENERIC_TIME_VSYSCALL
46 select HANDLE_DOMAIN_IRQ
47 select HARDIRQS_SW_RESEND
48 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
49 select HAVE_ARCH_AUDITSYSCALL
50 select HAVE_ARCH_BITREVERSE
51 select HAVE_ARCH_JUMP_LABEL
52 select HAVE_ARCH_KASAN if SPARSEMEM_VMEMMAP
54 select HAVE_ARCH_SECCOMP_FILTER
55 select HAVE_ARCH_TRACEHOOK
57 select HAVE_C_RECORDMCOUNT
58 select HAVE_CC_STACKPROTECTOR
59 select HAVE_CMPXCHG_DOUBLE
60 select HAVE_CMPXCHG_LOCAL
61 select HAVE_DEBUG_BUGVERBOSE
62 select HAVE_DEBUG_KMEMLEAK
63 select HAVE_DMA_API_DEBUG
65 select HAVE_DMA_CONTIGUOUS
66 select HAVE_DYNAMIC_FTRACE
67 select HAVE_EFFICIENT_UNALIGNED_ACCESS
68 select HAVE_FTRACE_MCOUNT_RECORD
69 select HAVE_FUNCTION_TRACER
70 select HAVE_FUNCTION_GRAPH_TRACER
71 select HAVE_GENERIC_DMA_COHERENT
72 select HAVE_HW_BREAKPOINT if PERF_EVENTS
74 select HAVE_PATA_PLATFORM
75 select HAVE_PERF_EVENTS
77 select HAVE_PERF_USER_STACK_DUMP
78 select HAVE_RCU_TABLE_FREE
79 select HAVE_SYSCALL_TRACEPOINTS
80 select IOMMU_DMA if IOMMU_SUPPORT
82 select IRQ_FORCED_THREADING
83 select MODULES_USE_ELF_RELA
86 select OF_EARLY_FLATTREE
87 select OF_RESERVED_MEM
88 select PERF_USE_VMALLOC
93 select SYSCTL_EXCEPTION_TRACE
94 select HAVE_CONTEXT_TRACKING
96 ARM 64-bit (AArch64) Linux support.
101 config ARCH_PHYS_ADDR_T_64BIT
110 config STACKTRACE_SUPPORT
113 config ILLEGAL_POINTER_VALUE
115 default 0xdead000000000000
117 config LOCKDEP_SUPPORT
120 config TRACE_IRQFLAGS_SUPPORT
123 config RWSEM_XCHGADD_ALGORITHM
130 config GENERIC_BUG_RELATIVE_POINTERS
132 depends on GENERIC_BUG
134 config GENERIC_HWEIGHT
140 config GENERIC_CALIBRATE_DELAY
146 config HAVE_GENERIC_RCU_GUP
149 config ARCH_DMA_ADDR_T_64BIT
152 config NEED_DMA_MAP_STATE
155 config NEED_SG_DMA_LENGTH
167 config KERNEL_MODE_NEON
170 config FIX_EARLYCON_MEM
173 config PGTABLE_LEVELS
175 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
176 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
177 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
178 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
179 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
180 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
182 source "init/Kconfig"
184 source "kernel/Kconfig.freezer"
186 source "arch/arm64/Kconfig.platforms"
193 This feature enables support for PCI bus system. If you say Y
194 here, the kernel will include drivers and infrastructure code
195 to support PCI bus devices.
200 config PCI_DOMAINS_GENERIC
206 source "drivers/pci/Kconfig"
207 source "drivers/pci/pcie/Kconfig"
208 source "drivers/pci/hotplug/Kconfig"
212 menu "Kernel Features"
214 menu "ARM errata workarounds via the alternatives framework"
216 config ARM64_ERRATUM_826319
217 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
220 This option adds an alternative code sequence to work around ARM
221 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
222 AXI master interface and an L2 cache.
224 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
225 and is unable to accept a certain write via this interface, it will
226 not progress on read data presented on the read data channel and the
229 The workaround promotes data cache clean instructions to
230 data cache clean-and-invalidate.
231 Please note that this does not necessarily enable the workaround,
232 as it depends on the alternative framework, which will only patch
233 the kernel if an affected CPU is detected.
237 config ARM64_ERRATUM_827319
238 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
241 This option adds an alternative code sequence to work around ARM
242 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
243 master interface and an L2 cache.
245 Under certain conditions this erratum can cause a clean line eviction
246 to occur at the same time as another transaction to the same address
247 on the AMBA 5 CHI interface, which can cause data corruption if the
248 interconnect reorders the two transactions.
250 The workaround promotes data cache clean instructions to
251 data cache clean-and-invalidate.
252 Please note that this does not necessarily enable the workaround,
253 as it depends on the alternative framework, which will only patch
254 the kernel if an affected CPU is detected.
258 config ARM64_ERRATUM_824069
259 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
262 This option adds an alternative code sequence to work around ARM
263 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
264 to a coherent interconnect.
266 If a Cortex-A53 processor is executing a store or prefetch for
267 write instruction at the same time as a processor in another
268 cluster is executing a cache maintenance operation to the same
269 address, then this erratum might cause a clean cache line to be
270 incorrectly marked as dirty.
272 The workaround promotes data cache clean instructions to
273 data cache clean-and-invalidate.
274 Please note that this option does not necessarily enable the
275 workaround, as it depends on the alternative framework, which will
276 only patch the kernel if an affected CPU is detected.
280 config ARM64_ERRATUM_819472
281 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
284 This option adds an alternative code sequence to work around ARM
285 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
286 present when it is connected to a coherent interconnect.
288 If the processor is executing a load and store exclusive sequence at
289 the same time as a processor in another cluster is executing a cache
290 maintenance operation to the same address, then this erratum might
291 cause data corruption.
293 The workaround promotes data cache clean instructions to
294 data cache clean-and-invalidate.
295 Please note that this does not necessarily enable the workaround,
296 as it depends on the alternative framework, which will only patch
297 the kernel if an affected CPU is detected.
301 config ARM64_ERRATUM_832075
302 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
305 This option adds an alternative code sequence to work around ARM
306 erratum 832075 on Cortex-A57 parts up to r1p2.
308 Affected Cortex-A57 parts might deadlock when exclusive load/store
309 instructions to Write-Back memory are mixed with Device loads.
311 The workaround is to promote device loads to use Load-Acquire
313 Please note that this does not necessarily enable the workaround,
314 as it depends on the alternative framework, which will only patch
315 the kernel if an affected CPU is detected.
319 config ARM64_ERRATUM_845719
320 bool "Cortex-A53: 845719: a load might read incorrect data"
324 This option adds an alternative code sequence to work around ARM
325 erratum 845719 on Cortex-A53 parts up to r0p4.
327 When running a compat (AArch32) userspace on an affected Cortex-A53
328 part, a load at EL0 from a virtual address that matches the bottom 32
329 bits of the virtual address used by a recent load at (AArch64) EL1
330 might return incorrect data.
332 The workaround is to write the contextidr_el1 register on exception
333 return to a 32-bit task.
334 Please note that this does not necessarily enable the workaround,
335 as it depends on the alternative framework, which will only patch
336 the kernel if an affected CPU is detected.
340 config ARM64_ERRATUM_843419
341 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
345 This option builds kernel modules using the large memory model in
346 order to avoid the use of the ADRP instruction, which can cause
347 a subsequent memory access to use an incorrect address on Cortex-A53
350 Note that the kernel itself must be linked with a version of ld
351 which fixes potentially affected ADRP instructions through the
356 config CAVIUM_ERRATUM_22375
357 bool "Cavium erratum 22375, 24313"
360 Enable workaround for erratum 22375, 24313.
362 This implements two gicv3-its errata workarounds for ThunderX. Both
363 with small impact affecting only ITS table allocation.
365 erratum 22375: only alloc 8MB table size
366 erratum 24313: ignore memory access type
368 The fixes are in ITS initialization and basically ignore memory access
369 type and table size provided by the TYPER and BASER registers.
373 config CAVIUM_ERRATUM_23154
374 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
377 The gicv3 of ThunderX requires a modified version for
378 reading the IAR status to ensure data synchronization
379 (access to icc_iar1_el1 is not sync'ed before and after).
388 default ARM64_4K_PAGES
390 Page size (translation granule) configuration.
392 config ARM64_4K_PAGES
395 This feature enables 4KB pages support.
397 config ARM64_16K_PAGES
400 The system will use 16KB pages support. AArch32 emulation
401 requires applications compiled with 16K (or a multiple of 16K)
404 config ARM64_64K_PAGES
407 This feature enables 64KB pages support (4KB by default)
408 allowing only two levels of page tables and faster TLB
409 look-up. AArch32 emulation requires applications compiled
410 with 64K aligned segments.
415 prompt "Virtual address space size"
416 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
417 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
418 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
420 Allows choosing one of multiple possible virtual address
421 space sizes. The level of translation table is determined by
422 a combination of page size and virtual address space size.
424 config ARM64_VA_BITS_36
425 bool "36-bit" if EXPERT
426 depends on ARM64_16K_PAGES
428 config ARM64_VA_BITS_39
430 depends on ARM64_4K_PAGES
432 config ARM64_VA_BITS_42
434 depends on ARM64_64K_PAGES
436 config ARM64_VA_BITS_47
438 depends on ARM64_16K_PAGES
440 config ARM64_VA_BITS_48
447 default 36 if ARM64_VA_BITS_36
448 default 39 if ARM64_VA_BITS_39
449 default 42 if ARM64_VA_BITS_42
450 default 47 if ARM64_VA_BITS_47
451 default 48 if ARM64_VA_BITS_48
453 config CPU_BIG_ENDIAN
454 bool "Build big-endian kernel"
456 Say Y if you plan on running a kernel in big-endian mode.
459 bool "Multi-core scheduler support"
461 Multi-core scheduler support improves the CPU scheduler's decision
462 making when dealing with multi-core CPU chips at a cost of slightly
463 increased overhead in some places. If unsure say N here.
466 bool "SMT scheduler support"
468 Improves the CPU scheduler's decision making when dealing with
469 MultiThreading at a cost of slightly increased overhead in some
470 places. If unsure say N here.
473 int "Maximum number of CPUs (2-4096)"
475 # These have to remain sorted largest to smallest
479 bool "Support for hot-pluggable CPUs"
480 select GENERIC_IRQ_MIGRATION
482 Say Y here to experiment with turning CPUs off and on. CPUs
483 can be controlled through /sys/devices/system/cpu.
485 source kernel/Kconfig.preempt
486 source kernel/Kconfig.hz
488 config ARCH_HAS_HOLES_MEMORYMODEL
489 def_bool y if SPARSEMEM
491 config ARCH_SPARSEMEM_ENABLE
493 select SPARSEMEM_VMEMMAP_ENABLE
495 config ARCH_SPARSEMEM_DEFAULT
496 def_bool ARCH_SPARSEMEM_ENABLE
498 config ARCH_SELECT_MEMORY_MODEL
499 def_bool ARCH_SPARSEMEM_ENABLE
501 config HAVE_ARCH_PFN_VALID
502 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
504 config HW_PERF_EVENTS
508 config SYS_SUPPORTS_HUGETLBFS
511 config ARCH_WANT_GENERAL_HUGETLB
514 config ARCH_WANT_HUGE_PMD_SHARE
515 def_bool y if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
517 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
520 config ARCH_HAS_CACHE_LINE_SIZE
526 bool "Enable seccomp to safely compute untrusted bytecode"
528 This kernel feature is useful for number crunching applications
529 that may need to compute untrusted bytecode during their
530 execution. By using pipes or other transports made available to
531 the process as file descriptors supporting the read/write
532 syscalls, it's possible to isolate those applications in
533 their own address space using seccomp. Once seccomp is
534 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
535 and the task is only allowed to execute a few safe syscalls
536 defined by each seccomp mode.
543 bool "Xen guest support on ARM64"
544 depends on ARM64 && OF
547 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
549 config FORCE_MAX_ZONEORDER
551 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
552 default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE)
555 The kernel memory allocator divides physically contiguous memory
556 blocks into "zones", where each zone is a power of two number of
557 pages. This option selects the largest power of two that the kernel
558 keeps in the memory allocator. If you need to allocate very large
559 blocks of physically contiguous memory, then you may need to
562 This config option is actually maximum order plus one. For example,
563 a value of 11 means that the largest free memory block is 2^10 pages.
565 We make sure that we can allocate upto a HugePage size for each configuration.
567 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
569 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
570 4M allocations matching the default size used by generic code.
572 menuconfig ARMV8_DEPRECATED
573 bool "Emulate deprecated/obsolete ARMv8 instructions"
576 Legacy software support may require certain instructions
577 that have been deprecated or obsoleted in the architecture.
579 Enable this config to enable selective emulation of these
587 bool "Emulate SWP/SWPB instructions"
589 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
590 they are always undefined. Say Y here to enable software
591 emulation of these instructions for userspace using LDXR/STXR.
593 In some older versions of glibc [<=2.8] SWP is used during futex
594 trylock() operations with the assumption that the code will not
595 be preempted. This invalid assumption may be more likely to fail
596 with SWP emulation enabled, leading to deadlock of the user
599 NOTE: when accessing uncached shared regions, LDXR/STXR rely
600 on an external transaction monitoring block called a global
601 monitor to maintain update atomicity. If your system does not
602 implement a global monitor, this option can cause programs that
603 perform SWP operations to uncached memory to deadlock.
607 config CP15_BARRIER_EMULATION
608 bool "Emulate CP15 Barrier instructions"
610 The CP15 barrier instructions - CP15ISB, CP15DSB, and
611 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
612 strongly recommended to use the ISB, DSB, and DMB
613 instructions instead.
615 Say Y here to enable software emulation of these
616 instructions for AArch32 userspace code. When this option is
617 enabled, CP15 barrier usage is traced which can help
618 identify software that needs updating.
622 config SETEND_EMULATION
623 bool "Emulate SETEND instruction"
625 The SETEND instruction alters the data-endianness of the
626 AArch32 EL0, and is deprecated in ARMv8.
628 Say Y here to enable software emulation of the instruction
629 for AArch32 userspace code.
631 Note: All the cpus on the system must have mixed endian support at EL0
632 for this feature to be enabled. If a new CPU - which doesn't support mixed
633 endian - is hotplugged in after this feature has been enabled, there could
634 be unexpected results in the applications.
639 menu "ARMv8.1 architectural features"
641 config ARM64_HW_AFDBM
642 bool "Support for hardware updates of the Access and Dirty page flags"
645 The ARMv8.1 architecture extensions introduce support for
646 hardware updates of the access and dirty information in page
647 table entries. When enabled in TCR_EL1 (HA and HD bits) on
648 capable processors, accesses to pages with PTE_AF cleared will
649 set this bit instead of raising an access flag fault.
650 Similarly, writes to read-only pages with the DBM bit set will
651 clear the read-only bit (AP[2]) instead of raising a
654 Kernels built with this configuration option enabled continue
655 to work on pre-ARMv8.1 hardware and the performance impact is
656 minimal. If unsure, say Y.
659 bool "Enable support for Privileged Access Never (PAN)"
662 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
663 prevents the kernel or hypervisor from accessing user-space (EL0)
666 Choosing this option will cause any unprotected (not using
667 copy_to_user et al) memory access to fail with a permission fault.
669 The feature is detected at runtime, and will remain as a 'nop'
670 instruction if the cpu does not implement the feature.
672 config ARM64_LSE_ATOMICS
673 bool "Atomic instructions"
675 As part of the Large System Extensions, ARMv8.1 introduces new
676 atomic instructions that are designed specifically to scale in
679 Say Y here to make use of these instructions for the in-kernel
680 atomic routines. This incurs a small overhead on CPUs that do
681 not support these instructions and requires the kernel to be
682 built with binutils >= 2.25.
691 string "Default kernel command string"
694 Provide a set of default command-line options at build time by
695 entering them here. As a minimum, you should specify the the
696 root device (e.g. root=/dev/nfs).
699 bool "Always use the default kernel command string"
701 Always use the default kernel command string, even if the boot
702 loader passes other arguments to the kernel.
703 This is useful if you cannot or don't want to change the
704 command-line options your boot loader passes to the kernel.
710 bool "UEFI runtime support"
711 depends on OF && !CPU_BIG_ENDIAN
714 select EFI_PARAMS_FROM_FDT
715 select EFI_RUNTIME_WRAPPERS
720 This option provides support for runtime services provided
721 by UEFI firmware (such as non-volatile variables, realtime
722 clock, and platform reset). A UEFI stub is also provided to
723 allow the kernel to be booted as an EFI application. This
724 is only useful on systems that have UEFI firmware.
727 bool "Enable support for SMBIOS (DMI) tables"
731 This enables SMBIOS/DMI feature for systems.
733 This option is only useful on systems that have UEFI firmware.
734 However, even with this option, the resultant kernel should
735 continue to boot on existing non-UEFI platforms.
739 menu "Userspace binary formats"
741 source "fs/Kconfig.binfmt"
744 bool "Kernel support for 32-bit EL0"
745 depends on ARM64_4K_PAGES || EXPERT
746 select COMPAT_BINFMT_ELF
748 select OLD_SIGSUSPEND3
749 select COMPAT_OLD_SIGACTION
751 This option enables support for a 32-bit EL0 running under a 64-bit
752 kernel at EL1. AArch32-specific components such as system calls,
753 the user helper functions, VFP support and the ptrace interface are
754 handled appropriately by the kernel.
756 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
757 that you will only be able to execute AArch32 binaries that were compiled
758 with page size aligned segments.
760 If you want to execute 32-bit userspace applications, say Y.
762 config SYSVIPC_COMPAT
764 depends on COMPAT && SYSVIPC
768 menu "Power management options"
770 source "kernel/power/Kconfig"
772 config ARCH_SUSPEND_POSSIBLE
777 menu "CPU Power Management"
779 source "drivers/cpuidle/Kconfig"
781 source "drivers/cpufreq/Kconfig"
787 source "drivers/Kconfig"
789 source "drivers/firmware/Kconfig"
791 source "drivers/acpi/Kconfig"
795 source "arch/arm64/kvm/Kconfig"
797 source "arch/arm64/Kconfig.debug"
799 source "security/Kconfig"
801 source "crypto/Kconfig"
803 source "arch/arm64/crypto/Kconfig"