1 # SPDX-License-Identifier: GPL-2.0-only
4 select ACPI_CCA_REQUIRED if ACPI
5 select ACPI_GENERIC_GSI if ACPI
6 select ACPI_GTDT if ACPI
7 select ACPI_IORT if ACPI
8 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
9 select ACPI_MCFG if (ACPI && PCI)
10 select ACPI_SPCR_TABLE if ACPI
11 select ACPI_PPTT if ACPI
12 select ARCH_CLOCKSOURCE_DATA
13 select ARCH_HAS_DEBUG_VIRTUAL
14 select ARCH_HAS_DEVMEM_IS_ALLOWED
15 select ARCH_HAS_DMA_COHERENT_TO_PFN
16 select ARCH_HAS_DMA_MMAP_PGPROT
17 select ARCH_HAS_DMA_PREP_COHERENT
18 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
19 select ARCH_HAS_ELF_RANDOMIZE
20 select ARCH_HAS_FAST_MULTIPLIER
21 select ARCH_HAS_FORTIFY_SOURCE
22 select ARCH_HAS_GCOV_PROFILE_ALL
23 select ARCH_HAS_GIGANTIC_PAGE
25 select ARCH_HAS_KEEPINITRD
26 select ARCH_HAS_MEMBARRIER_SYNC_CORE
27 select ARCH_HAS_PTE_DEVMAP
28 select ARCH_HAS_PTE_SPECIAL
29 select ARCH_HAS_SETUP_DMA_OPS
30 select ARCH_HAS_SET_DIRECT_MAP
31 select ARCH_HAS_SET_MEMORY
32 select ARCH_HAS_STRICT_KERNEL_RWX
33 select ARCH_HAS_STRICT_MODULE_RWX
34 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
35 select ARCH_HAS_SYNC_DMA_FOR_CPU
36 select ARCH_HAS_SYSCALL_WRAPPER
37 select ARCH_HAS_TEARDOWN_DMA_OPS if IOMMU_SUPPORT
38 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
39 select ARCH_HAVE_NMI_SAFE_CMPXCHG
40 select ARCH_INLINE_READ_LOCK if !PREEMPT
41 select ARCH_INLINE_READ_LOCK_BH if !PREEMPT
42 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPT
43 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPT
44 select ARCH_INLINE_READ_UNLOCK if !PREEMPT
45 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPT
46 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPT
47 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPT
48 select ARCH_INLINE_WRITE_LOCK if !PREEMPT
49 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPT
50 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPT
51 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPT
52 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPT
53 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPT
54 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPT
55 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPT
56 select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPT
57 select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPT
58 select ARCH_INLINE_SPIN_LOCK if !PREEMPT
59 select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPT
60 select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPT
61 select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPT
62 select ARCH_INLINE_SPIN_UNLOCK if !PREEMPT
63 select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPT
64 select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPT
65 select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPT
66 select ARCH_KEEP_MEMBLOCK
67 select ARCH_USE_CMPXCHG_LOCKREF
68 select ARCH_USE_QUEUED_RWLOCKS
69 select ARCH_USE_QUEUED_SPINLOCKS
70 select ARCH_SUPPORTS_MEMORY_FAILURE
71 select ARCH_SUPPORTS_ATOMIC_RMW
72 select ARCH_SUPPORTS_INT128 if GCC_VERSION >= 50000 || CC_IS_CLANG
73 select ARCH_SUPPORTS_NUMA_BALANCING
74 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT
75 select ARCH_WANT_FRAME_POINTERS
76 select ARCH_HAS_UBSAN_SANITIZE_ALL
80 select AUDIT_ARCH_COMPAT_GENERIC
81 select ARM_GIC_V2M if PCI
83 select ARM_GIC_V3_ITS if PCI
85 select BUILDTIME_EXTABLE_SORT
86 select CLONE_BACKWARDS
88 select CPU_PM if (SUSPEND || CPU_IDLE)
90 select DCACHE_WORD_ACCESS
91 select DMA_DIRECT_REMAP
94 select GENERIC_ALLOCATOR
95 select GENERIC_ARCH_TOPOLOGY
96 select GENERIC_CLOCKEVENTS
97 select GENERIC_CLOCKEVENTS_BROADCAST
98 select GENERIC_CPU_AUTOPROBE
99 select GENERIC_CPU_VULNERABILITIES
100 select GENERIC_EARLY_IOREMAP
101 select GENERIC_IDLE_POLL_SETUP
102 select GENERIC_IRQ_MULTI_HANDLER
103 select GENERIC_IRQ_PROBE
104 select GENERIC_IRQ_SHOW
105 select GENERIC_IRQ_SHOW_LEVEL
106 select GENERIC_PCI_IOMAP
107 select GENERIC_SCHED_CLOCK
108 select GENERIC_SMP_IDLE_THREAD
109 select GENERIC_STRNCPY_FROM_USER
110 select GENERIC_STRNLEN_USER
111 select GENERIC_TIME_VSYSCALL
112 select GENERIC_GETTIMEOFDAY
113 select GENERIC_COMPAT_VDSO if (!CPU_BIG_ENDIAN && COMPAT)
114 select HANDLE_DOMAIN_IRQ
115 select HARDIRQS_SW_RESEND
117 select HAVE_ACPI_APEI if (ACPI && EFI)
118 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
119 select HAVE_ARCH_AUDITSYSCALL
120 select HAVE_ARCH_BITREVERSE
121 select HAVE_ARCH_HUGE_VMAP
122 select HAVE_ARCH_JUMP_LABEL
123 select HAVE_ARCH_JUMP_LABEL_RELATIVE
124 select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
125 select HAVE_ARCH_KASAN_SW_TAGS if HAVE_ARCH_KASAN
126 select HAVE_ARCH_KGDB
127 select HAVE_ARCH_MMAP_RND_BITS
128 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
129 select HAVE_ARCH_PREL32_RELOCATIONS
130 select HAVE_ARCH_SECCOMP_FILTER
131 select HAVE_ARCH_STACKLEAK
132 select HAVE_ARCH_THREAD_STRUCT_WHITELIST
133 select HAVE_ARCH_TRACEHOOK
134 select HAVE_ARCH_TRANSPARENT_HUGEPAGE
135 select HAVE_ARCH_VMAP_STACK
136 select HAVE_ARM_SMCCC
138 select HAVE_C_RECORDMCOUNT
139 select HAVE_CMPXCHG_DOUBLE
140 select HAVE_CMPXCHG_LOCAL
141 select HAVE_CONTEXT_TRACKING
142 select HAVE_DEBUG_BUGVERBOSE
143 select HAVE_DEBUG_KMEMLEAK
144 select HAVE_DMA_CONTIGUOUS
145 select HAVE_DYNAMIC_FTRACE
146 select HAVE_EFFICIENT_UNALIGNED_ACCESS
148 select HAVE_FTRACE_MCOUNT_RECORD
149 select HAVE_FUNCTION_TRACER
150 select HAVE_FUNCTION_GRAPH_TRACER
151 select HAVE_GCC_PLUGINS
152 select HAVE_HW_BREAKPOINT if PERF_EVENTS
153 select HAVE_IRQ_TIME_ACCOUNTING
154 select HAVE_MEMBLOCK_NODE_MAP if NUMA
156 select HAVE_PATA_PLATFORM
157 select HAVE_PERF_EVENTS
158 select HAVE_PERF_REGS
159 select HAVE_PERF_USER_STACK_DUMP
160 select HAVE_REGS_AND_STACK_ACCESS_API
161 select HAVE_FUNCTION_ARG_ACCESS_API
162 select HAVE_RCU_TABLE_FREE
164 select HAVE_STACKPROTECTOR
165 select HAVE_SYSCALL_TRACEPOINTS
167 select HAVE_KRETPROBES
168 select HAVE_GENERIC_VDSO
169 select IOMMU_DMA if IOMMU_SUPPORT
171 select IRQ_FORCED_THREADING
172 select MODULES_USE_ELF_RELA
173 select NEED_DMA_MAP_STATE
174 select NEED_SG_DMA_LENGTH
176 select OF_EARLY_FLATTREE
177 select PCI_DOMAINS_GENERIC if PCI
178 select PCI_ECAM if (ACPI && PCI)
179 select PCI_SYSCALL if PCI
185 select SYSCTL_EXCEPTION_TRACE
186 select THREAD_INFO_IN_TASK
188 ARM 64-bit (AArch64) Linux support.
196 config ARM64_PAGE_SHIFT
198 default 16 if ARM64_64K_PAGES
199 default 14 if ARM64_16K_PAGES
202 config ARM64_CONT_SHIFT
204 default 5 if ARM64_64K_PAGES
205 default 7 if ARM64_16K_PAGES
208 config ARCH_MMAP_RND_BITS_MIN
209 default 14 if ARM64_64K_PAGES
210 default 16 if ARM64_16K_PAGES
213 # max bits determined by the following formula:
214 # VA_BITS - PAGE_SHIFT - 3
215 config ARCH_MMAP_RND_BITS_MAX
216 default 19 if ARM64_VA_BITS=36
217 default 24 if ARM64_VA_BITS=39
218 default 27 if ARM64_VA_BITS=42
219 default 30 if ARM64_VA_BITS=47
220 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
221 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
222 default 33 if ARM64_VA_BITS=48
223 default 14 if ARM64_64K_PAGES
224 default 16 if ARM64_16K_PAGES
227 config ARCH_MMAP_RND_COMPAT_BITS_MIN
228 default 7 if ARM64_64K_PAGES
229 default 9 if ARM64_16K_PAGES
232 config ARCH_MMAP_RND_COMPAT_BITS_MAX
238 config STACKTRACE_SUPPORT
241 config ILLEGAL_POINTER_VALUE
243 default 0xdead000000000000
245 config LOCKDEP_SUPPORT
248 config TRACE_IRQFLAGS_SUPPORT
255 config GENERIC_BUG_RELATIVE_POINTERS
257 depends on GENERIC_BUG
259 config GENERIC_HWEIGHT
265 config GENERIC_CALIBRATE_DELAY
269 bool "Support DMA32 zone" if EXPERT
272 config ARCH_ENABLE_MEMORY_HOTPLUG
278 config KERNEL_MODE_NEON
281 config FIX_EARLYCON_MEM
284 config PGTABLE_LEVELS
286 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
287 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
288 default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_USER_VA_BITS_52)
289 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
290 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
291 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
293 config ARCH_SUPPORTS_UPROBES
296 config ARCH_PROC_KCORE_TEXT
299 source "arch/arm64/Kconfig.platforms"
301 menu "Kernel Features"
303 menu "ARM errata workarounds via the alternatives framework"
305 config ARM64_WORKAROUND_CLEAN_CACHE
308 config ARM64_ERRATUM_826319
309 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
311 select ARM64_WORKAROUND_CLEAN_CACHE
313 This option adds an alternative code sequence to work around ARM
314 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
315 AXI master interface and an L2 cache.
317 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
318 and is unable to accept a certain write via this interface, it will
319 not progress on read data presented on the read data channel and the
322 The workaround promotes data cache clean instructions to
323 data cache clean-and-invalidate.
324 Please note that this does not necessarily enable the workaround,
325 as it depends on the alternative framework, which will only patch
326 the kernel if an affected CPU is detected.
330 config ARM64_ERRATUM_827319
331 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
333 select ARM64_WORKAROUND_CLEAN_CACHE
335 This option adds an alternative code sequence to work around ARM
336 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
337 master interface and an L2 cache.
339 Under certain conditions this erratum can cause a clean line eviction
340 to occur at the same time as another transaction to the same address
341 on the AMBA 5 CHI interface, which can cause data corruption if the
342 interconnect reorders the two transactions.
344 The workaround promotes data cache clean instructions to
345 data cache clean-and-invalidate.
346 Please note that this does not necessarily enable the workaround,
347 as it depends on the alternative framework, which will only patch
348 the kernel if an affected CPU is detected.
352 config ARM64_ERRATUM_824069
353 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
355 select ARM64_WORKAROUND_CLEAN_CACHE
357 This option adds an alternative code sequence to work around ARM
358 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
359 to a coherent interconnect.
361 If a Cortex-A53 processor is executing a store or prefetch for
362 write instruction at the same time as a processor in another
363 cluster is executing a cache maintenance operation to the same
364 address, then this erratum might cause a clean cache line to be
365 incorrectly marked as dirty.
367 The workaround promotes data cache clean instructions to
368 data cache clean-and-invalidate.
369 Please note that this option does not necessarily enable the
370 workaround, as it depends on the alternative framework, which will
371 only patch the kernel if an affected CPU is detected.
375 config ARM64_ERRATUM_819472
376 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
378 select ARM64_WORKAROUND_CLEAN_CACHE
380 This option adds an alternative code sequence to work around ARM
381 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
382 present when it is connected to a coherent interconnect.
384 If the processor is executing a load and store exclusive sequence at
385 the same time as a processor in another cluster is executing a cache
386 maintenance operation to the same address, then this erratum might
387 cause data corruption.
389 The workaround promotes data cache clean instructions to
390 data cache clean-and-invalidate.
391 Please note that this does not necessarily enable the workaround,
392 as it depends on the alternative framework, which will only patch
393 the kernel if an affected CPU is detected.
397 config ARM64_ERRATUM_832075
398 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
401 This option adds an alternative code sequence to work around ARM
402 erratum 832075 on Cortex-A57 parts up to r1p2.
404 Affected Cortex-A57 parts might deadlock when exclusive load/store
405 instructions to Write-Back memory are mixed with Device loads.
407 The workaround is to promote device loads to use Load-Acquire
409 Please note that this does not necessarily enable the workaround,
410 as it depends on the alternative framework, which will only patch
411 the kernel if an affected CPU is detected.
415 config ARM64_ERRATUM_834220
416 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
420 This option adds an alternative code sequence to work around ARM
421 erratum 834220 on Cortex-A57 parts up to r1p2.
423 Affected Cortex-A57 parts might report a Stage 2 translation
424 fault as the result of a Stage 1 fault for load crossing a
425 page boundary when there is a permission or device memory
426 alignment fault at Stage 1 and a translation fault at Stage 2.
428 The workaround is to verify that the Stage 1 translation
429 doesn't generate a fault before handling the Stage 2 fault.
430 Please note that this does not necessarily enable the workaround,
431 as it depends on the alternative framework, which will only patch
432 the kernel if an affected CPU is detected.
436 config ARM64_ERRATUM_845719
437 bool "Cortex-A53: 845719: a load might read incorrect data"
441 This option adds an alternative code sequence to work around ARM
442 erratum 845719 on Cortex-A53 parts up to r0p4.
444 When running a compat (AArch32) userspace on an affected Cortex-A53
445 part, a load at EL0 from a virtual address that matches the bottom 32
446 bits of the virtual address used by a recent load at (AArch64) EL1
447 might return incorrect data.
449 The workaround is to write the contextidr_el1 register on exception
450 return to a 32-bit task.
451 Please note that this does not necessarily enable the workaround,
452 as it depends on the alternative framework, which will only patch
453 the kernel if an affected CPU is detected.
457 config ARM64_ERRATUM_843419
458 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
460 select ARM64_MODULE_PLTS if MODULES
462 This option links the kernel with '--fix-cortex-a53-843419' and
463 enables PLT support to replace certain ADRP instructions, which can
464 cause subsequent memory accesses to use an incorrect address on
465 Cortex-A53 parts up to r0p4.
469 config ARM64_ERRATUM_1024718
470 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update"
473 This option adds a workaround for ARM Cortex-A55 Erratum 1024718.
475 Affected Cortex-A55 cores (r0p0, r0p1, r1p0) could cause incorrect
476 update of the hardware dirty bit when the DBM/AP bits are updated
477 without a break-before-make. The workaround is to disable the usage
478 of hardware DBM locally on the affected cores. CPUs not affected by
479 this erratum will continue to use the feature.
483 config ARM64_ERRATUM_1418040
484 bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result"
488 This option adds a workaround for ARM Cortex-A76/Neoverse-N1
489 errata 1188873 and 1418040.
491 Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could
492 cause register corruption when accessing the timer registers
493 from AArch32 userspace.
497 config ARM64_ERRATUM_1165522
498 bool "Cortex-A76: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
501 This option adds a workaround for ARM Cortex-A76 erratum 1165522.
503 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with
504 corrupted TLBs by speculating an AT instruction during a guest
509 config ARM64_ERRATUM_1286807
510 bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation"
512 select ARM64_WORKAROUND_REPEAT_TLBI
514 This option adds a workaround for ARM Cortex-A76 erratum 1286807.
516 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual
517 address for a cacheable mapping of a location is being
518 accessed by a core while another core is remapping the virtual
519 address to a new physical page using the recommended
520 break-before-make sequence, then under very rare circumstances
521 TLBI+DSB completes before a read using the translation being
522 invalidated has been observed by other observers. The
523 workaround repeats the TLBI+DSB operation.
527 config ARM64_ERRATUM_1463225
528 bool "Cortex-A76: Software Step might prevent interrupt recognition"
531 This option adds a workaround for Arm Cortex-A76 erratum 1463225.
533 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping
534 of a system call instruction (SVC) can prevent recognition of
535 subsequent interrupts when software stepping is disabled in the
536 exception handler of the system call and either kernel debugging
537 is enabled or VHE is in use.
539 Work around the erratum by triggering a dummy step exception
540 when handling a system call from a task that is being stepped
541 in a VHE configuration of the kernel.
545 config CAVIUM_ERRATUM_22375
546 bool "Cavium erratum 22375, 24313"
549 Enable workaround for errata 22375 and 24313.
551 This implements two gicv3-its errata workarounds for ThunderX. Both
552 with a small impact affecting only ITS table allocation.
554 erratum 22375: only alloc 8MB table size
555 erratum 24313: ignore memory access type
557 The fixes are in ITS initialization and basically ignore memory access
558 type and table size provided by the TYPER and BASER registers.
562 config CAVIUM_ERRATUM_23144
563 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
567 ITS SYNC command hang for cross node io and collections/cpu mapping.
571 config CAVIUM_ERRATUM_23154
572 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
575 The gicv3 of ThunderX requires a modified version for
576 reading the IAR status to ensure data synchronization
577 (access to icc_iar1_el1 is not sync'ed before and after).
581 config CAVIUM_ERRATUM_27456
582 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
585 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
586 instructions may cause the icache to become corrupted if it
587 contains data for a non-current ASID. The fix is to
588 invalidate the icache when changing the mm context.
592 config CAVIUM_ERRATUM_30115
593 bool "Cavium erratum 30115: Guest may disable interrupts in host"
596 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through
597 1.2, and T83 Pass 1.0, KVM guest execution may disable
598 interrupts in host. Trapping both GICv3 group-0 and group-1
599 accesses sidesteps the issue.
603 config QCOM_FALKOR_ERRATUM_1003
604 bool "Falkor E1003: Incorrect translation due to ASID change"
607 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
608 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID
609 in TTBR1_EL1, this situation only occurs in the entry trampoline and
610 then only for entries in the walk cache, since the leaf translation
611 is unchanged. Work around the erratum by invalidating the walk cache
612 entries for the trampoline before entering the kernel proper.
614 config ARM64_WORKAROUND_REPEAT_TLBI
617 config QCOM_FALKOR_ERRATUM_1009
618 bool "Falkor E1009: Prematurely complete a DSB after a TLBI"
620 select ARM64_WORKAROUND_REPEAT_TLBI
622 On Falkor v1, the CPU may prematurely complete a DSB following a
623 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation
624 one more time to fix the issue.
628 config QCOM_QDF2400_ERRATUM_0065
629 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size"
632 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports
633 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have
634 been indicated as 16Bytes (0xf), not 8Bytes (0x7).
638 config SOCIONEXT_SYNQUACER_PREITS
639 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
642 Socionext Synquacer SoCs implement a separate h/w block to generate
643 MSI doorbell writes with non-zero values for the device ID.
647 config HISILICON_ERRATUM_161600802
648 bool "Hip07 161600802: Erroneous redistributor VLPI base"
651 The HiSilicon Hip07 SoC uses the wrong redistributor base
652 when issued ITS commands such as VMOVP and VMAPP, and requires
653 a 128kB offset to be applied to the target address in this commands.
657 config QCOM_FALKOR_ERRATUM_E1041
658 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access"
661 Falkor CPU may speculatively fetch instructions from an improper
662 memory location when MMU translation is changed from SCTLR_ELn[M]=1
663 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem.
667 config FUJITSU_ERRATUM_010001
668 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly"
671 This option adds a workaround for Fujitsu-A64FX erratum E#010001.
672 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory
673 accesses may cause undefined fault (Data abort, DFSC=0b111111).
674 This fault occurs under a specific hardware condition when a
675 load/store instruction performs an address translation using:
676 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1.
677 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1.
678 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1.
679 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1.
681 The workaround is to ensure these bits are clear in TCR_ELx.
682 The workaround only affects the Fujitsu-A64FX.
691 default ARM64_4K_PAGES
693 Page size (translation granule) configuration.
695 config ARM64_4K_PAGES
698 This feature enables 4KB pages support.
700 config ARM64_16K_PAGES
703 The system will use 16KB pages support. AArch32 emulation
704 requires applications compiled with 16K (or a multiple of 16K)
707 config ARM64_64K_PAGES
710 This feature enables 64KB pages support (4KB by default)
711 allowing only two levels of page tables and faster TLB
712 look-up. AArch32 emulation requires applications compiled
713 with 64K aligned segments.
718 prompt "Virtual address space size"
719 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
720 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
721 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
723 Allows choosing one of multiple possible virtual address
724 space sizes. The level of translation table is determined by
725 a combination of page size and virtual address space size.
727 config ARM64_VA_BITS_36
728 bool "36-bit" if EXPERT
729 depends on ARM64_16K_PAGES
731 config ARM64_VA_BITS_39
733 depends on ARM64_4K_PAGES
735 config ARM64_VA_BITS_42
737 depends on ARM64_64K_PAGES
739 config ARM64_VA_BITS_47
741 depends on ARM64_16K_PAGES
743 config ARM64_VA_BITS_48
746 config ARM64_USER_VA_BITS_52
748 depends on ARM64_64K_PAGES && (ARM64_PAN || !ARM64_SW_TTBR0_PAN)
750 Enable 52-bit virtual addressing for userspace when explicitly
751 requested via a hint to mmap(). The kernel will continue to
752 use 48-bit virtual addresses for its own mappings.
754 NOTE: Enabling 52-bit virtual addressing in conjunction with
755 ARMv8.3 Pointer Authentication will result in the PAC being
756 reduced from 7 bits to 3 bits, which may have a significant
757 impact on its susceptibility to brute-force attacks.
759 If unsure, select 48-bit virtual addressing instead.
763 config ARM64_FORCE_52BIT
764 bool "Force 52-bit virtual addresses for userspace"
765 depends on ARM64_USER_VA_BITS_52 && EXPERT
767 For systems with 52-bit userspace VAs enabled, the kernel will attempt
768 to maintain compatibility with older software by providing 48-bit VAs
769 unless a hint is supplied to mmap.
771 This configuration option disables the 48-bit compatibility logic, and
772 forces all userspace addresses to be 52-bit on HW that supports it. One
773 should only enable this configuration option for stress testing userspace
774 memory management code. If unsure say N here.
778 default 36 if ARM64_VA_BITS_36
779 default 39 if ARM64_VA_BITS_39
780 default 42 if ARM64_VA_BITS_42
781 default 47 if ARM64_VA_BITS_47
782 default 48 if ARM64_VA_BITS_48 || ARM64_USER_VA_BITS_52
785 prompt "Physical address space size"
786 default ARM64_PA_BITS_48
788 Choose the maximum physical address range that the kernel will
791 config ARM64_PA_BITS_48
794 config ARM64_PA_BITS_52
795 bool "52-bit (ARMv8.2)"
796 depends on ARM64_64K_PAGES
797 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
799 Enable support for a 52-bit physical address space, introduced as
800 part of the ARMv8.2-LPA extension.
802 With this enabled, the kernel will also continue to work on CPUs that
803 do not support ARMv8.2-LPA, but with some added memory overhead (and
804 minor performance overhead).
810 default 48 if ARM64_PA_BITS_48
811 default 52 if ARM64_PA_BITS_52
813 config CPU_BIG_ENDIAN
814 bool "Build big-endian kernel"
816 Say Y if you plan on running a kernel in big-endian mode.
819 bool "Multi-core scheduler support"
821 Multi-core scheduler support improves the CPU scheduler's decision
822 making when dealing with multi-core CPU chips at a cost of slightly
823 increased overhead in some places. If unsure say N here.
826 bool "SMT scheduler support"
828 Improves the CPU scheduler's decision making when dealing with
829 MultiThreading at a cost of slightly increased overhead in some
830 places. If unsure say N here.
833 int "Maximum number of CPUs (2-4096)"
838 bool "Support for hot-pluggable CPUs"
839 select GENERIC_IRQ_MIGRATION
841 Say Y here to experiment with turning CPUs off and on. CPUs
842 can be controlled through /sys/devices/system/cpu.
844 # Common NUMA Features
846 bool "Numa Memory Allocation and Scheduler Support"
847 select ACPI_NUMA if ACPI
850 Enable NUMA (Non Uniform Memory Access) support.
852 The kernel will try to allocate memory used by a CPU on the
853 local memory of the CPU and add some more
854 NUMA awareness to the kernel.
857 int "Maximum NUMA Nodes (as a power of 2)"
860 depends on NEED_MULTIPLE_NODES
862 Specify the maximum number of NUMA Nodes available on the target
863 system. Increases memory reserved to accommodate various tables.
865 config USE_PERCPU_NUMA_NODE_ID
869 config HAVE_SETUP_PER_CPU_AREA
873 config NEED_PER_CPU_EMBED_FIRST_CHUNK
880 source "kernel/Kconfig.hz"
882 config ARCH_SUPPORTS_DEBUG_PAGEALLOC
885 config ARCH_SPARSEMEM_ENABLE
887 select SPARSEMEM_VMEMMAP_ENABLE
889 config ARCH_SPARSEMEM_DEFAULT
890 def_bool ARCH_SPARSEMEM_ENABLE
892 config ARCH_SELECT_MEMORY_MODEL
893 def_bool ARCH_SPARSEMEM_ENABLE
895 config ARCH_FLATMEM_ENABLE
898 config HAVE_ARCH_PFN_VALID
901 config HW_PERF_EVENTS
905 config SYS_SUPPORTS_HUGETLBFS
908 config ARCH_WANT_HUGE_PMD_SHARE
909 def_bool y if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
911 config ARCH_HAS_CACHE_LINE_SIZE
914 config ARCH_ENABLE_SPLIT_PMD_PTLOCK
915 def_bool y if PGTABLE_LEVELS > 2
918 bool "Enable seccomp to safely compute untrusted bytecode"
920 This kernel feature is useful for number crunching applications
921 that may need to compute untrusted bytecode during their
922 execution. By using pipes or other transports made available to
923 the process as file descriptors supporting the read/write
924 syscalls, it's possible to isolate those applications in
925 their own address space using seccomp. Once seccomp is
926 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
927 and the task is only allowed to execute a few safe syscalls
928 defined by each seccomp mode.
931 bool "Enable paravirtualization code"
933 This changes the kernel so it can modify itself when it is run
934 under a hypervisor, potentially improving performance significantly
935 over full virtualization.
937 config PARAVIRT_TIME_ACCOUNTING
938 bool "Paravirtual steal time accounting"
941 Select this option to enable fine granularity task steal time
942 accounting. Time spent executing other tasks in parallel with
943 the current vCPU is discounted from the vCPU power. To account for
944 that, there can be a small performance impact.
946 If in doubt, say N here.
949 depends on PM_SLEEP_SMP
951 bool "kexec system call"
953 kexec is a system call that implements the ability to shutdown your
954 current kernel, and to start another kernel. It is like a reboot
955 but it is independent of the system firmware. And like a reboot
956 you can start any kernel with it, not just Linux.
959 bool "kexec file based system call"
962 This is new version of kexec system call. This system call is
963 file based and takes file descriptors as system call argument
964 for kernel and initramfs as opposed to list of segments as
965 accepted by previous system call.
967 config KEXEC_VERIFY_SIG
968 bool "Verify kernel signature during kexec_file_load() syscall"
969 depends on KEXEC_FILE
971 Select this option to verify a signature with loaded kernel
972 image. If configured, any attempt of loading a image without
973 valid signature will fail.
975 In addition to that option, you need to enable signature
976 verification for the corresponding kernel image type being
977 loaded in order for this to work.
979 config KEXEC_IMAGE_VERIFY_SIG
980 bool "Enable Image signature verification support"
982 depends on KEXEC_VERIFY_SIG
983 depends on EFI && SIGNED_PE_FILE_VERIFICATION
985 Enable Image signature verification support.
987 comment "Support for PE file signature verification disabled"
988 depends on KEXEC_VERIFY_SIG
989 depends on !EFI || !SIGNED_PE_FILE_VERIFICATION
992 bool "Build kdump crash kernel"
994 Generate crash dump after being started by kexec. This should
995 be normally only set in special crash dump kernels which are
996 loaded in the main kernel with kexec-tools into a specially
997 reserved region and then later executed after a crash by
1000 For more details see Documentation/admin-guide/kdump/kdump.rst
1007 bool "Xen guest support on ARM64"
1008 depends on ARM64 && OF
1012 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
1014 config FORCE_MAX_ZONEORDER
1016 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
1017 default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE)
1020 The kernel memory allocator divides physically contiguous memory
1021 blocks into "zones", where each zone is a power of two number of
1022 pages. This option selects the largest power of two that the kernel
1023 keeps in the memory allocator. If you need to allocate very large
1024 blocks of physically contiguous memory, then you may need to
1025 increase this value.
1027 This config option is actually maximum order plus one. For example,
1028 a value of 11 means that the largest free memory block is 2^10 pages.
1030 We make sure that we can allocate upto a HugePage size for each configuration.
1032 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
1034 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
1035 4M allocations matching the default size used by generic code.
1037 config UNMAP_KERNEL_AT_EL0
1038 bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT
1041 Speculation attacks against some high-performance processors can
1042 be used to bypass MMU permission checks and leak kernel data to
1043 userspace. This can be defended against by unmapping the kernel
1044 when running in userspace, mapping it back in on exception entry
1045 via a trampoline page in the vector table.
1049 config HARDEN_BRANCH_PREDICTOR
1050 bool "Harden the branch predictor against aliasing attacks" if EXPERT
1053 Speculation attacks against some high-performance processors rely on
1054 being able to manipulate the branch predictor for a victim context by
1055 executing aliasing branches in the attacker context. Such attacks
1056 can be partially mitigated against by clearing internal branch
1057 predictor state and limiting the prediction logic in some situations.
1059 This config option will take CPU-specific actions to harden the
1060 branch predictor against aliasing attacks and may rely on specific
1061 instruction sequences or control bits being set by the system
1066 config HARDEN_EL2_VECTORS
1067 bool "Harden EL2 vector mapping against system register leak" if EXPERT
1070 Speculation attacks against some high-performance processors can
1071 be used to leak privileged information such as the vector base
1072 register, resulting in a potential defeat of the EL2 layout
1075 This config option will map the vectors to a fixed location,
1076 independent of the EL2 code mapping, so that revealing VBAR_EL2
1077 to an attacker does not give away any extra information. This
1078 only gets enabled on affected CPUs.
1083 bool "Speculative Store Bypass Disable" if EXPERT
1086 This enables mitigation of the bypassing of previous stores
1087 by speculative loads.
1091 config RODATA_FULL_DEFAULT_ENABLED
1092 bool "Apply r/o permissions of VM areas also to their linear aliases"
1095 Apply read-only attributes of VM areas to the linear alias of
1096 the backing pages as well. This prevents code or read-only data
1097 from being modified (inadvertently or intentionally) via another
1098 mapping of the same memory page. This additional enhancement can
1099 be turned off at runtime by passing rodata=[off|on] (and turned on
1100 with rodata=full if this option is set to 'n')
1102 This requires the linear region to be mapped down to pages,
1103 which may adversely affect performance in some cases.
1105 config ARM64_SW_TTBR0_PAN
1106 bool "Emulate Privileged Access Never using TTBR0_EL1 switching"
1108 Enabling this option prevents the kernel from accessing
1109 user-space memory directly by pointing TTBR0_EL1 to a reserved
1110 zeroed area and reserved ASID. The user access routines
1111 restore the valid TTBR0_EL1 temporarily.
1114 bool "Kernel support for 32-bit EL0"
1115 depends on ARM64_4K_PAGES || EXPERT
1116 select COMPAT_BINFMT_ELF if BINFMT_ELF
1118 select OLD_SIGSUSPEND3
1119 select COMPAT_OLD_SIGACTION
1121 This option enables support for a 32-bit EL0 running under a 64-bit
1122 kernel at EL1. AArch32-specific components such as system calls,
1123 the user helper functions, VFP support and the ptrace interface are
1124 handled appropriately by the kernel.
1126 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
1127 that you will only be able to execute AArch32 binaries that were compiled
1128 with page size aligned segments.
1130 If you want to execute 32-bit userspace applications, say Y.
1134 config KUSER_HELPERS
1135 bool "Enable kuser helpers page for 32 bit applications"
1138 Warning: disabling this option may break 32-bit user programs.
1140 Provide kuser helpers to compat tasks. The kernel provides
1141 helper code to userspace in read only form at a fixed location
1142 to allow userspace to be independent of the CPU type fitted to
1143 the system. This permits binaries to be run on ARMv4 through
1144 to ARMv8 without modification.
1146 See Documentation/arm/kernel_user_helpers.rst for details.
1148 However, the fixed address nature of these helpers can be used
1149 by ROP (return orientated programming) authors when creating
1152 If all of the binaries and libraries which run on your platform
1153 are built specifically for your platform, and make no use of
1154 these helpers, then you can turn this option off to hinder
1155 such exploits. However, in that case, if a binary or library
1156 relying on those helpers is run, it will not function correctly.
1158 Say N here only if you are absolutely certain that you do not
1159 need these helpers; otherwise, the safe option is to say Y.
1162 menuconfig ARMV8_DEPRECATED
1163 bool "Emulate deprecated/obsolete ARMv8 instructions"
1166 Legacy software support may require certain instructions
1167 that have been deprecated or obsoleted in the architecture.
1169 Enable this config to enable selective emulation of these
1176 config SWP_EMULATION
1177 bool "Emulate SWP/SWPB instructions"
1179 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
1180 they are always undefined. Say Y here to enable software
1181 emulation of these instructions for userspace using LDXR/STXR.
1183 In some older versions of glibc [<=2.8] SWP is used during futex
1184 trylock() operations with the assumption that the code will not
1185 be preempted. This invalid assumption may be more likely to fail
1186 with SWP emulation enabled, leading to deadlock of the user
1189 NOTE: when accessing uncached shared regions, LDXR/STXR rely
1190 on an external transaction monitoring block called a global
1191 monitor to maintain update atomicity. If your system does not
1192 implement a global monitor, this option can cause programs that
1193 perform SWP operations to uncached memory to deadlock.
1197 config CP15_BARRIER_EMULATION
1198 bool "Emulate CP15 Barrier instructions"
1200 The CP15 barrier instructions - CP15ISB, CP15DSB, and
1201 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
1202 strongly recommended to use the ISB, DSB, and DMB
1203 instructions instead.
1205 Say Y here to enable software emulation of these
1206 instructions for AArch32 userspace code. When this option is
1207 enabled, CP15 barrier usage is traced which can help
1208 identify software that needs updating.
1212 config SETEND_EMULATION
1213 bool "Emulate SETEND instruction"
1215 The SETEND instruction alters the data-endianness of the
1216 AArch32 EL0, and is deprecated in ARMv8.
1218 Say Y here to enable software emulation of the instruction
1219 for AArch32 userspace code.
1221 Note: All the cpus on the system must have mixed endian support at EL0
1222 for this feature to be enabled. If a new CPU - which doesn't support mixed
1223 endian - is hotplugged in after this feature has been enabled, there could
1224 be unexpected results in the applications.
1231 menu "ARMv8.1 architectural features"
1233 config ARM64_HW_AFDBM
1234 bool "Support for hardware updates of the Access and Dirty page flags"
1237 The ARMv8.1 architecture extensions introduce support for
1238 hardware updates of the access and dirty information in page
1239 table entries. When enabled in TCR_EL1 (HA and HD bits) on
1240 capable processors, accesses to pages with PTE_AF cleared will
1241 set this bit instead of raising an access flag fault.
1242 Similarly, writes to read-only pages with the DBM bit set will
1243 clear the read-only bit (AP[2]) instead of raising a
1246 Kernels built with this configuration option enabled continue
1247 to work on pre-ARMv8.1 hardware and the performance impact is
1248 minimal. If unsure, say Y.
1251 bool "Enable support for Privileged Access Never (PAN)"
1254 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
1255 prevents the kernel or hypervisor from accessing user-space (EL0)
1258 Choosing this option will cause any unprotected (not using
1259 copy_to_user et al) memory access to fail with a permission fault.
1261 The feature is detected at runtime, and will remain as a 'nop'
1262 instruction if the cpu does not implement the feature.
1264 config ARM64_LSE_ATOMICS
1265 bool "Atomic instructions"
1268 As part of the Large System Extensions, ARMv8.1 introduces new
1269 atomic instructions that are designed specifically to scale in
1272 Say Y here to make use of these instructions for the in-kernel
1273 atomic routines. This incurs a small overhead on CPUs that do
1274 not support these instructions and requires the kernel to be
1275 built with binutils >= 2.25 in order for the new instructions
1279 bool "Enable support for Virtualization Host Extensions (VHE)"
1282 Virtualization Host Extensions (VHE) allow the kernel to run
1283 directly at EL2 (instead of EL1) on processors that support
1284 it. This leads to better performance for KVM, as they reduce
1285 the cost of the world switch.
1287 Selecting this option allows the VHE feature to be detected
1288 at runtime, and does not affect processors that do not
1289 implement this feature.
1293 menu "ARMv8.2 architectural features"
1296 bool "Enable support for User Access Override (UAO)"
1299 User Access Override (UAO; part of the ARMv8.2 Extensions)
1300 causes the 'unprivileged' variant of the load/store instructions to
1301 be overridden to be privileged.
1303 This option changes get_user() and friends to use the 'unprivileged'
1304 variant of the load/store instructions. This ensures that user-space
1305 really did have access to the supplied memory. When addr_limit is
1306 set to kernel memory the UAO bit will be set, allowing privileged
1307 access to kernel memory.
1309 Choosing this option will cause copy_to_user() et al to use user-space
1312 The feature is detected at runtime, the kernel will use the
1313 regular load/store instructions if the cpu does not implement the
1317 bool "Enable support for persistent memory"
1318 select ARCH_HAS_PMEM_API
1319 select ARCH_HAS_UACCESS_FLUSHCACHE
1321 Say Y to enable support for the persistent memory API based on the
1322 ARMv8.2 DCPoP feature.
1324 The feature is detected at runtime, and the kernel will use DC CVAC
1325 operations if DC CVAP is not supported (following the behaviour of
1326 DC CVAP itself if the system does not define a point of persistence).
1328 config ARM64_RAS_EXTN
1329 bool "Enable support for RAS CPU Extensions"
1332 CPUs that support the Reliability, Availability and Serviceability
1333 (RAS) Extensions, part of ARMv8.2 are able to track faults and
1334 errors, classify them and report them to software.
1336 On CPUs with these extensions system software can use additional
1337 barriers to determine if faults are pending and read the
1338 classification from a new set of registers.
1340 Selecting this feature will allow the kernel to use these barriers
1341 and access the new registers if the system supports the extension.
1342 Platform RAS features may additionally depend on firmware support.
1345 bool "Enable support for Common Not Private (CNP) translations"
1347 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
1349 Common Not Private (CNP) allows translation table entries to
1350 be shared between different PEs in the same inner shareable
1351 domain, so the hardware can use this fact to optimise the
1352 caching of such entries in the TLB.
1354 Selecting this option allows the CNP feature to be detected
1355 at runtime, and does not affect PEs that do not implement
1360 menu "ARMv8.3 architectural features"
1362 config ARM64_PTR_AUTH
1363 bool "Enable support for pointer authentication"
1365 depends on !KVM || ARM64_VHE
1367 Pointer authentication (part of the ARMv8.3 Extensions) provides
1368 instructions for signing and authenticating pointers against secret
1369 keys, which can be used to mitigate Return Oriented Programming (ROP)
1372 This option enables these instructions at EL0 (i.e. for userspace).
1374 Choosing this option will cause the kernel to initialise secret keys
1375 for each process at exec() time, with these keys being
1376 context-switched along with the process.
1378 The feature is detected at runtime. If the feature is not present in
1379 hardware it will not be advertised to userspace/KVM guest nor will it
1380 be enabled. However, KVM guest also require VHE mode and hence
1381 CONFIG_ARM64_VHE=y option to use this feature.
1386 bool "ARM Scalable Vector Extension support"
1388 depends on !KVM || ARM64_VHE
1390 The Scalable Vector Extension (SVE) is an extension to the AArch64
1391 execution state which complements and extends the SIMD functionality
1392 of the base architecture to support much larger vectors and to enable
1393 additional vectorisation opportunities.
1395 To enable use of this extension on CPUs that implement it, say Y.
1397 On CPUs that support the SVE2 extensions, this option will enable
1400 Note that for architectural reasons, firmware _must_ implement SVE
1401 support when running on SVE capable hardware. The required support
1404 * version 1.5 and later of the ARM Trusted Firmware
1405 * the AArch64 boot wrapper since commit 5e1261e08abf
1406 ("bootwrapper: SVE: Enable SVE for EL2 and below").
1408 For other firmware implementations, consult the firmware documentation
1411 If you need the kernel to boot on SVE-capable hardware with broken
1412 firmware, you may need to say N here until you get your firmware
1413 fixed. Otherwise, you may experience firmware panics or lockups when
1414 booting the kernel. If unsure and you are not observing these
1415 symptoms, you should assume that it is safe to say Y.
1417 CPUs that support SVE are architecturally required to support the
1418 Virtualization Host Extensions (VHE), so the kernel makes no
1419 provision for supporting SVE alongside KVM without VHE enabled.
1420 Thus, you will need to enable CONFIG_ARM64_VHE if you want to support
1421 KVM in the same kernel image.
1423 config ARM64_MODULE_PLTS
1424 bool "Use PLTs to allow module memory to spill over into vmalloc area"
1426 select HAVE_MOD_ARCH_SPECIFIC
1428 Allocate PLTs when loading modules so that jumps and calls whose
1429 targets are too far away for their relative offsets to be encoded
1430 in the instructions themselves can be bounced via veneers in the
1431 module's PLT. This allows modules to be allocated in the generic
1432 vmalloc area after the dedicated module memory area has been
1435 When running with address space randomization (KASLR), the module
1436 region itself may be too far away for ordinary relative jumps and
1437 calls, and so in that case, module PLTs are required and cannot be
1440 Specific errata workaround(s) might also force module PLTs to be
1441 enabled (ARM64_ERRATUM_843419).
1443 config ARM64_PSEUDO_NMI
1444 bool "Support for NMI-like interrupts"
1445 select CONFIG_ARM_GIC_V3
1447 Adds support for mimicking Non-Maskable Interrupts through the use of
1448 GIC interrupt priority. This support requires version 3 or later of
1451 This high priority configuration for interrupts needs to be
1452 explicitly enabled by setting the kernel parameter
1453 "irqchip.gicv3_pseudo_nmi" to 1.
1458 config ARM64_DEBUG_PRIORITY_MASKING
1459 bool "Debug interrupt priority masking"
1461 This adds runtime checks to functions enabling/disabling
1462 interrupts when using priority masking. The additional checks verify
1463 the validity of ICC_PMR_EL1 when calling concerned functions.
1471 This builds the kernel as a Position Independent Executable (PIE),
1472 which retains all relocation metadata required to relocate the
1473 kernel binary at runtime to a different virtual address than the
1474 address it was linked at.
1475 Since AArch64 uses the RELA relocation format, this requires a
1476 relocation pass at runtime even if the kernel is loaded at the
1477 same address it was linked at.
1479 config RANDOMIZE_BASE
1480 bool "Randomize the address of the kernel image"
1481 select ARM64_MODULE_PLTS if MODULES
1484 Randomizes the virtual address at which the kernel image is
1485 loaded, as a security feature that deters exploit attempts
1486 relying on knowledge of the location of kernel internals.
1488 It is the bootloader's job to provide entropy, by passing a
1489 random u64 value in /chosen/kaslr-seed at kernel entry.
1491 When booting via the UEFI stub, it will invoke the firmware's
1492 EFI_RNG_PROTOCOL implementation (if available) to supply entropy
1493 to the kernel proper. In addition, it will randomise the physical
1494 location of the kernel Image as well.
1498 config RANDOMIZE_MODULE_REGION_FULL
1499 bool "Randomize the module region over a 4 GB range"
1500 depends on RANDOMIZE_BASE
1503 Randomizes the location of the module region inside a 4 GB window
1504 covering the core kernel. This way, it is less likely for modules
1505 to leak information about the location of core kernel data structures
1506 but it does imply that function calls between modules and the core
1507 kernel will need to be resolved via veneers in the module PLT.
1509 When this option is not set, the module region will be randomized over
1510 a limited range that contains the [_stext, _etext] interval of the
1511 core kernel, so branch relocations are always in range.
1513 config CC_HAVE_STACKPROTECTOR_SYSREG
1514 def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0)
1516 config STACKPROTECTOR_PER_TASK
1518 depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG
1524 config ARM64_ACPI_PARKING_PROTOCOL
1525 bool "Enable support for the ARM64 ACPI parking protocol"
1528 Enable support for the ARM64 ACPI parking protocol. If disabled
1529 the kernel will not allow booting through the ARM64 ACPI parking
1530 protocol even if the corresponding data is present in the ACPI
1534 string "Default kernel command string"
1537 Provide a set of default command-line options at build time by
1538 entering them here. As a minimum, you should specify the the
1539 root device (e.g. root=/dev/nfs).
1541 config CMDLINE_FORCE
1542 bool "Always use the default kernel command string"
1544 Always use the default kernel command string, even if the boot
1545 loader passes other arguments to the kernel.
1546 This is useful if you cannot or don't want to change the
1547 command-line options your boot loader passes to the kernel.
1553 bool "UEFI runtime support"
1554 depends on OF && !CPU_BIG_ENDIAN
1555 depends on KERNEL_MODE_NEON
1556 select ARCH_SUPPORTS_ACPI
1559 select EFI_PARAMS_FROM_FDT
1560 select EFI_RUNTIME_WRAPPERS
1565 This option provides support for runtime services provided
1566 by UEFI firmware (such as non-volatile variables, realtime
1567 clock, and platform reset). A UEFI stub is also provided to
1568 allow the kernel to be booted as an EFI application. This
1569 is only useful on systems that have UEFI firmware.
1572 bool "Enable support for SMBIOS (DMI) tables"
1576 This enables SMBIOS/DMI feature for systems.
1578 This option is only useful on systems that have UEFI firmware.
1579 However, even with this option, the resultant kernel should
1580 continue to boot on existing non-UEFI platforms.
1584 config SYSVIPC_COMPAT
1586 depends on COMPAT && SYSVIPC
1588 config ARCH_ENABLE_HUGEPAGE_MIGRATION
1590 depends on HUGETLB_PAGE && MIGRATION
1592 menu "Power management options"
1594 source "kernel/power/Kconfig"
1596 config ARCH_HIBERNATION_POSSIBLE
1600 config ARCH_HIBERNATION_HEADER
1602 depends on HIBERNATION
1604 config ARCH_SUSPEND_POSSIBLE
1609 menu "CPU Power Management"
1611 source "drivers/cpuidle/Kconfig"
1613 source "drivers/cpufreq/Kconfig"
1617 source "drivers/firmware/Kconfig"
1619 source "drivers/acpi/Kconfig"
1621 source "arch/arm64/kvm/Kconfig"
1624 source "arch/arm64/crypto/Kconfig"