arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ or MIT)
   2 /*
   3  * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
   4  */
   5
   6 #include <dt-bindings/interrupt-controller/arm-gic.h>
   7 #include <dt-bindings/clock/sun50i-h6-ccu.h>
   8 #include <dt-bindings/clock/sun50i-h6-r-ccu.h>
   9 #include <dt-bindings/clock/sun8i-de2.h>
  10 #include <dt-bindings/clock/sun8i-tcon-top.h>
  11 #include <dt-bindings/reset/sun50i-h6-ccu.h>
  12 #include <dt-bindings/reset/sun50i-h6-r-ccu.h>
  13 #include <dt-bindings/reset/sun8i-de2.h>
  14
  15 / {
  16         interrupt-parent = <&gic>;
  17         #address-cells = <1>;
  18         #size-cells = <1>;
  19
  20         cpus {
  21                 #address-cells = <1>;
  22                 #size-cells = <0>;
  23
  24                 cpu0: cpu@0 {
  25                         compatible = "arm,cortex-a53";
  26                         device_type = "cpu";
  27                         reg = <0>;
  28                         enable-method = "psci";
  29                 };
  30
  31                 cpu1: cpu@1 {
  32                         compatible = "arm,cortex-a53";
  33                         device_type = "cpu";
  34                         reg = <1>;
  35                         enable-method = "psci";
  36                 };
  37
  38                 cpu2: cpu@2 {
  39                         compatible = "arm,cortex-a53";
  40                         device_type = "cpu";
  41                         reg = <2>;
  42                         enable-method = "psci";
  43                 };
  44
  45                 cpu3: cpu@3 {
  46                         compatible = "arm,cortex-a53";
  47                         device_type = "cpu";
  48                         reg = <3>;
  49                         enable-method = "psci";
  50                 };
  51         };
  52
  53         de: display-engine {
  54                 compatible = "allwinner,sun50i-h6-display-engine";
  55                 allwinner,pipelines = <&mixer0>;
  56                 status = "disabled";
  57         };
  58
  59         iosc: internal-osc-clk {
  60                 #clock-cells = <0>;
  61                 compatible = "fixed-clock";
  62                 clock-frequency = <16000000>;
  63                 clock-accuracy = <300000000>;
  64                 clock-output-names = "iosc";
  65         };
  66
  67         osc24M: osc24M_clk {
  68                 #clock-cells = <0>;
  69                 compatible = "fixed-clock";
  70                 clock-frequency = <24000000>;
  71                 clock-output-names = "osc24M";
  72         };
  73
  74         osc32k: osc32k_clk {
  75                 #clock-cells = <0>;
  76                 compatible = "fixed-clock";
  77                 clock-frequency = <32768>;
  78                 clock-output-names = "osc32k";
  79         };
  80
  81         psci {
  82                 compatible = "arm,psci-0.2";
  83                 method = "smc";
  84         };
  85
  86         timer {
  87                 compatible = "arm,armv8-timer";
  88                 interrupts = <GIC_PPI 13
  89                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
  90                              <GIC_PPI 14
  91                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
  92                              <GIC_PPI 11
  93                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
  94                              <GIC_PPI 10
  95                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  96         };
  97
  98         soc {
  99                 compatible = "simple-bus";
 100                 #address-cells = <1>;
 101                 #size-cells = <1>;
 102                 ranges;
 103
 104                 display-engine@1000000 {
 105                         compatible = "allwinner,sun50i-h6-de3",
 106                                      "allwinner,sun50i-a64-de2";
 107                         reg = <0x1000000 0x400000>;
 108                         allwinner,sram = <&de2_sram 1>;
 109                         #address-cells = <1>;
 110                         #size-cells = <1>;
 111                         ranges = <0 0x1000000 0x400000>;
 112
 113                         display_clocks: clock@0 {
 114                                 compatible = "allwinner,sun50i-h6-de3-clk";
 115                                 reg = <0x0 0x10000>;
 116                                 clocks = <&ccu CLK_DE>,
 117                                          <&ccu CLK_BUS_DE>;
 118                                 clock-names = "mod",
 119                                               "bus";
 120                                 resets = <&ccu RST_BUS_DE>;
 121                                 #clock-cells = <1>;
 122                                 #reset-cells = <1>;
 123                         };
 124
 125                         mixer0: mixer@100000 {
 126                                 compatible = "allwinner,sun50i-h6-de3-mixer-0";
 127                                 reg = <0x100000 0x100000>;
 128                                 clocks = <&display_clocks CLK_BUS_MIXER0>,
 129                                          <&display_clocks CLK_MIXER0>;
 130                                 clock-names = "bus",
 131                                               "mod";
 132                                 resets = <&display_clocks RST_MIXER0>;
 133
 134                                 ports {
 135                                         #address-cells = <1>;
 136                                         #size-cells = <0>;
 137
 138                                         mixer0_out: port@1 {
 139                                                 reg = <1>;
 140
 141                                                 mixer0_out_tcon_top_mixer0: endpoint {
 142                                                         remote-endpoint = <&tcon_top_mixer0_in_mixer0>;
 143                                                 };
 144                                         };
 145                                 };
 146                         };
 147                 };
 148
 149                 video-codec@1c0e000 {
 150                         compatible = "allwinner,sun50i-h6-video-engine";
 151                         reg = <0x01c0e000 0x2000>;
 152                         clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
 153                                  <&ccu CLK_MBUS_VE>;
 154                         clock-names = "ahb", "mod", "ram";
 155                         resets = <&ccu RST_BUS_VE>;
 156                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 157                         allwinner,sram = <&ve_sram 1>;
 158                 };
 159
 160                 syscon: syscon@3000000 {
 161                         compatible = "allwinner,sun50i-h6-system-control",
 162                                      "allwinner,sun50i-a64-system-control";
 163                         reg = <0x03000000 0x1000>;
 164                         #address-cells = <1>;
 165                         #size-cells = <1>;
 166                         ranges;
 167
 168                         sram_c: sram@28000 {
 169                                 compatible = "mmio-sram";
 170                                 reg = <0x00028000 0x1e000>;
 171                                 #address-cells = <1>;
 172                                 #size-cells = <1>;
 173                                 ranges = <0 0x00028000 0x1e000>;
 174
 175                                 de2_sram: sram-section@0 {
 176                                         compatible = "allwinner,sun50i-h6-sram-c",
 177                                                      "allwinner,sun50i-a64-sram-c";
 178                                         reg = <0x0000 0x1e000>;
 179                                 };
 180                         };
 181
 182                         sram_c1: sram@1a00000 {
 183                                 compatible = "mmio-sram";
 184                                 reg = <0x01a00000 0x200000>;
 185                                 #address-cells = <1>;
 186                                 #size-cells = <1>;
 187                                 ranges = <0 0x01a00000 0x200000>;
 188
 189                                 ve_sram: sram-section@0 {
 190                                         compatible = "allwinner,sun50i-h6-sram-c1",
 191                                                      "allwinner,sun4i-a10-sram-c1";
 192                                         reg = <0x000000 0x200000>;
 193                                 };
 194                         };
 195                 };
 196
 197                 ccu: clock@3001000 {
 198                         compatible = "allwinner,sun50i-h6-ccu";
 199                         reg = <0x03001000 0x1000>;
 200                         clocks = <&osc24M>, <&osc32k>, <&iosc>;
 201                         clock-names = "hosc", "losc", "iosc";
 202                         #clock-cells = <1>;
 203                         #reset-cells = <1>;
 204                 };
 205
 206                 sid: sid@3006000 {
 207                         compatible = "allwinner,sun50i-h6-sid";
 208                         reg = <0x03006000 0x400>;
 209                 };
 210
 211                 pio: pinctrl@300b000 {
 212                         compatible = "allwinner,sun50i-h6-pinctrl";
 213                         reg = <0x0300b000 0x400>;
 214                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
 215                                      <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
 216                                      <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
 217                                      <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 218                         clocks = <&ccu CLK_APB1>, <&osc24M>, <&osc32k>;
 219                         clock-names = "apb", "hosc", "losc";
 220                         gpio-controller;
 221                         #gpio-cells = <3>;
 222                         interrupt-controller;
 223                         #interrupt-cells = <3>;
 224
 225                         ext_rgmii_pins: rgmii-pins {
 226                                 pins = "PD0", "PD1", "PD2", "PD3", "PD4",
 227                                        "PD5", "PD7", "PD8", "PD9", "PD10",
 228                                        "PD11", "PD12", "PD13", "PD19", "PD20";
 229                                 function = "emac";
 230                                 drive-strength = <40>;
 231                         };
 232
 233                         hdmi_pins: hdmi-pins {
 234                                 pins = "PH8", "PH9", "PH10";
 235                                 function = "hdmi";
 236                         };
 237
 238                         mmc0_pins: mmc0-pins {
 239                                 pins = "PF0", "PF1", "PF2", "PF3",
 240                                        "PF4", "PF5";
 241                                 function = "mmc0";
 242                                 drive-strength = <30>;
 243                                 bias-pull-up;
 244                         };
 245
 246                         /omit-if-no-ref/
 247                         mmc1_pins: mmc1-pins {
 248                                 pins = "PG0", "PG1", "PG2", "PG3",
 249                                        "PG4", "PG5";
 250                                 function = "mmc1";
 251                                 drive-strength = <30>;
 252                                 bias-pull-up;
 253                         };
 254
 255                         mmc2_pins: mmc2-pins {
 256                                 pins = "PC1", "PC4", "PC5", "PC6",
 257                                        "PC7", "PC8", "PC9", "PC10",
 258                                        "PC11", "PC12", "PC13", "PC14";
 259                                 function = "mmc2";
 260                                 drive-strength = <30>;
 261                                 bias-pull-up;
 262                         };
 263
 264                         uart0_ph_pins: uart0-ph-pins {
 265                                 pins = "PH0", "PH1";
 266                                 function = "uart0";
 267                         };
 268                 };
 269
 270                 gic: interrupt-controller@3021000 {
 271                         compatible = "arm,gic-400";
 272                         reg = <0x03021000 0x1000>,
 273                               <0x03022000 0x2000>,
 274                               <0x03024000 0x2000>,
 275                               <0x03026000 0x2000>;
 276                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 277                         interrupt-controller;
 278                         #interrupt-cells = <3>;
 279                 };
 280
 281                 mmc0: mmc@4020000 {
 282                         compatible = "allwinner,sun50i-h6-mmc",
 283                                      "allwinner,sun50i-a64-mmc";
 284                         reg = <0x04020000 0x1000>;
 285                         clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
 286                         clock-names = "ahb", "mmc";
 287                         resets = <&ccu RST_BUS_MMC0>;
 288                         reset-names = "ahb";
 289                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 290                         pinctrl-names = "default";
 291                         pinctrl-0 = <&mmc0_pins>;
 292                         status = "disabled";
 293                         #address-cells = <1>;
 294                         #size-cells = <0>;
 295                 };
 296
 297                 mmc1: mmc@4021000 {
 298                         compatible = "allwinner,sun50i-h6-mmc",
 299                                      "allwinner,sun50i-a64-mmc";
 300                         reg = <0x04021000 0x1000>;
 301                         clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
 302                         clock-names = "ahb", "mmc";
 303                         resets = <&ccu RST_BUS_MMC1>;
 304                         reset-names = "ahb";
 305                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 306                         pinctrl-names = "default";
 307                         pinctrl-0 = <&mmc1_pins>;
 308                         status = "disabled";
 309                         #address-cells = <1>;
 310                         #size-cells = <0>;
 311                 };
 312
 313                 mmc2: mmc@4022000 {
 314                         compatible = "allwinner,sun50i-h6-emmc",
 315                                      "allwinner,sun50i-a64-emmc";
 316                         reg = <0x04022000 0x1000>;
 317                         clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
 318                         clock-names = "ahb", "mmc";
 319                         resets = <&ccu RST_BUS_MMC2>;
 320                         reset-names = "ahb";
 321                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 322                         pinctrl-names = "default";
 323                         pinctrl-0 = <&mmc2_pins>;
 324                         status = "disabled";
 325                         #address-cells = <1>;
 326                         #size-cells = <0>;
 327                 };
 328
 329                 uart0: serial@5000000 {
 330                         compatible = "snps,dw-apb-uart";
 331                         reg = <0x05000000 0x400>;
 332                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
 333                         reg-shift = <2>;
 334                         reg-io-width = <4>;
 335                         clocks = <&ccu CLK_BUS_UART0>;
 336                         resets = <&ccu RST_BUS_UART0>;
 337                         status = "disabled";
 338                 };
 339
 340                 uart1: serial@5000400 {
 341                         compatible = "snps,dw-apb-uart";
 342                         reg = <0x05000400 0x400>;
 343                         interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 344                         reg-shift = <2>;
 345                         reg-io-width = <4>;
 346                         clocks = <&ccu CLK_BUS_UART1>;
 347                         resets = <&ccu RST_BUS_UART1>;
 348                         status = "disabled";
 349                 };
 350
 351                 uart2: serial@5000800 {
 352                         compatible = "snps,dw-apb-uart";
 353                         reg = <0x05000800 0x400>;
 354                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 355                         reg-shift = <2>;
 356                         reg-io-width = <4>;
 357                         clocks = <&ccu CLK_BUS_UART2>;
 358                         resets = <&ccu RST_BUS_UART2>;
 359                         status = "disabled";
 360                 };
 361
 362                 uart3: serial@5000c00 {
 363                         compatible = "snps,dw-apb-uart";
 364                         reg = <0x05000c00 0x400>;
 365                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 366                         reg-shift = <2>;
 367                         reg-io-width = <4>;
 368                         clocks = <&ccu CLK_BUS_UART3>;
 369                         resets = <&ccu RST_BUS_UART3>;
 370                         status = "disabled";
 371                 };
 372
 373                 emac: ethernet@5020000 {
 374                         compatible = "allwinner,sun50i-h6-emac",
 375                                      "allwinner,sun50i-a64-emac";
 376                         syscon = <&syscon>;
 377                         reg = <0x05020000 0x10000>;
 378                         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 379                         interrupt-names = "macirq";
 380                         resets = <&ccu RST_BUS_EMAC>;
 381                         reset-names = "stmmaceth";
 382                         clocks = <&ccu CLK_BUS_EMAC>;
 383                         clock-names = "stmmaceth";
 384                         status = "disabled";
 385
 386                         mdio: mdio {
 387                                 compatible = "snps,dwmac-mdio";
 388                                 #address-cells = <1>;
 389                                 #size-cells = <0>;
 390                         };
 391                 };
 392
 393                 usb2otg: usb@5100000 {
 394                         compatible = "allwinner,sun50i-h6-musb",
 395                                      "allwinner,sun8i-a33-musb";
 396                         reg = <0x05100000 0x0400>;
 397                         clocks = <&ccu CLK_BUS_OTG>;
 398                         resets = <&ccu RST_BUS_OTG>;
 399                         interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 400                         interrupt-names = "mc";
 401                         phys = <&usb2phy 0>;
 402                         phy-names = "usb";
 403                         extcon = <&usb2phy 0>;
 404                         status = "disabled";
 405                 };
 406
 407                 usb2phy: phy@5100400 {
 408                         compatible = "allwinner,sun50i-h6-usb-phy";
 409                         reg = <0x05100400 0x24>,
 410                               <0x05101800 0x4>,
 411                               <0x05311800 0x4>;
 412                         reg-names = "phy_ctrl",
 413                                     "pmu0",
 414                                     "pmu3";
 415                         clocks = <&ccu CLK_USB_PHY0>,
 416                                  <&ccu CLK_USB_PHY3>;
 417                         clock-names = "usb0_phy",
 418                                       "usb3_phy";
 419                         resets = <&ccu RST_USB_PHY0>,
 420                                  <&ccu RST_USB_PHY3>;
 421                         reset-names = "usb0_reset",
 422                                       "usb3_reset";
 423                         status = "disabled";
 424                         #phy-cells = <1>;
 425                 };
 426
 427                 ehci0: usb@5101000 {
 428                         compatible = "allwinner,sun50i-h6-ehci", "generic-ehci";
 429                         reg = <0x05101000 0x100>;
 430                         interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 431                         clocks = <&ccu CLK_BUS_OHCI0>,
 432                                  <&ccu CLK_BUS_EHCI0>,
 433                                  <&ccu CLK_USB_OHCI0>;
 434                         resets = <&ccu RST_BUS_OHCI0>,
 435                                  <&ccu RST_BUS_EHCI0>;
 436                         status = "disabled";
 437                 };
 438
 439                 ohci0: usb@5101400 {
 440                         compatible = "allwinner,sun50i-h6-ohci", "generic-ohci";
 441                         reg = <0x05101400 0x100>;
 442                         interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 443                         clocks = <&ccu CLK_BUS_OHCI0>,
 444                                  <&ccu CLK_USB_OHCI0>;
 445                         resets = <&ccu RST_BUS_OHCI0>;
 446                         status = "disabled";
 447                 };
 448
 449                 ehci3: usb@5311000 {
 450                         compatible = "allwinner,sun50i-h6-ehci", "generic-ehci";
 451                         reg = <0x05311000 0x100>;
 452                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 453                         clocks = <&ccu CLK_BUS_OHCI3>,
 454                                  <&ccu CLK_BUS_EHCI3>,
 455                                  <&ccu CLK_USB_OHCI3>;
 456                         resets = <&ccu RST_BUS_OHCI3>,
 457                                  <&ccu RST_BUS_EHCI3>;
 458                         phys = <&usb2phy 3>;
 459                         phy-names = "usb";
 460                         status = "disabled";
 461                 };
 462
 463                 ohci3: usb@5311400 {
 464                         compatible = "allwinner,sun50i-h6-ohci", "generic-ohci";
 465                         reg = <0x05311400 0x100>;
 466                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 467                         clocks = <&ccu CLK_BUS_OHCI3>,
 468                                  <&ccu CLK_USB_OHCI3>;
 469                         resets = <&ccu RST_BUS_OHCI3>;
 470                         phys = <&usb2phy 3>;
 471                         phy-names = "usb";
 472                         status = "disabled";
 473                 };
 474
 475                 hdmi: hdmi@6000000 {
 476                         compatible = "allwinner,sun50i-h6-dw-hdmi";
 477                         reg = <0x06000000 0x10000>;
 478                         reg-io-width = <1>;
 479                         interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 480                         clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>,
 481                                  <&ccu CLK_HDMI>, <&ccu CLK_HDMI_CEC>,
 482                                  <&ccu CLK_HDCP>, <&ccu CLK_BUS_HDCP>;
 483                         clock-names = "iahb", "isfr", "tmds", "cec", "hdcp",
 484                                       "hdcp-bus";
 485                         resets = <&ccu RST_BUS_HDMI_SUB>, <&ccu RST_BUS_HDCP>;
 486                         reset-names = "ctrl", "hdcp";
 487                         phys = <&hdmi_phy>;
 488                         phy-names = "hdmi-phy";
 489                         pinctrl-names = "default";
 490                         pinctrl-0 = <&hdmi_pins>;
 491                         status = "disabled";
 492
 493                         ports {
 494                                 #address-cells = <1>;
 495                                 #size-cells = <0>;
 496
 497                                 hdmi_in: port@0 {
 498                                         reg = <0>;
 499
 500                                         hdmi_in_tcon_top: endpoint {
 501                                                 remote-endpoint = <&tcon_top_hdmi_out_hdmi>;
 502                                         };
 503                                 };
 504
 505                                 hdmi_out: port@1 {
 506                                         reg = <1>;
 507                                 };
 508                         };
 509                 };
 510
 511                 hdmi_phy: hdmi-phy@6010000 {
 512                         compatible = "allwinner,sun50i-h6-hdmi-phy";
 513                         reg = <0x06010000 0x10000>;
 514                         clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>;
 515                         clock-names = "bus", "mod";
 516                         resets = <&ccu RST_BUS_HDMI>;
 517                         reset-names = "phy";
 518                         #phy-cells = <0>;
 519                 };
 520
 521                 tcon_top: tcon-top@6510000 {
 522                         compatible = "allwinner,sun50i-h6-tcon-top";
 523                         reg = <0x06510000 0x1000>;
 524                         clocks = <&ccu CLK_BUS_TCON_TOP>,
 525                                  <&ccu CLK_TCON_TV0>;
 526                         clock-names = "bus",
 527                                       "tcon-tv0";
 528                         clock-output-names = "tcon-top-tv0";
 529                         resets = <&ccu RST_BUS_TCON_TOP>;
 530                         reset-names = "rst";
 531                         #clock-cells = <1>;
 532
 533                         ports {
 534                                 #address-cells = <1>;
 535                                 #size-cells = <0>;
 536
 537                                 tcon_top_mixer0_in: port@0 {
 538                                         #address-cells = <1>;
 539                                         #size-cells = <0>;
 540                                         reg = <0>;
 541
 542                                         tcon_top_mixer0_in_mixer0: endpoint@0 {
 543                                                 reg = <0>;
 544                                                 remote-endpoint = <&mixer0_out_tcon_top_mixer0>;
 545                                         };
 546                                 };
 547
 548                                 tcon_top_mixer0_out: port@1 {
 549                                         #address-cells = <1>;
 550                                         #size-cells = <0>;
 551                                         reg = <1>;
 552
 553                                         tcon_top_mixer0_out_tcon_tv: endpoint@2 {
 554                                                 reg = <2>;
 555                                                 remote-endpoint = <&tcon_tv_in_tcon_top_mixer0>;
 556                                         };
 557                                 };
 558
 559                                 tcon_top_hdmi_in: port@4 {
 560                                         #address-cells = <1>;
 561                                         #size-cells = <0>;
 562                                         reg = <4>;
 563
 564                                         tcon_top_hdmi_in_tcon_tv: endpoint@0 {
 565                                                 reg = <0>;
 566                                                 remote-endpoint = <&tcon_tv_out_tcon_top>;
 567                                         };
 568                                 };
 569
 570                                 tcon_top_hdmi_out: port@5 {
 571                                         reg = <5>;
 572
 573                                         tcon_top_hdmi_out_hdmi: endpoint {
 574                                                 remote-endpoint = <&hdmi_in_tcon_top>;
 575                                         };
 576                                 };
 577                         };
 578                 };
 579
 580                 tcon_tv: lcd-controller@6515000 {
 581                         compatible = "allwinner,sun50i-h6-tcon-tv",
 582                                      "allwinner,sun8i-r40-tcon-tv";
 583                         reg = <0x06515000 0x1000>;
 584                         interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 585                         clocks = <&ccu CLK_BUS_TCON_TV0>,
 586                                  <&tcon_top CLK_TCON_TOP_TV0>;
 587                         clock-names = "ahb",
 588                                       "tcon-ch1";
 589                         resets = <&ccu RST_BUS_TCON_TV0>;
 590                         reset-names = "lcd";
 591
 592                         ports {
 593                                 #address-cells = <1>;
 594                                 #size-cells = <0>;
 595
 596                                 tcon_tv_in: port@0 {
 597                                         reg = <0>;
 598
 599                                         tcon_tv_in_tcon_top_mixer0: endpoint {
 600                                                 remote-endpoint = <&tcon_top_mixer0_out_tcon_tv>;
 601                                         };
 602                                 };
 603
 604                                 tcon_tv_out: port@1 {
 605                                         #address-cells = <1>;
 606                                         #size-cells = <0>;
 607                                         reg = <1>;
 608
 609                                         tcon_tv_out_tcon_top: endpoint@1 {
 610                                                 reg = <1>;
 611                                                 remote-endpoint = <&tcon_top_hdmi_in_tcon_tv>;
 612                                         };
 613                                 };
 614                         };
 615                 };
 616
 617                 r_ccu: clock@7010000 {
 618                         compatible = "allwinner,sun50i-h6-r-ccu";
 619                         reg = <0x07010000 0x400>;
 620                         clocks = <&osc24M>, <&osc32k>, <&iosc>,
 621                                  <&ccu CLK_PLL_PERIPH0>;
 622                         clock-names = "hosc", "losc", "iosc", "pll-periph";
 623                         #clock-cells = <1>;
 624                         #reset-cells = <1>;
 625                 };
 626
 627                 r_intc: interrupt-controller@7021000 {
 628                         compatible = "allwinner,sun50i-h6-r-intc",
 629                                      "allwinner,sun6i-a31-r-intc";
 630                         interrupt-controller;
 631                         #interrupt-cells = <2>;
 632                         reg = <0x07021000 0x400>;
 633                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 634                 };
 635
 636                 r_pio: pinctrl@7022000 {
 637                         compatible = "allwinner,sun50i-h6-r-pinctrl";
 638                         reg = <0x07022000 0x400>;
 639                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
 640                                      <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 641                         clocks = <&r_ccu CLK_R_APB1>, <&osc24M>, <&osc32k>;
 642                         clock-names = "apb", "hosc", "losc";
 643                         gpio-controller;
 644                         #gpio-cells = <3>;
 645                         interrupt-controller;
 646                         #interrupt-cells = <3>;
 647
 648                         r_i2c_pins: r-i2c-pins {
 649                                 pins = "PL0", "PL1";
 650                                 function = "s_i2c";
 651                         };
 652                 };
 653
 654                 r_i2c: i2c@7081400 {
 655                         compatible = "allwinner,sun6i-a31-i2c";
 656                         reg = <0x07081400 0x400>;
 657                         interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 658                         clocks = <&r_ccu CLK_R_APB2_I2C>;
 659                         resets = <&r_ccu RST_R_APB2_I2C>;
 660                         pinctrl-names = "default";
 661                         pinctrl-0 = <&r_i2c_pins>;
 662                         status = "disabled";
 663                         #address-cells = <1>;
 664                         #size-cells = <0>;
 665                 };
 666         };
 667 };