arch/arm64/boot/dts/amlogic/meson-axg.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (c) 2017 Amlogic, Inc. All rights reserved.
   4  */
   5
   6 #include <dt-bindings/gpio/gpio.h>
   7 #include <dt-bindings/interrupt-controller/irq.h>
   8 #include <dt-bindings/interrupt-controller/arm-gic.h>
   9 #include <dt-bindings/clock/axg-clkc.h>
  10 #include <dt-bindings/gpio/meson-axg-gpio.h>
  11 #include <dt-bindings/reset/amlogic,meson-axg-reset.h>
  12
  13 / {
  14         compatible = "amlogic,meson-axg";
  15
  16         interrupt-parent = <&gic>;
  17         #address-cells = <2>;
  18         #size-cells = <2>;
  19
  20         reserved-memory {
  21                 #address-cells = <2>;
  22                 #size-cells = <2>;
  23                 ranges;
  24
  25                 /* 16 MiB reserved for Hardware ROM Firmware */
  26                 hwrom_reserved: hwrom@0 {
  27                         reg = <0x0 0x0 0x0 0x1000000>;
  28                         no-map;
  29                 };
  30
  31                 /* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */
  32                 secmon_reserved: secmon@5000000 {
  33                         reg = <0x0 0x05000000 0x0 0x300000>;
  34                         no-map;
  35                 };
  36         };
  37
  38         cpus {
  39                 #address-cells = <0x2>;
  40                 #size-cells = <0x0>;
  41
  42                 cpu0: cpu@0 {
  43                         device_type = "cpu";
  44                         compatible = "arm,cortex-a53", "arm,armv8";
  45                         reg = <0x0 0x0>;
  46                         enable-method = "psci";
  47                         next-level-cache = <&l2>;
  48                 };
  49
  50                 cpu1: cpu@1 {
  51                         device_type = "cpu";
  52                         compatible = "arm,cortex-a53", "arm,armv8";
  53                         reg = <0x0 0x1>;
  54                         enable-method = "psci";
  55                         next-level-cache = <&l2>;
  56                 };
  57
  58                 cpu2: cpu@2 {
  59                         device_type = "cpu";
  60                         compatible = "arm,cortex-a53", "arm,armv8";
  61                         reg = <0x0 0x2>;
  62                         enable-method = "psci";
  63                         next-level-cache = <&l2>;
  64                 };
  65
  66                 cpu3: cpu@3 {
  67                         device_type = "cpu";
  68                         compatible = "arm,cortex-a53", "arm,armv8";
  69                         reg = <0x0 0x3>;
  70                         enable-method = "psci";
  71                         next-level-cache = <&l2>;
  72                 };
  73
  74                 l2: l2-cache0 {
  75                         compatible = "cache";
  76                 };
  77         };
  78
  79         arm-pmu {
  80                 compatible = "arm,cortex-a53-pmu";
  81                 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
  82                              <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
  83                              <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
  84                              <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
  85                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
  86         };
  87
  88         psci {
  89                 compatible = "arm,psci-1.0";
  90                 method = "smc";
  91         };
  92
  93         timer {
  94                 compatible = "arm,armv8-timer";
  95                 interrupts = <GIC_PPI 13
  96                         (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
  97                              <GIC_PPI 14
  98                         (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
  99                              <GIC_PPI 11
 100                         (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
 101                              <GIC_PPI 10
 102                         (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
 103         };
 104
 105         xtal: xtal-clk {
 106                 compatible = "fixed-clock";
 107                 clock-frequency = <24000000>;
 108                 clock-output-names = "xtal";
 109                 #clock-cells = <0>;
 110         };
 111
 112         ao_alt_xtal: ao_alt_xtal-clk {
 113                 compatible = "fixed-clock";
 114                 clock-frequency = <32000000>;
 115                 clock-output-names = "ao_alt_xtal";
 116                 #clock-cells = <0>;
 117         };
 118
 119         soc {
 120                 compatible = "simple-bus";
 121                 #address-cells = <2>;
 122                 #size-cells = <2>;
 123                 ranges;
 124
 125                 apb: apb@ffe00000 {
 126                         compatible = "simple-bus";
 127                         reg = <0x0 0xffe00000 0x0 0x200000>;
 128                         #address-cells = <2>;
 129                         #size-cells = <2>;
 130                         ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x200000>;
 131
 132                         sd_emmc_b: sd@5000 {
 133                                 compatible = "amlogic,meson-axg-mmc";
 134                                 reg = <0x0 0x5000 0x0 0x2000>;
 135                                 interrupts = <GIC_SPI 217 IRQ_TYPE_EDGE_RISING>;
 136                                 status = "disabled";
 137                                 clocks = <&clkc CLKID_SD_EMMC_B>,
 138                                         <&clkc CLKID_SD_EMMC_B_CLK0>,
 139                                         <&clkc CLKID_FCLK_DIV2>;
 140                                 clock-names = "core", "clkin0", "clkin1";
 141                                 resets = <&reset RESET_SD_EMMC_B>;
 142                         };
 143
 144                         sd_emmc_c: mmc@7000 {
 145                                 compatible = "amlogic,meson-axg-mmc";
 146                                 reg = <0x0 0x7000 0x0 0x2000>;
 147                                 interrupts = <GIC_SPI 218 IRQ_TYPE_EDGE_RISING>;
 148                                 status = "disabled";
 149                                 clocks = <&clkc CLKID_SD_EMMC_C>,
 150                                         <&clkc CLKID_SD_EMMC_C_CLK0>,
 151                                         <&clkc CLKID_FCLK_DIV2>;
 152                                 clock-names = "core", "clkin0", "clkin1";
 153                                 resets = <&reset RESET_SD_EMMC_C>;
 154                         };
 155                 };
 156
 157                 cbus: bus@ffd00000 {
 158                         compatible = "simple-bus";
 159                         reg = <0x0 0xffd00000 0x0 0x25000>;
 160                         #address-cells = <2>;
 161                         #size-cells = <2>;
 162                         ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x25000>;
 163
 164                         gpio_intc: interrupt-controller@f080 {
 165                                 compatible = "amlogic,meson-gpio-intc";
 166                                 reg = <0x0 0xf080 0x0 0x10>;
 167                                 interrupt-controller;
 168                                 #interrupt-cells = <2>;
 169                                 amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>;
 170                                 status = "disabled";
 171                         };
 172
 173                         pwm_ab: pwm@1b000 {
 174                                 compatible = "amlogic,meson-axg-ee-pwm";
 175                                 reg = <0x0 0x1b000 0x0 0x20>;
 176                                 #pwm-cells = <3>;
 177                                 status = "disabled";
 178                         };
 179
 180                         pwm_cd: pwm@1a000 {
 181                                 compatible = "amlogic,meson-axg-ee-pwm";
 182                                 reg = <0x0 0x1a000 0x0 0x20>;
 183                                 #pwm-cells = <3>;
 184                                 status = "disabled";
 185                         };
 186
 187                         reset: reset-controller@1004 {
 188                                 compatible = "amlogic,meson-axg-reset";
 189                                 reg = <0x0 0x01004 0x0 0x9c>;
 190                                 #reset-cells = <1>;
 191                         };
 192
 193                         spicc0: spi@13000 {
 194                                 compatible = "amlogic,meson-axg-spicc";
 195                                 reg = <0x0 0x13000 0x0 0x3c>;
 196                                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 197                                 clocks = <&clkc CLKID_SPICC0>;
 198                                 clock-names = "core";
 199                                 #address-cells = <1>;
 200                                 #size-cells = <0>;
 201                                 status = "disabled";
 202                         };
 203
 204                         spicc1: spi@15000 {
 205                                 compatible = "amlogic,meson-axg-spicc";
 206                                 reg = <0x0 0x15000 0x0 0x3c>;
 207                                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 208                                 clocks = <&clkc CLKID_SPICC1>;
 209                                 clock-names = "core";
 210                                 #address-cells = <1>;
 211                                 #size-cells = <0>;
 212                                 status = "disabled";
 213                         };
 214
 215                         i2c0: i2c@1f000 {
 216                                 compatible = "amlogic,meson-axg-i2c";
 217                                 status = "disabled";
 218                                 reg = <0x0 0x1f000 0x0 0x20>;
 219                                 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
 220                                         <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>;
 221                                 #address-cells = <1>;
 222                                 #size-cells = <0>;
 223                                 clocks = <&clkc CLKID_I2C>;
 224                                 clock-names = "clk_i2c";
 225                         };
 226
 227                         i2c1: i2c@1e000 {
 228                                 compatible = "amlogic,meson-axg-i2c";
 229                                 #address-cells = <1>;
 230                                 #size-cells = <0>;
 231                                 reg = <0x0 0x1e000 0x0 0x20>;
 232                                 status = "disabled";
 233                                 interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>,
 234                                         <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>;
 235                                 clocks = <&clkc CLKID_I2C>;
 236                                 clock-names = "clk_i2c";
 237                         };
 238
 239                         i2c2: i2c@1d000 {
 240                                 compatible = "amlogic,meson-axg-i2c";
 241                                 status = "disabled";
 242                                 reg = <0x0 0x1d000 0x0 0x20>;
 243                                 interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>,
 244                                         <GIC_SPI 49 IRQ_TYPE_EDGE_RISING>;
 245                                 #address-cells = <1>;
 246                                 #size-cells = <0>;
 247                                 clocks = <&clkc CLKID_I2C>;
 248                                 clock-names = "clk_i2c";
 249                         };
 250
 251                         i2c3: i2c@1c000 {
 252                                 compatible = "amlogic,meson-axg-i2c";
 253                                 status = "disabled";
 254                                 reg = <0x0 0x1c000 0x0 0x20>;
 255                                 interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>,
 256                                         <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>;
 257                                 #address-cells = <1>;
 258                                 #size-cells = <0>;
 259                                 clocks = <&clkc CLKID_I2C>;
 260                                 clock-names = "clk_i2c";
 261                         };
 262
 263                         uart_A: serial@24000 {
 264                                 compatible = "amlogic,meson-gx-uart";
 265                                 reg = <0x0 0x24000 0x0 0x18>;
 266                                 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
 267                                 status = "disabled";
 268                                 clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
 269                                 clock-names = "xtal", "pclk", "baud";
 270                         };
 271
 272                         uart_B: serial@23000 {
 273                                 compatible = "amlogic,meson-gx-uart";
 274                                 reg = <0x0 0x23000 0x0 0x18>;
 275                                 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
 276                                 status = "disabled";
 277                                 clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
 278                                 clock-names = "xtal", "pclk", "baud";
 279                         };
 280                 };
 281
 282                 ethmac: ethernet@ff3f0000 {
 283                         compatible = "amlogic,meson-gxbb-dwmac", "snps,dwmac";
 284                         reg = <0x0 0xff3f0000 0x0 0x10000
 285                                 0x0 0xff634540 0x0 0x8>;
 286                         interrupts = <GIC_SPI 8 IRQ_TYPE_EDGE_RISING>;
 287                         interrupt-names = "macirq";
 288                         clocks = <&clkc CLKID_ETH>,
 289                                  <&clkc CLKID_FCLK_DIV2>,
 290                                  <&clkc CLKID_MPLL2>;
 291                         clock-names = "stmmaceth", "clkin0", "clkin1";
 292                         status = "disabled";
 293                 };
 294
 295                 gic: interrupt-controller@ffc01000 {
 296                         compatible = "arm,gic-400";
 297                         reg = <0x0 0xffc01000 0 0x1000>,
 298                               <0x0 0xffc02000 0 0x2000>,
 299                               <0x0 0xffc04000 0 0x2000>,
 300                               <0x0 0xffc06000 0 0x2000>;
 301                         interrupt-controller;
 302                         interrupts = <GIC_PPI 9
 303                                 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
 304                         #interrupt-cells = <3>;
 305                         #address-cells = <0>;
 306                 };
 307
 308                 hiubus: bus@ff63c000 {
 309                         compatible = "simple-bus";
 310                         reg = <0x0 0xff63c000 0x0 0x1c00>;
 311                         #address-cells = <2>;
 312                         #size-cells = <2>;
 313                         ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x1c00>;
 314
 315                         sysctrl: system-controller@0 {
 316                                 compatible = "amlogic,meson-axg-hhi-sysctrl", "syscon", "simple-mfd";
 317                                 reg = <0 0 0 0x400>;
 318
 319                                 clkc: clock-controller {
 320                                         compatible = "amlogic,axg-clkc";
 321                                         #clock-cells = <1>;
 322                                 };
 323                         };
 324                 };
 325
 326                 mailbox: mailbox@ff63dc00 {
 327                         compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu";
 328                         reg = <0 0xff63dc00 0 0x400>;
 329                         interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
 330                                      <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>,
 331                                      <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>;
 332                         #mbox-cells = <1>;
 333                 };
 334
 335                 periphs: periphs@ff634000 {
 336                         compatible = "simple-bus";
 337                         reg = <0x0 0xff634000 0x0 0x2000>;
 338                         #address-cells = <2>;
 339                         #size-cells = <2>;
 340                         ranges = <0x0 0x0 0x0 0xff634000 0x0 0x2000>;
 341
 342                         hwrng: rng {
 343                                 compatible = "amlogic,meson-rng";
 344                                 reg = <0x0 0x18 0x0 0x4>;
 345                                 clocks = <&clkc CLKID_RNG0>;
 346                                 clock-names = "core";
 347                         };
 348
 349                         pinctrl_periphs: pinctrl@480 {
 350                                 compatible = "amlogic,meson-axg-periphs-pinctrl";
 351                                 #address-cells = <2>;
 352                                 #size-cells = <2>;
 353                                 ranges;
 354
 355                                 gpio: bank@480 {
 356                                         reg = <0x0 0x00480 0x0 0x40>,
 357                                                 <0x0 0x004e8 0x0 0x14>,
 358                                                 <0x0 0x00520 0x0 0x14>,
 359                                                 <0x0 0x00430 0x0 0x3c>;
 360                                         reg-names = "mux", "pull", "pull-enable", "gpio";
 361                                         gpio-controller;
 362                                         #gpio-cells = <2>;
 363                                         gpio-ranges = <&pinctrl_periphs 0 0 86>;
 364                                 };
 365
 366                                 emmc_pins: emmc {
 367                                         mux {
 368                                                 groups = "emmc_nand_d0",
 369                                                         "emmc_nand_d1",
 370                                                         "emmc_nand_d2",
 371                                                         "emmc_nand_d3",
 372                                                         "emmc_nand_d4",
 373                                                         "emmc_nand_d5",
 374                                                         "emmc_nand_d6",
 375                                                         "emmc_nand_d7",
 376                                                         "emmc_clk",
 377                                                         "emmc_cmd",
 378                                                         "emmc_ds";
 379                                                 function = "emmc";
 380                                         };
 381                                 };
 382
 383                                 emmc_clk_gate_pins: emmc_clk_gate {
 384                                         mux {
 385                                                 groups = "BOOT_8";
 386                                                 function = "gpio_periphs";
 387                                         };
 388                                         cfg-pull-down {
 389                                                 pins = "BOOT_8";
 390                                                 bias-pull-down;
 391                                         };
 392                                 };
 393
 394                                 sdio_pins: sdio {
 395                                         mux {
 396                                                 groups = "sdio_d0",
 397                                                         "sdio_d1",
 398                                                         "sdio_d2",
 399                                                         "sdio_d3",
 400                                                         "sdio_cmd",
 401                                                         "sdio_clk";
 402                                                 function = "sdio";
 403                                         };
 404                                 };
 405
 406                                 sdio_clk_gate_pins: sdio_clk_gate {
 407                                         mux {
 408                                                 groups = "GPIOX_4";
 409                                                 function = "gpio_periphs";
 410                                         };
 411                                         cfg-pull-down {
 412                                                 pins = "GPIOX_4";
 413                                                 bias-pull-down;
 414                                         };
 415                                 };
 416
 417                                 eth_rmii_x_pins: eth-x-rmii {
 418                                         mux {
 419                                                 groups = "eth_mdio_x",
 420                                                        "eth_mdc_x",
 421                                                        "eth_rgmii_rx_clk_x",
 422                                                        "eth_rx_dv_x",
 423                                                        "eth_rxd0_x",
 424                                                        "eth_rxd1_x",
 425                                                        "eth_txen_x",
 426                                                        "eth_txd0_x",
 427                                                        "eth_txd1_x";
 428                                                 function = "eth";
 429                                         };
 430                                 };
 431
 432                                 eth_rmii_y_pins: eth-y-rmii {
 433                                         mux {
 434                                                 groups = "eth_mdio_y",
 435                                                        "eth_mdc_y",
 436                                                        "eth_rgmii_rx_clk_y",
 437                                                        "eth_rx_dv_y",
 438                                                        "eth_rxd0_y",
 439                                                        "eth_rxd1_y",
 440                                                        "eth_txen_y",
 441                                                        "eth_txd0_y",
 442                                                        "eth_txd1_y";
 443                                                 function = "eth";
 444                                         };
 445                                 };
 446
 447                                 eth_rgmii_x_pins: eth-x-rgmii {
 448                                         mux {
 449                                                 groups = "eth_mdio_x",
 450                                                        "eth_mdc_x",
 451                                                        "eth_rgmii_rx_clk_x",
 452                                                        "eth_rx_dv_x",
 453                                                        "eth_rxd0_x",
 454                                                        "eth_rxd1_x",
 455                                                        "eth_rxd2_rgmii",
 456                                                        "eth_rxd3_rgmii",
 457                                                        "eth_rgmii_tx_clk",
 458                                                        "eth_txen_x",
 459                                                        "eth_txd0_x",
 460                                                        "eth_txd1_x",
 461                                                        "eth_txd2_rgmii",
 462                                                        "eth_txd3_rgmii";
 463                                                 function = "eth";
 464                                         };
 465                                 };
 466
 467                                 eth_rgmii_y_pins: eth-y-rgmii {
 468                                         mux {
 469                                                 groups = "eth_mdio_y",
 470                                                        "eth_mdc_y",
 471                                                        "eth_rgmii_rx_clk_y",
 472                                                        "eth_rx_dv_y",
 473                                                        "eth_rxd0_y",
 474                                                        "eth_rxd1_y",
 475                                                        "eth_rxd2_rgmii",
 476                                                        "eth_rxd3_rgmii",
 477                                                        "eth_rgmii_tx_clk",
 478                                                        "eth_txen_y",
 479                                                        "eth_txd0_y",
 480                                                        "eth_txd1_y",
 481                                                        "eth_txd2_rgmii",
 482                                                        "eth_txd3_rgmii";
 483                                                 function = "eth";
 484                                         };
 485                                 };
 486
 487                                 pwm_a_a_pins: pwm_a_a {
 488                                         mux {
 489                                                 groups = "pwm_a_a";
 490                                                 function = "pwm_a";
 491                                         };
 492                                 };
 493
 494                                 pwm_a_x18_pins: pwm_a_x18 {
 495                                         mux {
 496                                                 groups = "pwm_a_x18";
 497                                                 function = "pwm_a";
 498                                         };
 499                                 };
 500
 501                                 pwm_a_x20_pins: pwm_a_x20 {
 502                                         mux {
 503                                                 groups = "pwm_a_x20";
 504                                                 function = "pwm_a";
 505                                         };
 506                                 };
 507
 508                                 pwm_a_z_pins: pwm_a_z {
 509                                         mux {
 510                                                 groups = "pwm_a_z";
 511                                                 function = "pwm_a";
 512                                         };
 513                                 };
 514
 515                                 pwm_b_a_pins: pwm_b_a {
 516                                         mux {
 517                                                 groups = "pwm_b_a";
 518                                                 function = "pwm_b";
 519                                         };
 520                                 };
 521
 522                                 pwm_b_x_pins: pwm_b_x {
 523                                         mux {
 524                                                 groups = "pwm_b_x";
 525                                                 function = "pwm_b";
 526                                         };
 527                                 };
 528
 529                                 pwm_b_z_pins: pwm_b_z {
 530                                         mux {
 531                                                 groups = "pwm_b_z";
 532                                                 function = "pwm_b";
 533                                         };
 534                                 };
 535
 536                                 pwm_c_a_pins: pwm_c_a {
 537                                         mux {
 538                                                 groups = "pwm_c_a";
 539                                                 function = "pwm_c";
 540                                         };
 541                                 };
 542
 543                                 pwm_c_x10_pins: pwm_c_x10 {
 544                                         mux {
 545                                                 groups = "pwm_c_x10";
 546                                                 function = "pwm_c";
 547                                         };
 548                                 };
 549
 550                                 pwm_c_x17_pins: pwm_c_x17 {
 551                                         mux {
 552                                                 groups = "pwm_c_x17";
 553                                                 function = "pwm_c";
 554                                         };
 555                                 };
 556
 557                                 pwm_d_x11_pins: pwm_d_x11 {
 558                                         mux {
 559                                                 groups = "pwm_d_x11";
 560                                                 function = "pwm_d";
 561                                         };
 562                                 };
 563
 564                                 pwm_d_x16_pins: pwm_d_x16 {
 565                                         mux {
 566                                                 groups = "pwm_d_x16";
 567                                                 function = "pwm_d";
 568                                         };
 569                                 };
 570
 571                                 spi0_pins: spi0 {
 572                                         mux {
 573                                                 groups = "spi0_miso",
 574                                                         "spi0_mosi",
 575                                                         "spi0_clk";
 576                                                 function = "spi0";
 577                                         };
 578                                 };
 579
 580                                 spi0_ss0_pins: spi0_ss0 {
 581                                         mux {
 582                                                 groups = "spi0_ss0";
 583                                                 function = "spi0";
 584                                         };
 585                                 };
 586
 587                                 spi0_ss1_pins: spi0_ss1 {
 588                                         mux {
 589                                                 groups = "spi0_ss1";
 590                                                 function = "spi0";
 591                                         };
 592                                 };
 593
 594                                 spi0_ss2_pins: spi0_ss2 {
 595                                         mux {
 596                                                 groups = "spi0_ss2";
 597                                                 function = "spi0";
 598                                         };
 599                                 };
 600
 601
 602                                 spi1_a_pins: spi1_a {
 603                                         mux {
 604                                                 groups = "spi1_miso_a",
 605                                                         "spi1_mosi_a",
 606                                                         "spi1_clk_a";
 607                                                 function = "spi1";
 608                                         };
 609                                 };
 610
 611                                 spi1_ss0_a_pins: spi1_ss0_a {
 612                                         mux {
 613                                                 groups = "spi1_ss0_a";
 614                                                 function = "spi1";
 615                                         };
 616                                 };
 617
 618                                 spi1_ss1_pins: spi1_ss1 {
 619                                         mux {
 620                                                 groups = "spi1_ss1";
 621                                                 function = "spi1";
 622                                         };
 623                                 };
 624
 625                                 spi1_x_pins: spi1_x {
 626                                         mux {
 627                                                 groups = "spi1_miso_x",
 628                                                         "spi1_mosi_x",
 629                                                         "spi1_clk_x";
 630                                                 function = "spi1";
 631                                         };
 632                                 };
 633
 634                                 spi1_ss0_x_pins: spi1_ss0_x {
 635                                         mux {
 636                                                 groups = "spi1_ss0_x";
 637                                                 function = "spi1";
 638                                         };
 639                                 };
 640
 641                                 i2c0_pins: i2c0 {
 642                                         mux {
 643                                                 groups = "i2c0_sck",
 644                                                         "i2c0_sda";
 645                                                 function = "i2c0";
 646                                         };
 647                                 };
 648
 649                                 i2c1_z_pins: i2c1_z {
 650                                         mux {
 651                                                 groups = "i2c1_sck_z",
 652                                                         "i2c1_sda_z";
 653                                                 function = "i2c1";
 654                                         };
 655                                 };
 656
 657                                 i2c1_x_pins: i2c1_x {
 658                                         mux {
 659                                                 groups = "i2c1_sck_x",
 660                                                         "i2c1_sda_x";
 661                                                 function = "i2c1";
 662                                         };
 663                                 };
 664
 665                                 i2c2_x_pins: i2c2_x {
 666                                         mux {
 667                                                 groups = "i2c2_sck_x",
 668                                                         "i2c2_sda_x";
 669                                                 function = "i2c2";
 670                                         };
 671                                 };
 672
 673                                 i2c2_a_pins: i2c2_a {
 674                                         mux {
 675                                                 groups = "i2c2_sck_a",
 676                                                         "i2c2_sda_a";
 677                                                 function = "i2c2";
 678                                         };
 679                                 };
 680
 681                                 i2c3_a6_pins: i2c3_a6 {
 682                                         mux {
 683                                                 groups = "i2c3_sda_a6",
 684                                                         "i2c3_sck_a7";
 685                                                 function = "i2c3";
 686                                         };
 687                                 };
 688
 689                                 i2c3_a12_pins: i2c3_a12 {
 690                                         mux {
 691                                                 groups = "i2c3_sda_a12",
 692                                                         "i2c3_sck_a13";
 693                                                 function = "i2c3";
 694                                         };
 695                                 };
 696
 697                                 i2c3_a19_pins: i2c3_a19 {
 698                                         mux {
 699                                                 groups = "i2c3_sda_a19",
 700                                                         "i2c3_sck_a20";
 701                                                 function = "i2c3";
 702                                         };
 703                                 };
 704
 705                                 uart_a_pins: uart_a {
 706                                         mux {
 707                                                 groups = "uart_tx_a",
 708                                                         "uart_rx_a";
 709                                                 function = "uart_a";
 710                                         };
 711                                 };
 712
 713                                 uart_a_cts_rts_pins: uart_a_cts_rts {
 714                                         mux {
 715                                                 groups = "uart_cts_a",
 716                                                         "uart_rts_a";
 717                                                 function = "uart_a";
 718                                         };
 719                                 };
 720
 721                                 uart_b_x_pins: uart_b_x {
 722                                         mux {
 723                                                 groups = "uart_tx_b_x",
 724                                                         "uart_rx_b_x";
 725                                                 function = "uart_b";
 726                                         };
 727                                 };
 728
 729                                 uart_b_x_cts_rts_pins: uart_b_x_cts_rts {
 730                                         mux {
 731                                                 groups = "uart_cts_b_x",
 732                                                         "uart_rts_b_x";
 733                                                 function = "uart_b";
 734                                         };
 735                                 };
 736
 737                                 uart_b_z_pins: uart_b_z {
 738                                         mux {
 739                                                 groups = "uart_tx_b_z",
 740                                                         "uart_rx_b_z";
 741                                                 function = "uart_b";
 742                                         };
 743                                 };
 744
 745                                 uart_b_z_cts_rts_pins: uart_b_z_cts_rts {
 746                                         mux {
 747                                                 groups = "uart_cts_b_z",
 748                                                         "uart_rts_b_z";
 749                                                 function = "uart_b";
 750                                         };
 751                                 };
 752
 753                                 uart_ao_b_z_pins: uart_ao_b_z {
 754                                         mux {
 755                                                 groups = "uart_ao_tx_b_z",
 756                                                         "uart_ao_rx_b_z";
 757                                                 function = "uart_ao_b_z";
 758                                         };
 759                                 };
 760
 761                                 uart_ao_b_z_cts_rts_pins: uart_ao_b_z_cts_rts {
 762                                         mux {
 763                                                 groups = "uart_ao_cts_b_z",
 764                                                         "uart_ao_rts_b_z";
 765                                                 function = "uart_ao_b_z";
 766                                         };
 767                                 };
 768
 769                                 mclk_b_pins: mclk_b {
 770                                         mux {
 771                                                 groups = "mclk_b";
 772                                                 function = "mclk_b";
 773                                         };
 774                                 };
 775
 776                                 mclk_c_pins: mclk_c {
 777                                         mux {
 778                                                 groups = "mclk_c";
 779                                                 function = "mclk_c";
 780                                         };
 781                                 };
 782
 783                                 tdma_sclk_pins: tdma_sclk {
 784                                         mux {
 785                                                 groups = "tdma_sclk";
 786                                                 function = "tdma";
 787                                         };
 788                                 };
 789
 790                                 tdma_sclk_slv_pins: tdma_sclk_slv {
 791                                         mux {
 792                                                 groups = "tdma_sclk_slv";
 793                                                 function = "tdma";
 794                                         };
 795                                 };
 796
 797                                 tdma_fs_pins: tdma_fs {
 798                                         mux {
 799                                                 groups = "tdma_fs";
 800                                                 function = "tdma";
 801                                         };
 802                                 };
 803
 804                                 tdma_fs_slv_pins: tdma_fs_slv {
 805                                         mux {
 806                                                 groups = "tdma_fs_slv";
 807                                                 function = "tdma";
 808                                         };
 809                                 };
 810
 811                                 tdma_din0_pins: tdma_din0 {
 812                                         mux {
 813                                                 groups = "tdma_din0";
 814                                                 function = "tdma";
 815                                         };
 816                                 };
 817
 818                                 tdma_dout0_x14_pins: tdma_dout0_x14 {
 819                                         mux {
 820                                                 groups = "tdma_dout0_x14";
 821                                                 function = "tdma";
 822                                         };
 823                                 };
 824
 825                                 tdma_dout0_x15_pins: tdma_dout0_x15 {
 826                                         mux {
 827                                                 groups = "tdma_dout0_x15";
 828                                                 function = "tdma";
 829                                         };
 830                                 };
 831
 832                                 tdma_dout1_pins: tdma_dout1 {
 833                                         mux {
 834                                                 groups = "tdma_dout1";
 835                                                 function = "tdma";
 836                                         };
 837                                 };
 838
 839                                 tdma_din1_pins: tdma_din1 {
 840                                         mux {
 841                                                 groups = "tdma_din1";
 842                                                 function = "tdma";
 843                                         };
 844                                 };
 845
 846                                 tdmb_sclk_pins: tdmb_sclk {
 847                                         mux {
 848                                                 groups = "tdmb_sclk";
 849                                                 function = "tdmb";
 850                                         };
 851                                 };
 852
 853                                 tdmb_sclk_slv_pins: tdmb_sclk_slv {
 854                                         mux {
 855                                                 groups = "tdmb_sclk_slv";
 856                                                 function = "tdmb";
 857                                         };
 858                                 };
 859
 860                                 tdmb_fs_pins: tdmb_fs {
 861                                         mux {
 862                                                 groups = "tdmb_fs";
 863                                                 function = "tdmb";
 864                                         };
 865                                 };
 866
 867                                 tdmb_fs_slv_pins: tdmb_fs_slv {
 868                                         mux {
 869                                                 groups = "tdmb_fs_slv";
 870                                                 function = "tdmb";
 871                                         };
 872                                 };
 873
 874                                 tdmb_din0_pins: tdmb_din0 {
 875                                         mux {
 876                                                 groups = "tdmb_din0";
 877                                                 function = "tdmb";
 878                                         };
 879                                 };
 880
 881                                 tdmb_dout0_pins: tdmb_dout0 {
 882                                         mux {
 883                                                 groups = "tdmb_dout0";
 884                                                 function = "tdmb";
 885                                         };
 886                                 };
 887
 888                                 tdmb_din1_pins: tdmb_din1 {
 889                                         mux {
 890                                                 groups = "tdmb_din1";
 891                                                 function = "tdmb";
 892                                         };
 893                                 };
 894
 895                                 tdmb_dout1_pins: tdmb_dout1 {
 896                                         mux {
 897                                                 groups = "tdmb_dout1";
 898                                                 function = "tdmb";
 899                                         };
 900                                 };
 901
 902                                 tdmb_din2_pins: tdmb_din2 {
 903                                         mux {
 904                                                 groups = "tdmb_din2";
 905                                                 function = "tdmb";
 906                                         };
 907                                 };
 908
 909                                 tdmb_dout2_pins: tdmb_dout2 {
 910                                         mux {
 911                                                 groups = "tdmb_dout2";
 912                                                 function = "tdmb";
 913                                         };
 914                                 };
 915
 916                                 tdmb_din3_pins: tdmb_din3 {
 917                                         mux {
 918                                                 groups = "tdmb_din3";
 919                                                 function = "tdmb";
 920                                         };
 921                                 };
 922
 923                                 tdmb_dout3_pins: tdmb_dout3 {
 924                                         mux {
 925                                                 groups = "tdmb_dout3";
 926                                                 function = "tdmb";
 927                                         };
 928                                 };
 929
 930                                 tdmc_sclk_pins: tdmc_sclk {
 931                                         mux {
 932                                                 groups = "tdmc_sclk";
 933                                                 function = "tdmc";
 934                                         };
 935                                 };
 936
 937                                 tdmc_sclk_slv_pins: tdmc_sclk_slv {
 938                                         mux {
 939                                                 groups = "tdmc_sclk_slv";
 940                                                 function = "tdmc";
 941                                         };
 942                                 };
 943
 944                                 tdmc_fs_pins: tdmc_fs {
 945                                         mux {
 946                                                 groups = "tdmc_fs";
 947                                                 function = "tdmc";
 948                                         };
 949                                 };
 950
 951                                 tdmc_fs_slv_pins: tdmc_fs_slv {
 952                                         mux {
 953                                                 groups = "tdmc_fs_slv";
 954                                                 function = "tdmc";
 955                                         };
 956                                 };
 957
 958                                 tdmc_din0_pins: tdmc_din0 {
 959                                         mux {
 960                                                 groups = "tdmc_din0";
 961                                                 function = "tdmc";
 962                                         };
 963                                 };
 964
 965                                 tdmc_dout0_pins: tdmc_dout0 {
 966                                         mux {
 967                                                 groups = "tdmc_dout0";
 968                                                 function = "tdmc";
 969                                         };
 970                                 };
 971
 972                                 tdmc_din1_pins: tdmc_din1 {
 973                                         mux {
 974                                                 groups = "tdmc_din1";
 975                                                 function = "tdmc";
 976                                         };
 977                                 };
 978
 979                                 tdmc_dout1_pins: tdmc_dout1 {
 980                                         mux {
 981                                                 groups = "tdmc_dout1";
 982                                                 function = "tdmc";
 983                                         };
 984                                 };
 985
 986                                 tdmc_din2_pins: tdmc_din2 {
 987                                         mux {
 988                                                 groups = "tdmc_din2";
 989                                                 function = "tdmc";
 990                                         };
 991                                 };
 992
 993                                 tdmc_dout2_pins: tdmc_dout2 {
 994                                         mux {
 995                                                 groups = "tdmc_dout2";
 996                                                 function = "tdmc";
 997                                         };
 998                                 };
 999
1000                                 tdmc_din3_pins: tdmc_din3 {
1001                                         mux {
1002                                                 groups = "tdmc_din3";
1003                                                 function = "tdmc";
1004                                         };
1005                                 };
1006
1007                                 tdmc_dout3_pins: tdmc_dout3 {
1008                                         mux {
1009                                                 groups = "tdmc_dout3";
1010                                                 function = "tdmc";
1011                                         };
1012                                 };
1013                         };
1014                 };
1015
1016                 sram: sram@fffc0000 {
1017                         compatible = "amlogic,meson-axg-sram", "mmio-sram";
1018                         reg = <0x0 0xfffc0000 0x0 0x20000>;
1019                         #address-cells = <1>;
1020                         #size-cells = <1>;
1021                         ranges = <0 0x0 0xfffc0000 0x20000>;
1022
1023                         cpu_scp_lpri: scp-shmem@0 {
1024                                 compatible = "amlogic,meson-axg-scp-shmem";
1025                                 reg = <0x13000 0x400>;
1026                         };
1027
1028                         cpu_scp_hpri: scp-shmem@200 {
1029                                 compatible = "amlogic,meson-axg-scp-shmem";
1030                                 reg = <0x13400 0x400>;
1031                         };
1032                 };
1033
1034                 aobus: bus@ff800000 {
1035                         compatible = "simple-bus";
1036                         reg = <0x0 0xff800000 0x0 0x100000>;
1037                         #address-cells = <2>;
1038                         #size-cells = <2>;
1039                         ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>;
1040
1041                         pinctrl_aobus: pinctrl@14 {
1042                                 compatible = "amlogic,meson-axg-aobus-pinctrl";
1043                                 #address-cells = <2>;
1044                                 #size-cells = <2>;
1045                                 ranges;
1046
1047                                 gpio_ao: bank@14 {
1048                                         reg = <0x0 0x00014 0x0 0x8>,
1049                                                 <0x0 0x0002c 0x0 0x4>,
1050                                                 <0x0 0x00024 0x0 0x8>;
1051                                         reg-names = "mux", "pull", "gpio";
1052                                         gpio-controller;
1053                                         #gpio-cells = <2>;
1054                                         gpio-ranges = <&pinctrl_aobus 0 0 15>;
1055                                 };
1056
1057                                 remote_input_ao_pins: remote_input_ao {
1058                                         mux {
1059                                                 groups = "remote_input_ao";
1060                                                 function = "remote_input_ao";
1061                                         };
1062                                 };
1063
1064                                 uart_ao_a_pins: uart_ao_a {
1065                                         mux {
1066                                                 groups = "uart_ao_tx_a",
1067                                                         "uart_ao_rx_a";
1068                                                 function = "uart_ao_a";
1069                                         };
1070                                 };
1071
1072                                 uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
1073                                         mux {
1074                                                 groups = "uart_ao_cts_a",
1075                                                         "uart_ao_rts_a";
1076                                                 function = "uart_ao_a";
1077                                         };
1078                                 };
1079
1080                                 uart_ao_b_pins: uart_ao_b {
1081                                         mux {
1082                                                 groups = "uart_ao_tx_b",
1083                                                         "uart_ao_rx_b";
1084                                                 function = "uart_ao_b";
1085                                         };
1086                                 };
1087
1088                                 uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
1089                                         mux {
1090                                                 groups = "uart_ao_cts_b",
1091                                                         "uart_ao_rts_b";
1092                                                 function = "uart_ao_b";
1093                                         };
1094                                 };
1095                         };
1096
1097                         sec_AO: ao-secure@140 {
1098                                 compatible = "amlogic,meson-gx-ao-secure", "syscon";
1099                                 reg = <0x0 0x140 0x0 0x140>;
1100                                 amlogic,has-chip-id;
1101                         };
1102
1103                         pwm_AO_ab: pwm@7000 {
1104                                 compatible = "amlogic,meson-axg-ao-pwm";
1105                                 reg = <0x0 0x07000 0x0 0x20>;
1106                                 #pwm-cells = <3>;
1107                                 status = "disabled";
1108                         };
1109
1110                         pwm_AO_cd: pwm@2000 {
1111                                 compatible = "amlogic,meson-axg-ao-pwm";
1112                                 reg = <0x0 0x02000  0x0 0x20>;
1113                                 #pwm-cells = <3>;
1114                                 status = "disabled";
1115                         };
1116
1117                         i2c_AO: i2c@5000 {
1118                                 compatible = "amlogic,meson-axg-i2c";
1119                                 status = "disabled";
1120                                 reg = <0x0 0x05000 0x0 0x20>;
1121                                 interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>;
1122                                 #address-cells = <1>;
1123                                 #size-cells = <0>;
1124                                 clocks = <&clkc CLKID_I2C>;
1125                                 clock-names = "clk_i2c";
1126                         };
1127
1128                         uart_AO: serial@3000 {
1129                                 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
1130                                 reg = <0x0 0x3000 0x0 0x18>;
1131                                 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
1132                                 clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>;
1133                                 clock-names = "xtal", "pclk", "baud";
1134                                 status = "disabled";
1135                         };
1136
1137                         uart_AO_B: serial@4000 {
1138                                 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
1139                                 reg = <0x0 0x4000 0x0 0x18>;
1140                                 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
1141                                 clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>;
1142                                 clock-names = "xtal", "pclk", "baud";
1143                                 status = "disabled";
1144                         };
1145
1146                         ir: ir@8000 {
1147                                 compatible = "amlogic,meson-gxbb-ir";
1148                                 reg = <0x0 0x8000 0x0 0x20>;
1149                                 interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
1150                                 status = "disabled";
1151                         };
1152                 };
1153         };
1154 };