1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2016 Andreas Färber
5 * Copyright (c) 2016 BayLibre, SAS.
6 * Author: Neil Armstrong <narmstrong@baylibre.com>
8 * Copyright (c) 2016 Endless Computers, Inc.
9 * Author: Carlo Caione <carlo@endlessm.com>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 interrupt-parent = <&gic>;
26 /* 16 MiB reserved for Hardware ROM Firmware */
27 hwrom_reserved: hwrom@0 {
28 reg = <0x0 0x0 0x0 0x1000000>;
32 /* 2 MiB reserved for ARM Trusted Firmware (BL31) */
33 secmon_reserved: secmon@10000000 {
34 reg = <0x0 0x10000000 0x0 0x200000>;
39 compatible = "shared-dma-pool";
41 size = <0x0 0xbc00000>;
42 alignment = <0x0 0x400000>;
48 #address-cells = <0x2>;
53 compatible = "arm,cortex-a53", "arm,armv8";
55 enable-method = "psci";
56 next-level-cache = <&l2>;
57 clocks = <&scpi_dvfs 0>;
62 compatible = "arm,cortex-a53", "arm,armv8";
64 enable-method = "psci";
65 next-level-cache = <&l2>;
66 clocks = <&scpi_dvfs 0>;
71 compatible = "arm,cortex-a53", "arm,armv8";
73 enable-method = "psci";
74 next-level-cache = <&l2>;
75 clocks = <&scpi_dvfs 0>;
80 compatible = "arm,cortex-a53", "arm,armv8";
82 enable-method = "psci";
83 next-level-cache = <&l2>;
84 clocks = <&scpi_dvfs 0>;
93 compatible = "arm,cortex-a53-pmu";
94 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
95 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
96 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
97 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
98 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
102 compatible = "arm,psci-0.2";
107 compatible = "arm,armv8-timer";
108 interrupts = <GIC_PPI 13
109 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
111 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
113 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
115 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
119 compatible = "fixed-clock";
120 clock-frequency = <24000000>;
121 clock-output-names = "xtal";
127 compatible = "amlogic,meson-gx-sm", "amlogic,meson-gxbb-sm";
132 compatible = "amlogic,meson-gx-efuse", "amlogic,meson-gxbb-efuse";
133 #address-cells = <1>;
141 eth_mac: eth_mac@34 {
151 compatible = "amlogic,meson-gxbb-scpi", "arm,scpi-pre-1.0";
152 mboxes = <&mailbox 1 &mailbox 2>;
153 shmem = <&cpu_scp_lpri &cpu_scp_hpri>;
155 scpi_clocks: clocks {
156 compatible = "arm,scpi-clocks";
158 scpi_dvfs: scpi_clocks@0 {
159 compatible = "arm,scpi-dvfs-clocks";
162 clock-output-names = "vcpu";
166 scpi_sensors: sensors {
167 compatible = "amlogic,meson-gxbb-scpi-sensors", "arm,scpi-sensors";
168 #thermal-sensor-cells = <1>;
173 compatible = "simple-bus";
174 #address-cells = <2>;
179 compatible = "simple-bus";
180 reg = <0x0 0xc1100000 0x0 0x100000>;
181 #address-cells = <2>;
183 ranges = <0x0 0x0 0x0 0xc1100000 0x0 0x100000>;
185 gpio_intc: interrupt-controller@9880 {
186 compatible = "amlogic,meson-gpio-intc";
187 reg = <0x0 0x9880 0x0 0x10>;
188 interrupt-controller;
189 #interrupt-cells = <2>;
190 amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>;
194 reset: reset-controller@4404 {
195 compatible = "amlogic,meson-gx-reset", "amlogic,meson-gxbb-reset";
196 reg = <0x0 0x04404 0x0 0x9c>;
200 uart_A: serial@84c0 {
201 compatible = "amlogic,meson-gx-uart";
202 reg = <0x0 0x84c0 0x0 0x18>;
203 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
207 uart_B: serial@84dc {
208 compatible = "amlogic,meson-gx-uart";
209 reg = <0x0 0x84dc 0x0 0x18>;
210 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
215 compatible = "amlogic,meson-gx-i2c", "amlogic,meson-gxbb-i2c";
216 reg = <0x0 0x08500 0x0 0x20>;
217 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>;
218 #address-cells = <1>;
224 compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm";
225 reg = <0x0 0x08550 0x0 0x10>;
231 compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm";
232 reg = <0x0 0x08650 0x0 0x10>;
238 compatible = "amlogic,meson-saradc";
239 reg = <0x0 0x8680 0x0 0x34>;
240 #io-channel-cells = <1>;
241 interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>;
246 compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm";
247 reg = <0x0 0x086c0 0x0 0x10>;
252 uart_C: serial@8700 {
253 compatible = "amlogic,meson-gx-uart";
254 reg = <0x0 0x8700 0x0 0x18>;
255 interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>;
260 compatible = "amlogic,meson-gx-i2c", "amlogic,meson-gxbb-i2c";
261 reg = <0x0 0x087c0 0x0 0x20>;
262 interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>;
263 #address-cells = <1>;
269 compatible = "amlogic,meson-gx-i2c", "amlogic,meson-gxbb-i2c";
270 reg = <0x0 0x087e0 0x0 0x20>;
271 interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>;
272 #address-cells = <1>;
278 compatible = "amlogic,meson-gx-spicc";
279 reg = <0x0 0x08d80 0x0 0x80>;
280 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
281 #address-cells = <1>;
287 compatible = "amlogic,meson-gx-spifc", "amlogic,meson-gxbb-spifc";
288 reg = <0x0 0x08c80 0x0 0x80>;
289 #address-cells = <1>;
295 compatible = "amlogic,meson-gx-wdt", "amlogic,meson-gxbb-wdt";
296 reg = <0x0 0x098d0 0x0 0x10>;
301 gic: interrupt-controller@c4301000 {
302 compatible = "arm,gic-400";
303 reg = <0x0 0xc4301000 0 0x1000>,
304 <0x0 0xc4302000 0 0x2000>,
305 <0x0 0xc4304000 0 0x2000>,
306 <0x0 0xc4306000 0 0x2000>;
307 interrupt-controller;
308 interrupts = <GIC_PPI 9
309 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
310 #interrupt-cells = <3>;
311 #address-cells = <0>;
314 sram: sram@c8000000 {
315 compatible = "amlogic,meson-gx-sram", "amlogic,meson-gxbb-sram", "mmio-sram";
316 reg = <0x0 0xc8000000 0x0 0x14000>;
318 #address-cells = <1>;
320 ranges = <0 0x0 0xc8000000 0x14000>;
322 cpu_scp_lpri: scp-shmem@0 {
323 compatible = "amlogic,meson-gx-scp-shmem", "amlogic,meson-gxbb-scp-shmem";
324 reg = <0x13000 0x400>;
327 cpu_scp_hpri: scp-shmem@200 {
328 compatible = "amlogic,meson-gx-scp-shmem", "amlogic,meson-gxbb-scp-shmem";
329 reg = <0x13400 0x400>;
333 aobus: bus@c8100000 {
334 compatible = "simple-bus";
335 reg = <0x0 0xc8100000 0x0 0x100000>;
336 #address-cells = <2>;
338 ranges = <0x0 0x0 0x0 0xc8100000 0x0 0x100000>;
340 sysctrl_AO: sys-ctrl@0 {
341 compatible = "amlogic,meson-gx-ao-sysctrl", "syscon", "simple-mfd";
342 reg = <0x0 0x0 0x0 0x100>;
344 pwrc_vpu: power-controller-vpu {
345 compatible = "amlogic,meson-gx-pwrc-vpu";
346 #power-domain-cells = <0>;
347 amlogic,hhi-sysctrl = <&sysctrl>;
350 clkc_AO: clock-controller {
351 compatible = "amlogic,meson-gx-aoclkc";
358 compatible = "amlogic,meson-gx-ao-cec";
359 reg = <0x0 0x00100 0x0 0x14>;
360 interrupts = <GIC_SPI 199 IRQ_TYPE_EDGE_RISING>;
363 sec_AO: ao-secure@140 {
364 compatible = "amlogic,meson-gx-ao-secure", "syscon";
365 reg = <0x0 0x140 0x0 0x140>;
369 uart_AO: serial@4c0 {
370 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
371 reg = <0x0 0x004c0 0x0 0x18>;
372 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
376 uart_AO_B: serial@4e0 {
377 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
378 reg = <0x0 0x004e0 0x0 0x18>;
379 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
384 compatible = "amlogic,meson-gx-i2c", "amlogic,meson-gxbb-i2c";
385 reg = <0x0 0x500 0x0 0x20>;
386 interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>;
387 #address-cells = <1>;
393 compatible = "amlogic,meson-gx-ao-pwm", "amlogic,meson-gxbb-ao-pwm";
394 reg = <0x0 0x00550 0x0 0x10>;
400 compatible = "amlogic,meson-gx-ir", "amlogic,meson-gxbb-ir";
401 reg = <0x0 0x00580 0x0 0x40>;
402 interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
407 periphs: periphs@c8834000 {
408 compatible = "simple-bus";
409 reg = <0x0 0xc8834000 0x0 0x2000>;
410 #address-cells = <2>;
412 ranges = <0x0 0x0 0x0 0xc8834000 0x0 0x2000>;
415 compatible = "amlogic,meson-rng";
416 reg = <0x0 0x0 0x0 0x4>;
420 hiubus: bus@c883c000 {
421 compatible = "simple-bus";
422 reg = <0x0 0xc883c000 0x0 0x2000>;
423 #address-cells = <2>;
425 ranges = <0x0 0x0 0x0 0xc883c000 0x0 0x2000>;
427 sysctrl: system-controller@0 {
428 compatible = "amlogic,meson-gx-hhi-sysctrl", "syscon", "simple-mfd";
432 mailbox: mailbox@404 {
433 compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu";
434 reg = <0 0x404 0 0x4c>;
435 interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
436 <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>,
437 <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>;
442 ethmac: ethernet@c9410000 {
443 compatible = "amlogic,meson-gx-dwmac", "amlogic,meson-gxbb-dwmac", "snps,dwmac";
444 reg = <0x0 0xc9410000 0x0 0x10000
445 0x0 0xc8834540 0x0 0x4>;
446 interrupts = <GIC_SPI 8 IRQ_TYPE_EDGE_RISING>;
447 interrupt-names = "macirq";
452 compatible = "simple-bus";
453 reg = <0x0 0xd0000000 0x0 0x200000>;
454 #address-cells = <2>;
456 ranges = <0x0 0x0 0x0 0xd0000000 0x0 0x200000>;
458 sd_emmc_a: mmc@70000 {
459 compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc";
460 reg = <0x0 0x70000 0x0 0x2000>;
461 interrupts = <GIC_SPI 216 IRQ_TYPE_EDGE_RISING>;
465 sd_emmc_b: mmc@72000 {
466 compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc";
467 reg = <0x0 0x72000 0x0 0x2000>;
468 interrupts = <GIC_SPI 217 IRQ_TYPE_EDGE_RISING>;
472 sd_emmc_c: mmc@74000 {
473 compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc";
474 reg = <0x0 0x74000 0x0 0x2000>;
475 interrupts = <GIC_SPI 218 IRQ_TYPE_EDGE_RISING>;
481 compatible = "amlogic,meson-gx-vpu";
482 reg = <0x0 0xd0100000 0x0 0x100000>,
483 <0x0 0xc883c000 0x0 0x1000>,
484 <0x0 0xc8838000 0x0 0x1000>;
485 reg-names = "vpu", "hhi", "dmc";
486 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
487 #address-cells = <1>;
490 /* CVBS VDAC output port */
491 cvbs_vdac_port: port@0 {
495 /* HDMI-TX output port */
496 hdmi_tx_port: port@1 {
499 hdmi_tx_out: endpoint {
500 remote-endpoint = <&hdmi_tx_in>;
505 hdmi_tx: hdmi-tx@c883a000 {
506 compatible = "amlogic,meson-gx-dw-hdmi";
507 reg = <0x0 0xc883a000 0x0 0x1c>;
508 interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>;
509 #address-cells = <1>;
514 hdmi_tx_venc_port: port@0 {
517 hdmi_tx_in: endpoint {
518 remote-endpoint = <&hdmi_tx_out>;
523 hdmi_tx_tmds_port: port@1 {