1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2016 Endless Computers, Inc.
4 * Author: Carlo Caione <carlo@endlessm.com>
7 #include "meson-gx.dtsi"
8 #include <dt-bindings/clock/gxbb-clkc.h>
9 #include <dt-bindings/clock/gxbb-aoclkc.h>
10 #include <dt-bindings/gpio/meson-gxl-gpio.h>
11 #include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
14 compatible = "amlogic,meson-gxl";
17 /* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */
18 secmon_reserved_alt: secmon@5000000 {
19 reg = <0x0 0x05000000 0x0 0x300000>;
27 compatible = "amlogic,meson-gxl-dwc3";
32 clocks = <&clkc CLKID_USB>;
33 clock-names = "usb_general";
34 resets = <&reset RESET_USB_OTG>;
35 reset-names = "usb_otg";
38 compatible = "snps,dwc3";
39 reg = <0x0 0xc9000000 0x0 0x100000>;
40 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
42 maximum-speed = "high-speed";
43 snps,dis_u2_susphy_quirk;
44 phys = <&usb3_phy>, <&usb2_phy0>, <&usb2_phy1>;
51 usb2_phy0: phy@78000 {
52 compatible = "amlogic,meson-gxl-usb2-phy";
54 reg = <0x0 0x78000 0x0 0x20>;
55 clocks = <&clkc CLKID_USB>;
57 resets = <&reset RESET_USB_OTG>;
62 usb2_phy1: phy@78020 {
63 compatible = "amlogic,meson-gxl-usb2-phy";
65 reg = <0x0 0x78020 0x0 0x20>;
66 clocks = <&clkc CLKID_USB>;
68 resets = <&reset RESET_USB_OTG>;
74 compatible = "amlogic,meson-gxl-usb3-phy";
76 reg = <0x0 0x78080 0x0 0x20>;
77 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
78 clocks = <&clkc CLKID_USB>, <&clkc_AO CLKID_AO_CEC_32K>;
79 clock-names = "phy", "peripheral";
80 resets = <&reset RESET_USB_OTG>, <&reset RESET_USB_OTG>;
81 reset-names = "phy", "peripheral";
87 reg = <0x0 0xc9410000 0x0 0x10000
88 0x0 0xc8834540 0x0 0x4>;
90 clocks = <&clkc CLKID_ETH>,
91 <&clkc CLKID_FCLK_DIV2>,
93 clock-names = "stmmaceth", "clkin0", "clkin1";
98 compatible = "snps,dwmac-mdio";
103 pinctrl_aobus: pinctrl@14 {
104 compatible = "amlogic,meson-gxl-aobus-pinctrl";
105 #address-cells = <2>;
110 reg = <0x0 0x00014 0x0 0x8>,
111 <0x0 0x0002c 0x0 0x4>,
112 <0x0 0x00024 0x0 0x8>;
113 reg-names = "mux", "pull", "gpio";
116 gpio-ranges = <&pinctrl_aobus 0 0 14>;
119 uart_ao_a_pins: uart_ao_a {
121 groups = "uart_tx_ao_a", "uart_rx_ao_a";
122 function = "uart_ao";
126 uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
128 groups = "uart_cts_ao_a",
130 function = "uart_ao";
134 uart_ao_b_pins: uart_ao_b {
136 groups = "uart_tx_ao_b", "uart_rx_ao_b";
137 function = "uart_ao_b";
141 uart_ao_b_0_1_pins: uart_ao_b_0_1 {
143 groups = "uart_tx_ao_b_0", "uart_rx_ao_b_1";
144 function = "uart_ao_b";
148 uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
150 groups = "uart_cts_ao_b",
152 function = "uart_ao_b";
156 remote_input_ao_pins: remote_input_ao {
158 groups = "remote_input_ao";
159 function = "remote_input_ao";
163 i2c_ao_pins: i2c_ao {
165 groups = "i2c_sck_ao",
171 pwm_ao_a_3_pins: pwm_ao_a_3 {
173 groups = "pwm_ao_a_3";
174 function = "pwm_ao_a";
178 pwm_ao_a_8_pins: pwm_ao_a_8 {
180 groups = "pwm_ao_a_8";
181 function = "pwm_ao_a";
185 pwm_ao_b_pins: pwm_ao_b {
188 function = "pwm_ao_b";
192 pwm_ao_b_6_pins: pwm_ao_b_6 {
194 groups = "pwm_ao_b_6";
195 function = "pwm_ao_b";
199 i2s_out_ch23_ao_pins: i2s_out_ch23_ao {
201 groups = "i2s_out_ch23_ao";
202 function = "i2s_out_ao";
206 i2s_out_ch45_ao_pins: i2s_out_ch45_ao {
208 groups = "i2s_out_ch45_ao";
209 function = "i2s_out_ao";
213 spdif_out_ao_6_pins: spdif_out_ao_6 {
215 groups = "spdif_out_ao_6";
216 function = "spdif_out_ao";
220 spdif_out_ao_9_pins: spdif_out_ao_9 {
222 groups = "spdif_out_ao_9";
223 function = "spdif_out_ao";
227 ao_cec_pins: ao_cec {
234 ee_cec_pins: ee_cec {
244 clocks = <&clkc_AO CLKID_AO_CEC_32K>;
245 clock-names = "core";
249 compatible = "amlogic,meson-gxl-aoclkc", "amlogic,meson-gx-aoclkc";
253 compatible = "amlogic,meson-gpio-intc",
254 "amlogic,meson-gxl-gpio-intc";
259 compatible = "amlogic,meson-gxl-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
260 resets = <&reset RESET_HDMITX_CAPB3>,
261 <&reset RESET_HDMI_SYSTEM_RESET>,
262 <&reset RESET_HDMI_TX>;
263 reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
264 clocks = <&clkc CLKID_HDMI_PCLK>,
266 <&clkc CLKID_GCLK_VENCI_INT0>;
267 clock-names = "isfr", "iahb", "venci";
271 clkc: clock-controller {
272 compatible = "amlogic,gxl-clkc";
278 clocks = <&clkc CLKID_I2C>;
282 clocks = <&clkc CLKID_AO_I2C>;
286 clocks = <&clkc CLKID_I2C>;
290 clocks = <&clkc CLKID_I2C>;
294 pinctrl_periphs: pinctrl@4b0 {
295 compatible = "amlogic,meson-gxl-periphs-pinctrl";
296 #address-cells = <2>;
301 reg = <0x0 0x004b0 0x0 0x28>,
302 <0x0 0x004e8 0x0 0x14>,
303 <0x0 0x00520 0x0 0x14>,
304 <0x0 0x00430 0x0 0x40>;
305 reg-names = "mux", "pull", "pull-enable", "gpio";
308 gpio-ranges = <&pinctrl_periphs 0 0 100>;
313 groups = "emmc_nand_d07",
320 emmc_ds_pins: emmc-ds {
327 emmc_clk_gate_pins: emmc_clk_gate {
330 function = "gpio_periphs";
357 spi_ss0_pins: spi-ss0 {
364 sdcard_pins: sdcard {
366 groups = "sdcard_d0",
376 sdcard_clk_gate_pins: sdcard_clk_gate {
379 function = "gpio_periphs";
399 sdio_clk_gate_pins: sdio_clk_gate {
402 function = "gpio_periphs";
410 sdio_irq_pins: sdio_irq {
417 uart_a_pins: uart_a {
419 groups = "uart_tx_a",
425 uart_a_cts_rts_pins: uart_a_cts_rts {
427 groups = "uart_cts_a",
433 uart_b_pins: uart_b {
435 groups = "uart_tx_b",
441 uart_b_cts_rts_pins: uart_b_cts_rts {
443 groups = "uart_cts_b",
449 uart_c_pins: uart_c {
451 groups = "uart_tx_c",
457 uart_c_cts_rts_pins: uart_c_cts_rts {
459 groups = "uart_cts_c",
467 groups = "i2c_sck_a",
475 groups = "i2c_sck_b",
483 groups = "i2c_sck_c",
509 eth_link_led_pins: eth_link_led {
511 groups = "eth_link_led";
512 function = "eth_led";
516 eth_act_led_pins: eth_act_led {
518 groups = "eth_act_led";
519 function = "eth_led";
558 pwm_f_clk_pins: pwm_f_clk {
560 groups = "pwm_f_clk";
565 pwm_f_x_pins: pwm_f_x {
572 hdmi_hpd_pins: hdmi_hpd {
575 function = "hdmi_hpd";
579 hdmi_i2c_pins: hdmi_i2c {
581 groups = "hdmi_sda", "hdmi_scl";
582 function = "hdmi_i2c";
586 i2s_am_clk_pins: i2s_am_clk {
588 groups = "i2s_am_clk";
589 function = "i2s_out";
593 i2s_out_ao_clk_pins: i2s_out_ao_clk {
595 groups = "i2s_out_ao_clk";
596 function = "i2s_out";
600 i2s_out_lr_clk_pins: i2s_out_lr_clk {
602 groups = "i2s_out_lr_clk";
603 function = "i2s_out";
607 i2s_out_ch01_pins: i2s_out_ch01 {
609 groups = "i2s_out_ch01";
610 function = "i2s_out";
613 i2sout_ch23_z_pins: i2sout_ch23_z {
615 groups = "i2sout_ch23_z";
616 function = "i2s_out";
620 i2sout_ch45_z_pins: i2sout_ch45_z {
622 groups = "i2sout_ch45_z";
623 function = "i2s_out";
627 i2sout_ch67_z_pins: i2sout_ch67_z {
629 groups = "i2sout_ch67_z";
630 function = "i2s_out";
634 spdif_out_h_pins: spdif_out_ao_h {
636 groups = "spdif_out_h";
637 function = "spdif_out";
643 compatible = "mdio-mux-mmioreg", "mdio-mux";
644 #address-cells = <1>;
646 reg = <0x0 0x55c 0x0 0x4>;
647 mux-mask = <0xffffffff>;
648 mdio-parent-bus = <&mdio0>;
650 internal_mdio: mdio@e40908ff {
652 #address-cells = <1>;
655 internal_phy: ethernet-phy@8 {
656 compatible = "ethernet-phy-id0181.4400", "ethernet-phy-ieee802.3-c22";
657 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
663 external_mdio: mdio@2009087f {
665 #address-cells = <1>;
672 resets = <&reset RESET_VIU>,
674 <&reset RESET_VCBUS>,
675 <&reset RESET_BT656>,
676 <&reset RESET_DVIN_RESET>,
678 <&reset RESET_VENCI>,
679 <&reset RESET_VENCP>,
682 <&reset RESET_VENCL>,
683 <&reset RESET_VID_LOCK>;
684 clocks = <&clkc CLKID_VPU>,
686 clock-names = "vpu", "vapb";
688 * VPU clocking is provided by two identical clock paths
689 * VPU_0 and VPU_1 muxed to a single clock by a glitch
690 * free mux to safely change frequency while running.
691 * Same for VAPB but with a final gate after the glitch free mux.
693 assigned-clocks = <&clkc CLKID_VPU_0_SEL>,
695 <&clkc CLKID_VPU>, /* Glitch free mux */
696 <&clkc CLKID_VAPB_0_SEL>,
697 <&clkc CLKID_VAPB_0>,
698 <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
699 assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
700 <0>, /* Do Nothing */
702 <&clkc CLKID_FCLK_DIV4>,
703 <0>, /* Do Nothing */
704 <&clkc CLKID_VAPB_0>;
705 assigned-clock-rates = <0>, /* Do Nothing */
707 <0>, /* Do Nothing */
708 <0>, /* Do Nothing */
710 <0>; /* Do Nothing */
714 compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc";
716 <&clkc CLKID_SAR_ADC>,
717 <&clkc CLKID_SAR_ADC_CLK>,
718 <&clkc CLKID_SAR_ADC_SEL>;
719 clock-names = "clkin", "core", "adc_clk", "adc_sel";
723 clocks = <&clkc CLKID_SD_EMMC_A>,
724 <&clkc CLKID_SD_EMMC_A_CLK0>,
725 <&clkc CLKID_FCLK_DIV2>;
726 clock-names = "core", "clkin0", "clkin1";
727 resets = <&reset RESET_SD_EMMC_A>;
731 clocks = <&clkc CLKID_SD_EMMC_B>,
732 <&clkc CLKID_SD_EMMC_B_CLK0>,
733 <&clkc CLKID_FCLK_DIV2>;
734 clock-names = "core", "clkin0", "clkin1";
735 resets = <&reset RESET_SD_EMMC_B>;
739 clocks = <&clkc CLKID_SD_EMMC_C>,
740 <&clkc CLKID_SD_EMMC_C_CLK0>,
741 <&clkc CLKID_FCLK_DIV2>;
742 clock-names = "core", "clkin0", "clkin1";
743 resets = <&reset RESET_SD_EMMC_C>;
747 clocks = <&clkc CLKID_SPICC>;
748 clock-names = "core";
749 resets = <&reset RESET_PERIPHS_SPICC>;
754 clocks = <&clkc CLKID_SPI>;
758 clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
759 clock-names = "xtal", "pclk", "baud";
763 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>;
764 clock-names = "xtal", "pclk", "baud";
768 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>;
769 clock-names = "xtal", "pclk", "baud";
773 clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
774 clock-names = "xtal", "pclk", "baud";
778 clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>;
779 clock-names = "xtal", "pclk", "baud";
783 compatible = "amlogic,meson-gxl-vpu", "amlogic,meson-gx-vpu";
784 power-domains = <&pwrc_vpu>;