arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Device Tree Include file for NXP Layerscape-1088A family SoC.
   4  *
   5  * Copyright 2017 NXP
   6  *
   7  * Harninder Rai <harninder.rai@nxp.com>
   8  *
   9  */
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11 #include <dt-bindings/thermal/thermal.h>
  12
  13 / {
  14         compatible = "fsl,ls1088a";
  15         interrupt-parent = <&gic>;
  16         #address-cells = <2>;
  17         #size-cells = <2>;
  18
  19         aliases {
  20                 crypto = &crypto;
  21         };
  22
  23         cpus {
  24                 #address-cells = <1>;
  25                 #size-cells = <0>;
  26
  27                 /* We have 2 clusters having 4 Cortex-A53 cores each */
  28                 cpu0: cpu@0 {
  29                         device_type = "cpu";
  30                         compatible = "arm,cortex-a53";
  31                         reg = <0x0>;
  32                         clocks = <&clockgen 1 0>;
  33                         cpu-idle-states = <&CPU_PH20>;
  34                         #cooling-cells = <2>;
  35                 };
  36
  37                 cpu1: cpu@1 {
  38                         device_type = "cpu";
  39                         compatible = "arm,cortex-a53";
  40                         reg = <0x1>;
  41                         clocks = <&clockgen 1 0>;
  42                         cpu-idle-states = <&CPU_PH20>;
  43                         #cooling-cells = <2>;
  44                 };
  45
  46                 cpu2: cpu@2 {
  47                         device_type = "cpu";
  48                         compatible = "arm,cortex-a53";
  49                         reg = <0x2>;
  50                         clocks = <&clockgen 1 0>;
  51                         cpu-idle-states = <&CPU_PH20>;
  52                         #cooling-cells = <2>;
  53                 };
  54
  55                 cpu3: cpu@3 {
  56                         device_type = "cpu";
  57                         compatible = "arm,cortex-a53";
  58                         reg = <0x3>;
  59                         clocks = <&clockgen 1 0>;
  60                         cpu-idle-states = <&CPU_PH20>;
  61                         #cooling-cells = <2>;
  62                 };
  63
  64                 cpu4: cpu@100 {
  65                         device_type = "cpu";
  66                         compatible = "arm,cortex-a53";
  67                         reg = <0x100>;
  68                         clocks = <&clockgen 1 1>;
  69                         cpu-idle-states = <&CPU_PH20>;
  70                         #cooling-cells = <2>;
  71                 };
  72
  73                 cpu5: cpu@101 {
  74                         device_type = "cpu";
  75                         compatible = "arm,cortex-a53";
  76                         reg = <0x101>;
  77                         clocks = <&clockgen 1 1>;
  78                         cpu-idle-states = <&CPU_PH20>;
  79                         #cooling-cells = <2>;
  80                 };
  81
  82                 cpu6: cpu@102 {
  83                         device_type = "cpu";
  84                         compatible = "arm,cortex-a53";
  85                         reg = <0x102>;
  86                         clocks = <&clockgen 1 1>;
  87                         cpu-idle-states = <&CPU_PH20>;
  88                         #cooling-cells = <2>;
  89                 };
  90
  91                 cpu7: cpu@103 {
  92                         device_type = "cpu";
  93                         compatible = "arm,cortex-a53";
  94                         reg = <0x103>;
  95                         clocks = <&clockgen 1 1>;
  96                         cpu-idle-states = <&CPU_PH20>;
  97                         #cooling-cells = <2>;
  98                 };
  99
 100                 CPU_PH20: cpu-ph20 {
 101                         compatible = "arm,idle-state";
 102                         idle-state-name = "PH20";
 103                         arm,psci-suspend-param = <0x0>;
 104                         entry-latency-us = <1000>;
 105                         exit-latency-us = <1000>;
 106                         min-residency-us = <3000>;
 107                 };
 108         };
 109
 110         gic: interrupt-controller@6000000 {
 111                 compatible = "arm,gic-v3";
 112                 #interrupt-cells = <3>;
 113                 interrupt-controller;
 114                 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
 115                       <0x0 0x06100000 0 0x100000>, /* GICR(RD_base+SGI_base)*/
 116                       <0x0 0x0c0c0000 0 0x2000>, /* GICC */
 117                       <0x0 0x0c0d0000 0 0x1000>, /* GICH */
 118                       <0x0 0x0c0e0000 0 0x20000>; /* GICV */
 119                 interrupts = <1 9 IRQ_TYPE_LEVEL_HIGH>;
 120                 #address-cells = <2>;
 121                 #size-cells = <2>;
 122                 ranges;
 123
 124                 its: gic-its@6020000 {
 125                         compatible = "arm,gic-v3-its";
 126                         msi-controller;
 127                         reg = <0x0 0x6020000 0 0x20000>;
 128                 };
 129         };
 130
 131         thermal-zones {
 132                 cpu_thermal: cpu-thermal {
 133                         polling-delay-passive = <1000>;
 134                         polling-delay = <5000>;
 135                         thermal-sensors = <&tmu 0>;
 136
 137                         trips {
 138                                 cpu_alert: cpu-alert {
 139                                         temperature = <85000>;
 140                                         hysteresis = <2000>;
 141                                         type = "passive";
 142                                 };
 143
 144                                 cpu_crit: cpu-crit {
 145                                         temperature = <95000>;
 146                                         hysteresis = <2000>;
 147                                         type = "critical";
 148                                 };
 149                         };
 150
 151                         cooling-maps {
 152                                 map0 {
 153                                         trip = <&cpu_alert>;
 154                                         cooling-device =
 155                                                 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 156                                                 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 157                                                 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 158                                                 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 159                                                 <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 160                                                 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 161                                                 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 162                                                 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 163                                 };
 164                         };
 165                 };
 166         };
 167
 168         timer {
 169                 compatible = "arm,armv8-timer";
 170                 interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */
 171                              <1 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */
 172                              <1 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */
 173                              <1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */
 174         };
 175
 176         fsl_mc: fsl-mc@80c000000 {
 177                 compatible = "fsl,qoriq-mc";
 178                 reg = <0x00000008 0x0c000000 0 0x40>,    /* MC portal base */
 179                       <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
 180                 msi-parent = <&its>;
 181                 #address-cells = <3>;
 182                 #size-cells = <1>;
 183
 184                 /*
 185                  * Region type 0x0 - MC portals
 186                  * Region type 0x1 - QBMAN portals
 187                  */
 188                 ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
 189                           0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
 190
 191                 dpmacs {
 192                         #address-cells = <1>;
 193                         #size-cells = <0>;
 194
 195                         dpmac1: dpmac@1 {
 196                                 compatible = "fsl,qoriq-mc-dpmac";
 197                                 reg = <1>;
 198                         };
 199
 200                         dpmac2: dpmac@2 {
 201                                 compatible = "fsl,qoriq-mc-dpmac";
 202                                 reg = <2>;
 203                         };
 204
 205                         dpmac3: dpmac@3 {
 206                                 compatible = "fsl,qoriq-mc-dpmac";
 207                                 reg = <3>;
 208                         };
 209
 210                         dpmac4: dpmac@4 {
 211                                 compatible = "fsl,qoriq-mc-dpmac";
 212                                 reg = <4>;
 213                         };
 214
 215                         dpmac5: dpmac@5 {
 216                                 compatible = "fsl,qoriq-mc-dpmac";
 217                                 reg = <5>;
 218                         };
 219
 220                         dpmac6: dpmac@6 {
 221                                 compatible = "fsl,qoriq-mc-dpmac";
 222                                 reg = <6>;
 223                         };
 224
 225                         dpmac7: dpmac@7 {
 226                                 compatible = "fsl,qoriq-mc-dpmac";
 227                                 reg = <7>;
 228                         };
 229
 230                         dpmac8: dpmac@8 {
 231                                 compatible = "fsl,qoriq-mc-dpmac";
 232                                 reg = <8>;
 233                         };
 234
 235                         dpmac9: dpmac@9 {
 236                                 compatible = "fsl,qoriq-mc-dpmac";
 237                                 reg = <9>;
 238                         };
 239
 240                         dpmac10: dpmac@a {
 241                                 compatible = "fsl,qoriq-mc-dpmac";
 242                                 reg = <0xa>;
 243                         };
 244                 };
 245         };
 246
 247         psci {
 248                 compatible = "arm,psci-0.2";
 249                 method = "smc";
 250         };
 251
 252         sysclk: sysclk {
 253                 compatible = "fixed-clock";
 254                 #clock-cells = <0>;
 255                 clock-frequency = <100000000>;
 256                 clock-output-names = "sysclk";
 257         };
 258
 259         soc {
 260                 compatible = "simple-bus";
 261                 #address-cells = <2>;
 262                 #size-cells = <2>;
 263                 ranges;
 264
 265                 clockgen: clocking@1300000 {
 266                         compatible = "fsl,ls1088a-clockgen";
 267                         reg = <0 0x1300000 0 0xa0000>;
 268                         #clock-cells = <2>;
 269                         clocks = <&sysclk>;
 270                 };
 271
 272                 dcfg: dcfg@1e00000 {
 273                         compatible = "fsl,ls1088a-dcfg", "syscon";
 274                         reg = <0x0 0x1e00000 0x0 0x10000>;
 275                         little-endian;
 276                 };
 277
 278                 tmu: tmu@1f80000 {
 279                         compatible = "fsl,qoriq-tmu";
 280                         reg = <0x0 0x1f80000 0x0 0x10000>;
 281                         interrupts = <0 23 0x4>;
 282                         fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
 283                         fsl,tmu-calibration =
 284                                 /* Calibration data group 1 */
 285                                 <0x00000000 0x00000026
 286                                 0x00000001 0x0000002d
 287                                 0x00000002 0x00000032
 288                                 0x00000003 0x00000039
 289                                 0x00000004 0x0000003f
 290                                 0x00000005 0x00000046
 291                                 0x00000006 0x0000004d
 292                                 0x00000007 0x00000054
 293                                 0x00000008 0x0000005a
 294                                 0x00000009 0x00000061
 295                                 0x0000000a 0x0000006a
 296                                 0x0000000b 0x00000071
 297                                 /* Calibration data group 2 */
 298                                 0x00010000 0x00000025
 299                                 0x00010001 0x0000002c
 300                                 0x00010002 0x00000035
 301                                 0x00010003 0x0000003d
 302                                 0x00010004 0x00000045
 303                                 0x00010005 0x0000004e
 304                                 0x00010006 0x00000057
 305                                 0x00010007 0x00000061
 306                                 0x00010008 0x0000006b
 307                                 0x00010009 0x00000076
 308                                 /* Calibration data group 3 */
 309                                 0x00020000 0x00000029
 310                                 0x00020001 0x00000033
 311                                 0x00020002 0x0000003d
 312                                 0x00020003 0x00000049
 313                                 0x00020004 0x00000056
 314                                 0x00020005 0x00000061
 315                                 0x00020006 0x0000006d
 316                                 /* Calibration data group 4 */
 317                                 0x00030000 0x00000021
 318                                 0x00030001 0x0000002a
 319                                 0x00030002 0x0000003c
 320                                 0x00030003 0x0000004e>;
 321                         little-endian;
 322                         #thermal-sensor-cells = <1>;
 323                 };
 324
 325                 duart0: serial@21c0500 {
 326                         compatible = "fsl,ns16550", "ns16550a";
 327                         reg = <0x0 0x21c0500 0x0 0x100>;
 328                         clocks = <&clockgen 4 3>;
 329                         interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
 330                         status = "disabled";
 331                 };
 332
 333                 duart1: serial@21c0600 {
 334                         compatible = "fsl,ns16550", "ns16550a";
 335                         reg = <0x0 0x21c0600 0x0 0x100>;
 336                         clocks = <&clockgen 4 3>;
 337                         interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
 338                         status = "disabled";
 339                 };
 340
 341                 gpio0: gpio@2300000 {
 342                         compatible = "fsl,qoriq-gpio";
 343                         reg = <0x0 0x2300000 0x0 0x10000>;
 344                         interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
 345                         gpio-controller;
 346                         #gpio-cells = <2>;
 347                         interrupt-controller;
 348                         #interrupt-cells = <2>;
 349                 };
 350
 351                 gpio1: gpio@2310000 {
 352                         compatible = "fsl,qoriq-gpio";
 353                         reg = <0x0 0x2310000 0x0 0x10000>;
 354                         interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
 355                         gpio-controller;
 356                         #gpio-cells = <2>;
 357                         interrupt-controller;
 358                         #interrupt-cells = <2>;
 359                 };
 360
 361                 gpio2: gpio@2320000 {
 362                         compatible = "fsl,qoriq-gpio";
 363                         reg = <0x0 0x2320000 0x0 0x10000>;
 364                         interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
 365                         gpio-controller;
 366                         #gpio-cells = <2>;
 367                         interrupt-controller;
 368                         #interrupt-cells = <2>;
 369                 };
 370
 371                 gpio3: gpio@2330000 {
 372                         compatible = "fsl,qoriq-gpio";
 373                         reg = <0x0 0x2330000 0x0 0x10000>;
 374                         interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
 375                         gpio-controller;
 376                         #gpio-cells = <2>;
 377                         interrupt-controller;
 378                         #interrupt-cells = <2>;
 379                 };
 380
 381                 ifc: ifc@2240000 {
 382                         compatible = "fsl,ifc", "simple-bus";
 383                         reg = <0x0 0x2240000 0x0 0x20000>;
 384                         interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
 385                         little-endian;
 386                         #address-cells = <2>;
 387                         #size-cells = <1>;
 388                         status = "disabled";
 389                 };
 390
 391                 i2c0: i2c@2000000 {
 392                         compatible = "fsl,vf610-i2c";
 393                         #address-cells = <1>;
 394                         #size-cells = <0>;
 395                         reg = <0x0 0x2000000 0x0 0x10000>;
 396                         interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
 397                         clocks = <&clockgen 4 3>;
 398                         status = "disabled";
 399                 };
 400
 401                 i2c1: i2c@2010000 {
 402                         compatible = "fsl,vf610-i2c";
 403                         #address-cells = <1>;
 404                         #size-cells = <0>;
 405                         reg = <0x0 0x2010000 0x0 0x10000>;
 406                         interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
 407                         clocks = <&clockgen 4 3>;
 408                         status = "disabled";
 409                 };
 410
 411                 i2c2: i2c@2020000 {
 412                         compatible = "fsl,vf610-i2c";
 413                         #address-cells = <1>;
 414                         #size-cells = <0>;
 415                         reg = <0x0 0x2020000 0x0 0x10000>;
 416                         interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
 417                         clocks = <&clockgen 4 3>;
 418                         status = "disabled";
 419                 };
 420
 421                 i2c3: i2c@2030000 {
 422                         compatible = "fsl,vf610-i2c";
 423                         #address-cells = <1>;
 424                         #size-cells = <0>;
 425                         reg = <0x0 0x2030000 0x0 0x10000>;
 426                         interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
 427                         clocks = <&clockgen 4 3>;
 428                         status = "disabled";
 429                 };
 430
 431                 esdhc: esdhc@2140000 {
 432                         compatible = "fsl,ls1088a-esdhc", "fsl,esdhc";
 433                         reg = <0x0 0x2140000 0x0 0x10000>;
 434                         interrupts = <0 28 0x4>; /* Level high type */
 435                         clock-frequency = <0>;
 436                         voltage-ranges = <1800 1800 3300 3300>;
 437                         sdhci,auto-cmd12;
 438                         little-endian;
 439                         bus-width = <4>;
 440                         status = "disabled";
 441                 };
 442
 443                 usb0: usb3@3100000 {
 444                         compatible = "snps,dwc3";
 445                         reg = <0x0 0x3100000 0x0 0x10000>;
 446                         interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
 447                         dr_mode = "host";
 448                         snps,quirk-frame-length-adjustment = <0x20>;
 449                         snps,dis_rxdet_inp3_quirk;
 450                         status = "disabled";
 451                 };
 452
 453                 usb1: usb3@3110000 {
 454                         compatible = "snps,dwc3";
 455                         reg = <0x0 0x3110000 0x0 0x10000>;
 456                         interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
 457                         dr_mode = "host";
 458                         snps,quirk-frame-length-adjustment = <0x20>;
 459                         snps,dis_rxdet_inp3_quirk;
 460                         status = "disabled";
 461                 };
 462
 463                 sata: sata@3200000 {
 464                         compatible = "fsl,ls1088a-ahci";
 465                         reg = <0x0 0x3200000 0x0 0x10000>,
 466                                 <0x7 0x100520 0x0 0x4>;
 467                         reg-names = "ahci", "sata-ecc";
 468                         interrupts = <0 133 IRQ_TYPE_LEVEL_HIGH>;
 469                         clocks = <&clockgen 4 3>;
 470                         dma-coherent;
 471                         status = "disabled";
 472                 };
 473
 474                 crypto: crypto@8000000 {
 475                         compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
 476                         fsl,sec-era = <8>;
 477                         #address-cells = <1>;
 478                         #size-cells = <1>;
 479                         ranges = <0x0 0x00 0x8000000 0x100000>;
 480                         reg = <0x00 0x8000000 0x0 0x100000>;
 481                         interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
 482                         dma-coherent;
 483
 484                         sec_jr0: jr@10000 {
 485                                 compatible = "fsl,sec-v5.0-job-ring",
 486                                              "fsl,sec-v4.0-job-ring";
 487                                 reg        = <0x10000 0x10000>;
 488                                 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
 489                         };
 490
 491                         sec_jr1: jr@20000 {
 492                                 compatible = "fsl,sec-v5.0-job-ring",
 493                                              "fsl,sec-v4.0-job-ring";
 494                                 reg        = <0x20000 0x10000>;
 495                                 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
 496                         };
 497
 498                         sec_jr2: jr@30000 {
 499                                 compatible = "fsl,sec-v5.0-job-ring",
 500                                              "fsl,sec-v4.0-job-ring";
 501                                 reg        = <0x30000 0x10000>;
 502                                 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
 503                         };
 504
 505                         sec_jr3: jr@40000 {
 506                                 compatible = "fsl,sec-v5.0-job-ring",
 507                                              "fsl,sec-v4.0-job-ring";
 508                                 reg        = <0x40000 0x10000>;
 509                                 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 510                         };
 511                 };
 512
 513                 pcie@3400000 {
 514                         compatible = "fsl,ls1088a-pcie";
 515                         reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */
 516                                0x20 0x00000000 0x0 0x00002000>; /* configuration space */
 517                         reg-names = "regs", "config";
 518                         interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
 519                         interrupt-names = "aer";
 520                         #address-cells = <3>;
 521                         #size-cells = <2>;
 522                         device_type = "pci";
 523                         dma-coherent;
 524                         num-lanes = <4>;
 525                         bus-range = <0x0 0xff>;
 526                         ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000   /* downstream I/O */
 527                                   0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 528                         msi-parent = <&its>;
 529                         #interrupt-cells = <1>;
 530                         interrupt-map-mask = <0 0 0 7>;
 531                         interrupt-map = <0000 0 0 1 &gic 0 0 0 109 IRQ_TYPE_LEVEL_HIGH>,
 532                                         <0000 0 0 2 &gic 0 0 0 110 IRQ_TYPE_LEVEL_HIGH>,
 533                                         <0000 0 0 3 &gic 0 0 0 111 IRQ_TYPE_LEVEL_HIGH>,
 534                                         <0000 0 0 4 &gic 0 0 0 112 IRQ_TYPE_LEVEL_HIGH>;
 535                         status = "disabled";
 536                 };
 537
 538                 pcie@3500000 {
 539                         compatible = "fsl,ls1088a-pcie";
 540                         reg = <0x00 0x03500000 0x0 0x00100000   /* controller registers */
 541                                0x28 0x00000000 0x0 0x00002000>; /* configuration space */
 542                         reg-names = "regs", "config";
 543                         interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
 544                         interrupt-names = "aer";
 545                         #address-cells = <3>;
 546                         #size-cells = <2>;
 547                         device_type = "pci";
 548                         dma-coherent;
 549                         num-lanes = <4>;
 550                         bus-range = <0x0 0xff>;
 551                         ranges = <0x81000000 0x0 0x00000000 0x28 0x00010000 0x0 0x00010000   /* downstream I/O */
 552                                   0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 553                         msi-parent = <&its>;
 554                         #interrupt-cells = <1>;
 555                         interrupt-map-mask = <0 0 0 7>;
 556                         interrupt-map = <0000 0 0 1 &gic 0 0 0 114 IRQ_TYPE_LEVEL_HIGH>,
 557                                         <0000 0 0 2 &gic 0 0 0 115 IRQ_TYPE_LEVEL_HIGH>,
 558                                         <0000 0 0 3 &gic 0 0 0 116 IRQ_TYPE_LEVEL_HIGH>,
 559                                         <0000 0 0 4 &gic 0 0 0 117 IRQ_TYPE_LEVEL_HIGH>;
 560                         status = "disabled";
 561                 };
 562
 563                 pcie@3600000 {
 564                         compatible = "fsl,ls1088a-pcie";
 565                         reg = <0x00 0x03600000 0x0 0x00100000   /* controller registers */
 566                                0x30 0x00000000 0x0 0x00002000>; /* configuration space */
 567                         reg-names = "regs", "config";
 568                         interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
 569                         interrupt-names = "aer";
 570                         #address-cells = <3>;
 571                         #size-cells = <2>;
 572                         device_type = "pci";
 573                         dma-coherent;
 574                         num-lanes = <8>;
 575                         bus-range = <0x0 0xff>;
 576                         ranges = <0x81000000 0x0 0x00000000 0x30 0x00010000 0x0 0x00010000   /* downstream I/O */
 577                                   0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 578                         msi-parent = <&its>;
 579                         #interrupt-cells = <1>;
 580                         interrupt-map-mask = <0 0 0 7>;
 581                         interrupt-map = <0000 0 0 1 &gic 0 0 0 119 IRQ_TYPE_LEVEL_HIGH>,
 582                                         <0000 0 0 2 &gic 0 0 0 120 IRQ_TYPE_LEVEL_HIGH>,
 583                                         <0000 0 0 3 &gic 0 0 0 121 IRQ_TYPE_LEVEL_HIGH>,
 584                                         <0000 0 0 4 &gic 0 0 0 122 IRQ_TYPE_LEVEL_HIGH>;
 585                         status = "disabled";
 586                 };
 587
 588                 cluster1_core0_watchdog: wdt@c000000 {
 589                         compatible = "arm,sp805-wdt", "arm,primecell";
 590                         reg = <0x0 0xc000000 0x0 0x1000>;
 591                         clocks = <&clockgen 4 3>, <&clockgen 4 3>;
 592                         clock-names = "apb_pclk", "wdog_clk";
 593                 };
 594
 595                 cluster1_core1_watchdog: wdt@c010000 {
 596                         compatible = "arm,sp805-wdt", "arm,primecell";
 597                         reg = <0x0 0xc010000 0x0 0x1000>;
 598                         clocks = <&clockgen 4 3>, <&clockgen 4 3>;
 599                         clock-names = "apb_pclk", "wdog_clk";
 600                 };
 601
 602                 cluster1_core2_watchdog: wdt@c020000 {
 603                         compatible = "arm,sp805-wdt", "arm,primecell";
 604                         reg = <0x0 0xc020000 0x0 0x1000>;
 605                         clocks = <&clockgen 4 3>, <&clockgen 4 3>;
 606                         clock-names = "apb_pclk", "wdog_clk";
 607                 };
 608
 609                 cluster1_core3_watchdog: wdt@c030000 {
 610                         compatible = "arm,sp805-wdt", "arm,primecell";
 611                         reg = <0x0 0xc030000 0x0 0x1000>;
 612                         clocks = <&clockgen 4 3>, <&clockgen 4 3>;
 613                         clock-names = "apb_pclk", "wdog_clk";
 614                 };
 615
 616                 cluster2_core0_watchdog: wdt@c100000 {
 617                         compatible = "arm,sp805-wdt", "arm,primecell";
 618                         reg = <0x0 0xc100000 0x0 0x1000>;
 619                         clocks = <&clockgen 4 3>, <&clockgen 4 3>;
 620                         clock-names = "apb_pclk", "wdog_clk";
 621                 };
 622
 623                 cluster2_core1_watchdog: wdt@c110000 {
 624                         compatible = "arm,sp805-wdt", "arm,primecell";
 625                         reg = <0x0 0xc110000 0x0 0x1000>;
 626                         clocks = <&clockgen 4 3>, <&clockgen 4 3>;
 627                         clock-names = "apb_pclk", "wdog_clk";
 628                 };
 629
 630                 cluster2_core2_watchdog: wdt@c120000 {
 631                         compatible = "arm,sp805-wdt", "arm,primecell";
 632                         reg = <0x0 0xc120000 0x0 0x1000>;
 633                         clocks = <&clockgen 4 3>, <&clockgen 4 3>;
 634                         clock-names = "apb_pclk", "wdog_clk";
 635                 };
 636
 637                 cluster2_core3_watchdog: wdt@c130000 {
 638                         compatible = "arm,sp805-wdt", "arm,primecell";
 639                         reg = <0x0 0xc130000 0x0 0x1000>;
 640                         clocks = <&clockgen 4 3>, <&clockgen 4 3>;
 641                         clock-names = "apb_pclk", "wdog_clk";
 642                 };
 643         };
 644
 645         firmware {
 646                 optee {
 647                         compatible = "linaro,optee-tz";
 648                         method = "smc";
 649                 };
 650         };
 651
 652 };