arch/arm64/boot/dts/freescale/imx8mq.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright 2017 NXP
   4  * Copyright (C) 2017-2018 Pengutronix, Lucas Stach <kernel@pengutronix.de>
   5  */
   6
   7 #include <dt-bindings/clock/imx8mq-clock.h>
   8 #include <dt-bindings/power/imx8mq-power.h>
   9 #include <dt-bindings/reset/imx8mq-reset.h>
  10 #include <dt-bindings/gpio/gpio.h>
  11 #include "dt-bindings/input/input.h"
  12 #include <dt-bindings/interrupt-controller/arm-gic.h>
  13 #include <dt-bindings/thermal/thermal.h>
  14 #include "imx8mq-pinfunc.h"
  15
  16 / {
  17         interrupt-parent = <&gpc>;
  18
  19         #address-cells = <2>;
  20         #size-cells = <2>;
  21
  22         aliases {
  23                 gpio0 = &gpio1;
  24                 gpio1 = &gpio2;
  25                 gpio2 = &gpio3;
  26                 gpio3 = &gpio4;
  27                 gpio4 = &gpio5;
  28                 i2c0 = &i2c1;
  29                 i2c1 = &i2c2;
  30                 i2c2 = &i2c3;
  31                 i2c3 = &i2c4;
  32                 serial0 = &uart1;
  33                 serial1 = &uart2;
  34                 serial2 = &uart3;
  35                 serial3 = &uart4;
  36                 spi0 = &ecspi1;
  37                 spi1 = &ecspi2;
  38                 spi2 = &ecspi3;
  39         };
  40
  41         ckil: clock-ckil {
  42                 compatible = "fixed-clock";
  43                 #clock-cells = <0>;
  44                 clock-frequency = <32768>;
  45                 clock-output-names = "ckil";
  46         };
  47
  48         osc_25m: clock-osc-25m {
  49                 compatible = "fixed-clock";
  50                 #clock-cells = <0>;
  51                 clock-frequency = <25000000>;
  52                 clock-output-names = "osc_25m";
  53         };
  54
  55         osc_27m: clock-osc-27m {
  56                 compatible = "fixed-clock";
  57                 #clock-cells = <0>;
  58                 clock-frequency = <27000000>;
  59                 clock-output-names = "osc_27m";
  60         };
  61
  62         clk_ext1: clock-ext1 {
  63                 compatible = "fixed-clock";
  64                 #clock-cells = <0>;
  65                 clock-frequency = <133000000>;
  66                 clock-output-names = "clk_ext1";
  67         };
  68
  69         clk_ext2: clock-ext2 {
  70                 compatible = "fixed-clock";
  71                 #clock-cells = <0>;
  72                 clock-frequency = <133000000>;
  73                 clock-output-names = "clk_ext2";
  74         };
  75
  76         clk_ext3: clock-ext3 {
  77                 compatible = "fixed-clock";
  78                 #clock-cells = <0>;
  79                 clock-frequency = <133000000>;
  80                 clock-output-names = "clk_ext3";
  81         };
  82
  83         clk_ext4: clock-ext4 {
  84                 compatible = "fixed-clock";
  85                 #clock-cells = <0>;
  86                 clock-frequency= <133000000>;
  87                 clock-output-names = "clk_ext4";
  88         };
  89
  90         cpus {
  91                 #address-cells = <1>;
  92                 #size-cells = <0>;
  93
  94                 A53_0: cpu@0 {
  95                         device_type = "cpu";
  96                         compatible = "arm,cortex-a53";
  97                         reg = <0x0>;
  98                         clock-latency = <61036>; /* two CLK32 periods */
  99                         clocks = <&clk IMX8MQ_CLK_ARM>;
 100                         enable-method = "psci";
 101                         next-level-cache = <&A53_L2>;
 102                         operating-points-v2 = <&a53_opp_table>;
 103                         #cooling-cells = <2>;
 104                         nvmem-cells = <&cpu_speed_grade>;
 105                         nvmem-cell-names = "speed_grade";
 106                 };
 107
 108                 A53_1: cpu@1 {
 109                         device_type = "cpu";
 110                         compatible = "arm,cortex-a53";
 111                         reg = <0x1>;
 112                         clock-latency = <61036>; /* two CLK32 periods */
 113                         clocks = <&clk IMX8MQ_CLK_ARM>;
 114                         enable-method = "psci";
 115                         next-level-cache = <&A53_L2>;
 116                         operating-points-v2 = <&a53_opp_table>;
 117                         #cooling-cells = <2>;
 118                 };
 119
 120                 A53_2: cpu@2 {
 121                         device_type = "cpu";
 122                         compatible = "arm,cortex-a53";
 123                         reg = <0x2>;
 124                         clock-latency = <61036>; /* two CLK32 periods */
 125                         clocks = <&clk IMX8MQ_CLK_ARM>;
 126                         enable-method = "psci";
 127                         next-level-cache = <&A53_L2>;
 128                         operating-points-v2 = <&a53_opp_table>;
 129                         #cooling-cells = <2>;
 130                 };
 131
 132                 A53_3: cpu@3 {
 133                         device_type = "cpu";
 134                         compatible = "arm,cortex-a53";
 135                         reg = <0x3>;
 136                         clock-latency = <61036>; /* two CLK32 periods */
 137                         clocks = <&clk IMX8MQ_CLK_ARM>;
 138                         enable-method = "psci";
 139                         next-level-cache = <&A53_L2>;
 140                         operating-points-v2 = <&a53_opp_table>;
 141                         #cooling-cells = <2>;
 142                 };
 143
 144                 A53_L2: l2-cache0 {
 145                         compatible = "cache";
 146                 };
 147         };
 148
 149         a53_opp_table: opp-table {
 150                 compatible = "operating-points-v2";
 151                 opp-shared;
 152
 153                 opp-800000000 {
 154                         opp-hz = /bits/ 64 <800000000>;
 155                         opp-microvolt = <900000>;
 156                         /* Industrial only */
 157                         opp-supported-hw = <0xf>, <0x4>;
 158                         clock-latency-ns = <150000>;
 159                 };
 160
 161                 opp-1000000000 {
 162                         opp-hz = /bits/ 64 <1000000000>;
 163                         opp-microvolt = <900000>;
 164                         /* Consumer only */
 165                         opp-supported-hw = <0xe>, <0x3>;
 166                         clock-latency-ns = <150000>;
 167                 };
 168
 169                 opp-1300000000 {
 170                         opp-hz = /bits/ 64 <1300000000>;
 171                         opp-microvolt = <1000000>;
 172                         opp-supported-hw = <0xc>, <0x7>;
 173                         clock-latency-ns = <150000>;
 174                 };
 175
 176                 opp-1500000000 {
 177                         opp-hz = /bits/ 64 <1500000000>;
 178                         opp-microvolt = <1000000>;
 179                         /* Consumer only but rely on speed grading */
 180                         opp-supported-hw = <0x8>, <0x7>;
 181                         clock-latency-ns = <150000>;
 182                 };
 183         };
 184
 185         pmu {
 186                 compatible = "arm,cortex-a53-pmu";
 187                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
 188                 interrupt-parent = <&gic>;
 189                 interrupt-affinity = <&A53_0>, <&A53_1>, <&A53_2>, <&A53_3>;
 190         };
 191
 192         psci {
 193                 compatible = "arm,psci-1.0";
 194                 method = "smc";
 195         };
 196
 197         thermal-zones {
 198                 cpu-thermal {
 199                         polling-delay-passive = <250>;
 200                         polling-delay = <2000>;
 201                         thermal-sensors = <&tmu 0>;
 202
 203                         trips {
 204                                 cpu_alert: cpu-alert {
 205                                         temperature = <80000>;
 206                                         hysteresis = <2000>;
 207                                         type = "passive";
 208                                 };
 209
 210                                 cpu-crit {
 211                                         temperature = <90000>;
 212                                         hysteresis = <2000>;
 213                                         type = "critical";
 214                                 };
 215                         };
 216
 217                         cooling-maps {
 218                                 map0 {
 219                                         trip = <&cpu_alert>;
 220                                         cooling-device =
 221                                                 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 222                                                 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 223                                                 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 224                                                 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 225                                 };
 226                         };
 227                 };
 228
 229                 gpu-thermal {
 230                         polling-delay-passive = <250>;
 231                         polling-delay = <2000>;
 232                         thermal-sensors = <&tmu 1>;
 233
 234                         trips {
 235                                 gpu-crit {
 236                                         temperature = <90000>;
 237                                         hysteresis = <2000>;
 238                                         type = "critical";
 239                                 };
 240                         };
 241                 };
 242
 243                 vpu-thermal {
 244                         polling-delay-passive = <250>;
 245                         polling-delay = <2000>;
 246                         thermal-sensors = <&tmu 2>;
 247
 248                         trips {
 249                                 vpu-crit {
 250                                         temperature = <90000>;
 251                                         hysteresis = <2000>;
 252                                         type = "critical";
 253                                 };
 254                         };
 255                 };
 256         };
 257
 258         timer {
 259                 compatible = "arm,armv8-timer";
 260                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */
 261                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */
 262                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */
 263                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */
 264                 interrupt-parent = <&gic>;
 265                 arm,no-tick-in-suspend;
 266         };
 267
 268         soc@0 {
 269                 compatible = "simple-bus";
 270                 #address-cells = <1>;
 271                 #size-cells = <1>;
 272                 ranges = <0x0 0x0 0x0 0x3e000000>;
 273                 dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>;
 274
 275                 bus@30000000 { /* AIPS1 */
 276                         compatible = "fsl,imx8mq-aips-bus", "simple-bus";
 277                         #address-cells = <1>;
 278                         #size-cells = <1>;
 279                         ranges = <0x30000000 0x30000000 0x400000>;
 280
 281                         gpio1: gpio@30200000 {
 282                                 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
 283                                 reg = <0x30200000 0x10000>;
 284                                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
 285                                              <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 286                                 clocks = <&clk IMX8MQ_CLK_GPIO1_ROOT>;
 287                                 gpio-controller;
 288                                 #gpio-cells = <2>;
 289                                 interrupt-controller;
 290                                 #interrupt-cells = <2>;
 291                                 gpio-ranges = <&iomuxc 0 10 30>;
 292                         };
 293
 294                         gpio2: gpio@30210000 {
 295                                 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
 296                                 reg = <0x30210000 0x10000>;
 297                                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
 298                                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 299                                 clocks = <&clk IMX8MQ_CLK_GPIO2_ROOT>;
 300                                 gpio-controller;
 301                                 #gpio-cells = <2>;
 302                                 interrupt-controller;
 303                                 #interrupt-cells = <2>;
 304                                 gpio-ranges = <&iomuxc 0 40 21>;
 305                         };
 306
 307                         gpio3: gpio@30220000 {
 308                                 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
 309                                 reg = <0x30220000 0x10000>;
 310                                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
 311                                              <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 312                                 clocks = <&clk IMX8MQ_CLK_GPIO3_ROOT>;
 313                                 gpio-controller;
 314                                 #gpio-cells = <2>;
 315                                 interrupt-controller;
 316                                 #interrupt-cells = <2>;
 317                                 gpio-ranges = <&iomuxc 0 61 26>;
 318                         };
 319
 320                         gpio4: gpio@30230000 {
 321                                 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
 322                                 reg = <0x30230000 0x10000>;
 323                                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
 324                                              <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 325                                 clocks = <&clk IMX8MQ_CLK_GPIO4_ROOT>;
 326                                 gpio-controller;
 327                                 #gpio-cells = <2>;
 328                                 interrupt-controller;
 329                                 #interrupt-cells = <2>;
 330                                 gpio-ranges = <&iomuxc 0 87 32>;
 331                         };
 332
 333                         gpio5: gpio@30240000 {
 334                                 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
 335                                 reg = <0x30240000 0x10000>;
 336                                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
 337                                              <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 338                                 clocks = <&clk IMX8MQ_CLK_GPIO5_ROOT>;
 339                                 gpio-controller;
 340                                 #gpio-cells = <2>;
 341                                 interrupt-controller;
 342                                 #interrupt-cells = <2>;
 343                                 gpio-ranges = <&iomuxc 0 119 30>;
 344                         };
 345
 346                         tmu: tmu@30260000 {
 347                                 compatible = "fsl,imx8mq-tmu";
 348                                 reg = <0x30260000 0x10000>;
 349                                 interrupt = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
 350                                 little-endian;
 351                                 fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>;
 352                                 fsl,tmu-calibration = <0x00000000 0x00000023
 353                                                        0x00000001 0x00000029
 354                                                        0x00000002 0x0000002f
 355                                                        0x00000003 0x00000035
 356                                                        0x00000004 0x0000003d
 357                                                        0x00000005 0x00000043
 358                                                        0x00000006 0x0000004b
 359                                                        0x00000007 0x00000051
 360                                                        0x00000008 0x00000057
 361                                                        0x00000009 0x0000005f
 362                                                        0x0000000a 0x00000067
 363                                                        0x0000000b 0x0000006f
 364
 365                                                        0x00010000 0x0000001b
 366                                                        0x00010001 0x00000023
 367                                                        0x00010002 0x0000002b
 368                                                        0x00010003 0x00000033
 369                                                        0x00010004 0x0000003b
 370                                                        0x00010005 0x00000043
 371                                                        0x00010006 0x0000004b
 372                                                        0x00010007 0x00000055
 373                                                        0x00010008 0x0000005d
 374                                                        0x00010009 0x00000067
 375                                                        0x0001000a 0x00000070
 376
 377                                                        0x00020000 0x00000017
 378                                                        0x00020001 0x00000023
 379                                                        0x00020002 0x0000002d
 380                                                        0x00020003 0x00000037
 381                                                        0x00020004 0x00000041
 382                                                        0x00020005 0x0000004b
 383                                                        0x00020006 0x00000057
 384                                                        0x00020007 0x00000063
 385                                                        0x00020008 0x0000006f
 386
 387                                                        0x00030000 0x00000015
 388                                                        0x00030001 0x00000021
 389                                                        0x00030002 0x0000002d
 390                                                        0x00030003 0x00000039
 391                                                        0x00030004 0x00000045
 392                                                        0x00030005 0x00000053
 393                                                        0x00030006 0x0000005f
 394                                                        0x00030007 0x00000071>;
 395                                 #thermal-sensor-cells =  <1>;
 396                         };
 397
 398                         wdog1: watchdog@30280000 {
 399                                 compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
 400                                 reg = <0x30280000 0x10000>;
 401                                 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 402                                 clocks = <&clk IMX8MQ_CLK_WDOG1_ROOT>;
 403                                 status = "disabled";
 404                         };
 405
 406                         wdog2: watchdog@30290000 {
 407                                 compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
 408                                 reg = <0x30290000 0x10000>;
 409                                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 410                                 clocks = <&clk IMX8MQ_CLK_WDOG2_ROOT>;
 411                                 status = "disabled";
 412                         };
 413
 414                         wdog3: watchdog@302a0000 {
 415                                 compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
 416                                 reg = <0x302a0000 0x10000>;
 417                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 418                                 clocks = <&clk IMX8MQ_CLK_WDOG3_ROOT>;
 419                                 status = "disabled";
 420                         };
 421
 422                         sdma2: sdma@302c0000 {
 423                                 compatible = "fsl,imx8mq-sdma","fsl,imx7d-sdma";
 424                                 reg = <0x302c0000 0x10000>;
 425                                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 426                                 clocks = <&clk IMX8MQ_CLK_SDMA2_ROOT>,
 427                                          <&clk IMX8MQ_CLK_SDMA2_ROOT>;
 428                                 clock-names = "ipg", "ahb";
 429                                 #dma-cells = <3>;
 430                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
 431                         };
 432
 433                         iomuxc: iomuxc@30330000 {
 434                                 compatible = "fsl,imx8mq-iomuxc";
 435                                 reg = <0x30330000 0x10000>;
 436                         };
 437
 438                         iomuxc_gpr: syscon@30340000 {
 439                                 compatible = "fsl,imx8mq-iomuxc-gpr", "fsl,imx6q-iomuxc-gpr", "syscon";
 440                                 reg = <0x30340000 0x10000>;
 441                         };
 442
 443                         ocotp: ocotp-ctrl@30350000 {
 444                                 compatible = "fsl,imx8mq-ocotp", "syscon";
 445                                 reg = <0x30350000 0x10000>;
 446                                 clocks = <&clk IMX8MQ_CLK_OCOTP_ROOT>;
 447                                 #address-cells = <1>;
 448                                 #size-cells = <1>;
 449
 450                                 cpu_speed_grade: speed-grade@10 {
 451                                         reg = <0x10 4>;
 452                                 };
 453                         };
 454
 455                         anatop: syscon@30360000 {
 456                                 compatible = "fsl,imx8mq-anatop", "syscon";
 457                                 reg = <0x30360000 0x10000>;
 458                                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
 459                         };
 460
 461                         snvs: snvs@30370000 {
 462                                 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
 463                                 reg = <0x30370000 0x10000>;
 464
 465                                 snvs_rtc: snvs-rtc-lp{
 466                                         compatible = "fsl,sec-v4.0-mon-rtc-lp";
 467                                         regmap =<&snvs>;
 468                                         offset = <0x34>;
 469                                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
 470                                                 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 471                                         clocks = <&clk IMX8MQ_CLK_SNVS_ROOT>;
 472                                         clock-names = "snvs-rtc";
 473                                 };
 474
 475                                 snvs_pwrkey: snvs-powerkey {
 476                                         compatible = "fsl,sec-v4.0-pwrkey";
 477                                         regmap = <&snvs>;
 478                                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 479                                         linux,keycode = <KEY_POWER>;
 480                                         wakeup-source;
 481                                         status = "disabled";
 482                                 };
 483                         };
 484
 485                         clk: clock-controller@30380000 {
 486                                 compatible = "fsl,imx8mq-ccm";
 487                                 reg = <0x30380000 0x10000>;
 488                                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
 489                                              <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 490                                 #clock-cells = <1>;
 491                                 clocks = <&ckil>, <&osc_25m>, <&osc_27m>,
 492                                          <&clk_ext1>, <&clk_ext2>,
 493                                          <&clk_ext3>, <&clk_ext4>;
 494                                 clock-names = "ckil", "osc_25m", "osc_27m",
 495                                               "clk_ext1", "clk_ext2",
 496                                               "clk_ext3", "clk_ext4";
 497                         };
 498
 499                         src: reset-controller@30390000 {
 500                                 compatible = "fsl,imx8mq-src", "syscon";
 501                                 reg = <0x30390000 0x10000>;
 502                                 #reset-cells = <1>;
 503                         };
 504
 505                         gpc: gpc@303a0000 {
 506                                 compatible = "fsl,imx8mq-gpc";
 507                                 reg = <0x303a0000 0x10000>;
 508                                 interrupt-parent = <&gic>;
 509                                 interrupt-controller;
 510                                 #interrupt-cells = <3>;
 511
 512                                 pgc {
 513                                         #address-cells = <1>;
 514                                         #size-cells = <0>;
 515
 516                                         pgc_mipi: power-domain@0 {
 517                                                 #power-domain-cells = <0>;
 518                                                 reg = <IMX8M_POWER_DOMAIN_MIPI>;
 519                                         };
 520
 521                                         /*
 522                                          * As per comment in ATF source code:
 523                                          *
 524                                          * PCIE1 and PCIE2 share the
 525                                          * same reset signal, if we
 526                                          * power down PCIE2, PCIE1
 527                                          * will be held in reset too.
 528                                          *
 529                                          * So instead of creating two
 530                                          * separate power domains for
 531                                          * PCIE1 and PCIE2 we create a
 532                                          * link between both and use
 533                                          * it as a shared PCIE power
 534                                          * domain.
 535                                          */
 536                                         pgc_pcie: power-domain@1 {
 537                                                 #power-domain-cells = <0>;
 538                                                 reg = <IMX8M_POWER_DOMAIN_PCIE1>;
 539                                                 power-domains = <&pgc_pcie2>;
 540                                         };
 541
 542                                         pgc_otg1: power-domain@2 {
 543                                                 #power-domain-cells = <0>;
 544                                                 reg = <IMX8M_POWER_DOMAIN_USB_OTG1>;
 545                                         };
 546
 547                                         pgc_otg2: power-domain@3 {
 548                                                 #power-domain-cells = <0>;
 549                                                 reg = <IMX8M_POWER_DOMAIN_USB_OTG2>;
 550                                         };
 551
 552                                         pgc_ddr1: power-domain@4 {
 553                                                 #power-domain-cells = <0>;
 554                                                 reg = <IMX8M_POWER_DOMAIN_DDR1>;
 555                                         };
 556
 557                                         pgc_gpu: power-domain@5 {
 558                                                 #power-domain-cells = <0>;
 559                                                 reg = <IMX8M_POWER_DOMAIN_GPU>;
 560                                                 clocks = <&clk IMX8MQ_CLK_GPU_ROOT>,
 561                                                          <&clk IMX8MQ_CLK_GPU_SHADER_DIV>,
 562                                                          <&clk IMX8MQ_CLK_GPU_AXI>,
 563                                                          <&clk IMX8MQ_CLK_GPU_AHB>;
 564                                         };
 565
 566                                         pgc_vpu: power-domain@6 {
 567                                                 #power-domain-cells = <0>;
 568                                                 reg = <IMX8M_POWER_DOMAIN_VPU>;
 569                                         };
 570
 571                                         pgc_disp: power-domain@7 {
 572                                                 #power-domain-cells = <0>;
 573                                                 reg = <IMX8M_POWER_DOMAIN_DISP>;
 574                                         };
 575
 576                                         pgc_mipi_csi1: power-domain@8 {
 577                                                 #power-domain-cells = <0>;
 578                                                 reg = <IMX8M_POWER_DOMAIN_MIPI_CSI1>;
 579                                         };
 580
 581                                         pgc_mipi_csi2: power-domain@9 {
 582                                                 #power-domain-cells = <0>;
 583                                                 reg = <IMX8M_POWER_DOMAIN_MIPI_CSI2>;
 584                                         };
 585
 586                                         pgc_pcie2: power-domain@a {
 587                                                 #power-domain-cells = <0>;
 588                                                 reg = <IMX8M_POWER_DOMAIN_PCIE2>;
 589                                         };
 590                                 };
 591                         };
 592                 };
 593
 594                 bus@30400000 { /* AIPS2 */
 595                         compatible = "fsl,imx8mq-aips-bus", "simple-bus";
 596                         #address-cells = <1>;
 597                         #size-cells = <1>;
 598                         ranges = <0x30400000 0x30400000 0x400000>;
 599
 600                         pwm1: pwm@30660000 {
 601                                 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
 602                                 reg = <0x30660000 0x10000>;
 603                                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 604                                 clocks = <&clk IMX8MQ_CLK_PWM1_ROOT>,
 605                                          <&clk IMX8MQ_CLK_PWM1_ROOT>;
 606                                 clock-names = "ipg", "per";
 607                                 #pwm-cells = <2>;
 608                                 status = "disabled";
 609                         };
 610
 611                         pwm2: pwm@30670000 {
 612                                 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
 613                                 reg = <0x30670000 0x10000>;
 614                                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 615                                 clocks = <&clk IMX8MQ_CLK_PWM2_ROOT>,
 616                                          <&clk IMX8MQ_CLK_PWM2_ROOT>;
 617                                 clock-names = "ipg", "per";
 618                                 #pwm-cells = <2>;
 619                                 status = "disabled";
 620                         };
 621
 622                         pwm3: pwm@30680000 {
 623                                 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
 624                                 reg = <0x30680000 0x10000>;
 625                                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 626                                 clocks = <&clk IMX8MQ_CLK_PWM3_ROOT>,
 627                                          <&clk IMX8MQ_CLK_PWM3_ROOT>;
 628                                 clock-names = "ipg", "per";
 629                                 #pwm-cells = <2>;
 630                                 status = "disabled";
 631                         };
 632
 633                         pwm4: pwm@30690000 {
 634                                 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
 635                                 reg = <0x30690000 0x10000>;
 636                                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 637                                 clocks = <&clk IMX8MQ_CLK_PWM4_ROOT>,
 638                                          <&clk IMX8MQ_CLK_PWM4_ROOT>;
 639                                 clock-names = "ipg", "per";
 640                                 #pwm-cells = <2>;
 641                                 status = "disabled";
 642                         };
 643                 };
 644
 645                 bus@30800000 { /* AIPS3 */
 646                         compatible = "fsl,imx8mq-aips-bus", "simple-bus";
 647                         #address-cells = <1>;
 648                         #size-cells = <1>;
 649                         ranges = <0x30800000 0x30800000 0x400000>,
 650                                  <0x08000000 0x08000000 0x10000000>;
 651
 652                         ecspi1: spi@30820000 {
 653                                 #address-cells = <1>;
 654                                 #size-cells = <0>;
 655                                 compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi";
 656                                 reg = <0x30820000 0x10000>;
 657                                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 658                                 clocks = <&clk IMX8MQ_CLK_ECSPI1_ROOT>,
 659                                          <&clk IMX8MQ_CLK_ECSPI1_ROOT>;
 660                                 clock-names = "ipg", "per";
 661                                 status = "disabled";
 662                         };
 663
 664                         ecspi2: spi@30830000 {
 665                                 #address-cells = <1>;
 666                                 #size-cells = <0>;
 667                                 compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi";
 668                                 reg = <0x30830000 0x10000>;
 669                                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 670                                 clocks = <&clk IMX8MQ_CLK_ECSPI2_ROOT>,
 671                                          <&clk IMX8MQ_CLK_ECSPI2_ROOT>;
 672                                 clock-names = "ipg", "per";
 673                                 status = "disabled";
 674                         };
 675
 676                         ecspi3: spi@30840000 {
 677                                 #address-cells = <1>;
 678                                 #size-cells = <0>;
 679                                 compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi";
 680                                 reg = <0x30840000 0x10000>;
 681                                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 682                                 clocks = <&clk IMX8MQ_CLK_ECSPI3_ROOT>,
 683                                          <&clk IMX8MQ_CLK_ECSPI3_ROOT>;
 684                                 clock-names = "ipg", "per";
 685                                 status = "disabled";
 686                         };
 687
 688                         uart1: serial@30860000 {
 689                                 compatible = "fsl,imx8mq-uart",
 690                                              "fsl,imx6q-uart";
 691                                 reg = <0x30860000 0x10000>;
 692                                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 693                                 clocks = <&clk IMX8MQ_CLK_UART1_ROOT>,
 694                                          <&clk IMX8MQ_CLK_UART1_ROOT>;
 695                                 clock-names = "ipg", "per";
 696                                 status = "disabled";
 697                         };
 698
 699                         uart3: serial@30880000 {
 700                                 compatible = "fsl,imx8mq-uart",
 701                                              "fsl,imx6q-uart";
 702                                 reg = <0x30880000 0x10000>;
 703                                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 704                                 clocks = <&clk IMX8MQ_CLK_UART3_ROOT>,
 705                                          <&clk IMX8MQ_CLK_UART3_ROOT>;
 706                                 clock-names = "ipg", "per";
 707                                 status = "disabled";
 708                         };
 709
 710                         uart2: serial@30890000 {
 711                                 compatible = "fsl,imx8mq-uart",
 712                                              "fsl,imx6q-uart";
 713                                 reg = <0x30890000 0x10000>;
 714                                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 715                                 clocks = <&clk IMX8MQ_CLK_UART2_ROOT>,
 716                                          <&clk IMX8MQ_CLK_UART2_ROOT>;
 717                                 clock-names = "ipg", "per";
 718                                 status = "disabled";
 719                         };
 720
 721                         sai2: sai@308b0000 {
 722                                 #sound-dai-cells = <0>;
 723                                 compatible = "fsl,imx8mq-sai",
 724                                              "fsl,imx6sx-sai";
 725                                 reg = <0x308b0000 0x10000>;
 726                                 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 727                                 clocks = <&clk IMX8MQ_CLK_SAI2_IPG>,
 728                                          <&clk IMX8MQ_CLK_SAI2_ROOT>,
 729                                          <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>;
 730                                 clock-names = "bus", "mclk1", "mclk2", "mclk3";
 731                                 dmas = <&sdma1 10 24 0>, <&sdma1 11 24 0>;
 732                                 dma-names = "rx", "tx";
 733                                 status = "disabled";
 734                         };
 735
 736                         dphy: dphy@30a00300 {
 737                                 compatible = "fsl,imx8mq-mipi-dphy";
 738                                 reg = <0x30a00300 0x100>;
 739                                 clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>;
 740                                 clock-names = "phy_ref";
 741                                 assigned-clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>;
 742                                 assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>;
 743                                 assigned-clock-rates = <24000000>;
 744                                 #phy-cells = <0>;
 745                                 power-domains = <&pgc_mipi>;
 746                                 status = "disabled";
 747                         };
 748
 749                         i2c1: i2c@30a20000 {
 750                                 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
 751                                 reg = <0x30a20000 0x10000>;
 752                                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 753                                 clocks = <&clk IMX8MQ_CLK_I2C1_ROOT>;
 754                                 #address-cells = <1>;
 755                                 #size-cells = <0>;
 756                                 status = "disabled";
 757                         };
 758
 759                         i2c2: i2c@30a30000 {
 760                                 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
 761                                 reg = <0x30a30000 0x10000>;
 762                                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 763                                 clocks = <&clk IMX8MQ_CLK_I2C2_ROOT>;
 764                                 #address-cells = <1>;
 765                                 #size-cells = <0>;
 766                                 status = "disabled";
 767                         };
 768
 769                         i2c3: i2c@30a40000 {
 770                                 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
 771                                 reg = <0x30a40000 0x10000>;
 772                                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 773                                 clocks = <&clk IMX8MQ_CLK_I2C3_ROOT>;
 774                                 #address-cells = <1>;
 775                                 #size-cells = <0>;
 776                                 status = "disabled";
 777                         };
 778
 779                         i2c4: i2c@30a50000 {
 780                                 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
 781                                 reg = <0x30a50000 0x10000>;
 782                                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 783                                 clocks = <&clk IMX8MQ_CLK_I2C4_ROOT>;
 784                                 #address-cells = <1>;
 785                                 #size-cells = <0>;
 786                                 status = "disabled";
 787                         };
 788
 789                         uart4: serial@30a60000 {
 790                                 compatible = "fsl,imx8mq-uart",
 791                                              "fsl,imx6q-uart";
 792                                 reg = <0x30a60000 0x10000>;
 793                                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 794                                 clocks = <&clk IMX8MQ_CLK_UART4_ROOT>,
 795                                          <&clk IMX8MQ_CLK_UART4_ROOT>;
 796                                 clock-names = "ipg", "per";
 797                                 status = "disabled";
 798                         };
 799
 800                         usdhc1: mmc@30b40000 {
 801                                 compatible = "fsl,imx8mq-usdhc",
 802                                              "fsl,imx7d-usdhc";
 803                                 reg = <0x30b40000 0x10000>;
 804                                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 805                                 clocks = <&clk IMX8MQ_CLK_DUMMY>,
 806                                          <&clk IMX8MQ_CLK_NAND_USDHC_BUS>,
 807                                          <&clk IMX8MQ_CLK_USDHC1_ROOT>;
 808                                 clock-names = "ipg", "ahb", "per";
 809                                 assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>;
 810                                 assigned-clock-rates = <400000000>;
 811                                 fsl,tuning-start-tap = <20>;
 812                                 fsl,tuning-step = <2>;
 813                                 bus-width = <4>;
 814                                 status = "disabled";
 815                         };
 816
 817                         usdhc2: mmc@30b50000 {
 818                                 compatible = "fsl,imx8mq-usdhc",
 819                                              "fsl,imx7d-usdhc";
 820                                 reg = <0x30b50000 0x10000>;
 821                                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 822                                 clocks = <&clk IMX8MQ_CLK_DUMMY>,
 823                                          <&clk IMX8MQ_CLK_NAND_USDHC_BUS>,
 824                                          <&clk IMX8MQ_CLK_USDHC2_ROOT>;
 825                                 clock-names = "ipg", "ahb", "per";
 826                                 fsl,tuning-start-tap = <20>;
 827                                 fsl,tuning-step = <2>;
 828                                 bus-width = <4>;
 829                                 status = "disabled";
 830                         };
 831
 832                         qspi0: spi@30bb0000 {
 833                                 #address-cells = <1>;
 834                                 #size-cells = <0>;
 835                                 compatible = "fsl,imx8mq-qspi", "fsl,imx7d-qspi";
 836                                 reg = <0x30bb0000 0x10000>,
 837                                       <0x08000000 0x10000000>;
 838                                 reg-names = "QuadSPI", "QuadSPI-memory";
 839                                 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 840                                 clocks = <&clk IMX8MQ_CLK_QSPI_ROOT>,
 841                                          <&clk IMX8MQ_CLK_QSPI_ROOT>;
 842                                 clock-names = "qspi_en", "qspi";
 843                                 status = "disabled";
 844                         };
 845
 846                         sdma1: sdma@30bd0000 {
 847                                 compatible = "fsl,imx8mq-sdma","fsl,imx7d-sdma";
 848                                 reg = <0x30bd0000 0x10000>;
 849                                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 850                                 clocks = <&clk IMX8MQ_CLK_SDMA1_ROOT>,
 851                                          <&clk IMX8MQ_CLK_AHB>;
 852                                 clock-names = "ipg", "ahb";
 853                                 #dma-cells = <3>;
 854                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
 855                         };
 856
 857                         fec1: ethernet@30be0000 {
 858                                 compatible = "fsl,imx8mq-fec", "fsl,imx6sx-fec";
 859                                 reg = <0x30be0000 0x10000>;
 860                                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 861                                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
 862                                              <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 863                                 clocks = <&clk IMX8MQ_CLK_ENET1_ROOT>,
 864                                          <&clk IMX8MQ_CLK_ENET1_ROOT>,
 865                                          <&clk IMX8MQ_CLK_ENET_TIMER>,
 866                                          <&clk IMX8MQ_CLK_ENET_REF>,
 867                                          <&clk IMX8MQ_CLK_ENET_PHY_REF>;
 868                                 clock-names = "ipg", "ahb", "ptp",
 869                                               "enet_clk_ref", "enet_out";
 870                                 fsl,num-tx-queues = <3>;
 871                                 fsl,num-rx-queues = <3>;
 872                                 status = "disabled";
 873                         };
 874                 };
 875
 876                 bus@32c00000 { /* AIPS4 */
 877                         compatible = "fsl,imx8mq-aips-bus", "simple-bus";
 878                         #address-cells = <1>;
 879                         #size-cells = <1>;
 880                         ranges = <0x32c00000 0x32c00000 0x400000>;
 881
 882                         irqsteer: interrupt-controller@32e2d000 {
 883                                 compatible = "fsl,imx8m-irqsteer", "fsl,imx-irqsteer";
 884                                 reg = <0x32e2d000 0x1000>;
 885                                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 886                                 clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>;
 887                                 clock-names = "ipg";
 888                                 fsl,channel = <0>;
 889                                 fsl,num-irqs = <64>;
 890                                 interrupt-controller;
 891                                 #interrupt-cells = <1>;
 892                         };
 893                 };
 894
 895                 gpu: gpu@38000000 {
 896                         compatible = "vivante,gc";
 897                         reg = <0x38000000 0x40000>;
 898                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 899                         clocks = <&clk IMX8MQ_CLK_GPU_ROOT>,
 900                                  <&clk IMX8MQ_CLK_GPU_SHADER_DIV>,
 901                                  <&clk IMX8MQ_CLK_GPU_AXI>,
 902                                  <&clk IMX8MQ_CLK_GPU_AHB>;
 903                         clock-names = "core", "shader", "bus", "reg";
 904                         assigned-clocks = <&clk IMX8MQ_CLK_GPU_CORE_SRC>,
 905                                           <&clk IMX8MQ_CLK_GPU_SHADER_SRC>,
 906                                           <&clk IMX8MQ_CLK_GPU_AXI>,
 907                                           <&clk IMX8MQ_CLK_GPU_AHB>,
 908                                           <&clk IMX8MQ_GPU_PLL_BYPASS>;
 909                         assigned-clock-parents = <&clk IMX8MQ_GPU_PLL_OUT>,
 910                                                  <&clk IMX8MQ_GPU_PLL_OUT>,
 911                                                  <&clk IMX8MQ_GPU_PLL_OUT>,
 912                                                  <&clk IMX8MQ_GPU_PLL_OUT>,
 913                                                  <&clk IMX8MQ_GPU_PLL>;
 914                         assigned-clock-rates = <800000000>, <800000000>,
 915                                                <800000000>, <800000000>, <0>;
 916                         power-domains = <&pgc_gpu>;
 917                 };
 918
 919                 usb_dwc3_0: usb@38100000 {
 920                         compatible = "fsl,imx8mq-dwc3", "snps,dwc3";
 921                         reg = <0x38100000 0x10000>;
 922                         clocks = <&clk IMX8MQ_CLK_USB_BUS>,
 923                                  <&clk IMX8MQ_CLK_USB_CORE_REF>,
 924                                  <&clk IMX8MQ_CLK_USB1_CTRL_ROOT>;
 925                         clock-names = "bus_early", "ref", "suspend";
 926                         assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>,
 927                                           <&clk IMX8MQ_CLK_USB_CORE_REF>;
 928                         assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>,
 929                                                  <&clk IMX8MQ_SYS1_PLL_100M>;
 930                         assigned-clock-rates = <500000000>, <100000000>;
 931                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 932                         phys = <&usb3_phy0>, <&usb3_phy0>;
 933                         phy-names = "usb2-phy", "usb3-phy";
 934                         power-domains = <&pgc_otg1>;
 935                         usb3-resume-missing-cas;
 936                         status = "disabled";
 937                 };
 938
 939                 usb3_phy0: usb-phy@381f0040 {
 940                         compatible = "fsl,imx8mq-usb-phy";
 941                         reg = <0x381f0040 0x40>;
 942                         clocks = <&clk IMX8MQ_CLK_USB1_PHY_ROOT>;
 943                         clock-names = "phy";
 944                         assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF>;
 945                         assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>;
 946                         assigned-clock-rates = <100000000>;
 947                         #phy-cells = <0>;
 948                         status = "disabled";
 949                 };
 950
 951                 usb_dwc3_1: usb@38200000 {
 952                         compatible = "fsl,imx8mq-dwc3", "snps,dwc3";
 953                         reg = <0x38200000 0x10000>;
 954                         clocks = <&clk IMX8MQ_CLK_USB_BUS>,
 955                                  <&clk IMX8MQ_CLK_USB_CORE_REF>,
 956                                  <&clk IMX8MQ_CLK_USB2_CTRL_ROOT>;
 957                         clock-names = "bus_early", "ref", "suspend";
 958                         assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>,
 959                                           <&clk IMX8MQ_CLK_USB_CORE_REF>;
 960                         assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>,
 961                                                  <&clk IMX8MQ_SYS1_PLL_100M>;
 962                         assigned-clock-rates = <500000000>, <100000000>;
 963                         interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 964                         phys = <&usb3_phy1>, <&usb3_phy1>;
 965                         phy-names = "usb2-phy", "usb3-phy";
 966                         power-domains = <&pgc_otg2>;
 967                         usb3-resume-missing-cas;
 968                         status = "disabled";
 969                 };
 970
 971                 usb3_phy1: usb-phy@382f0040 {
 972                         compatible = "fsl,imx8mq-usb-phy";
 973                         reg = <0x382f0040 0x40>;
 974                         clocks = <&clk IMX8MQ_CLK_USB2_PHY_ROOT>;
 975                         clock-names = "phy";
 976                         assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF>;
 977                         assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>;
 978                         assigned-clock-rates = <100000000>;
 979                         #phy-cells = <0>;
 980                         status = "disabled";
 981                 };
 982
 983                 pcie0: pcie@33800000 {
 984                         compatible = "fsl,imx8mq-pcie";
 985                         reg = <0x33800000 0x400000>,
 986                               <0x1ff00000 0x80000>;
 987                         reg-names = "dbi", "config";
 988                         #address-cells = <3>;
 989                         #size-cells = <2>;
 990                         device_type = "pci";
 991                         bus-range = <0x00 0xff>;
 992                         ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000 /* downstream I/O 64KB */
 993                                   0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
 994                         num-lanes = <1>;
 995                         num-viewport = <4>;
 996                         interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
 997                         interrupt-names = "msi";
 998                         #interrupt-cells = <1>;
 999                         interrupt-map-mask = <0 0 0 0x7>;
1000                         interrupt-map = <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1001                                         <0 0 0 2 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
1002                                         <0 0 0 3 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1003                                         <0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
1004                         fsl,max-link-speed = <2>;
1005                         power-domains = <&pgc_pcie>;
1006                         resets = <&src IMX8MQ_RESET_PCIEPHY>,
1007                                  <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>,
1008                                  <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>;
1009                         reset-names = "pciephy", "apps", "turnoff";
1010                         status = "disabled";
1011                 };
1012
1013                 pcie1: pcie@33c00000 {
1014                         compatible = "fsl,imx8mq-pcie";
1015                         reg = <0x33c00000 0x400000>,
1016                               <0x27f00000 0x80000>;
1017                         reg-names = "dbi", "config";
1018                         #address-cells = <3>;
1019                         #size-cells = <2>;
1020                         device_type = "pci";
1021                         ranges =  <0x81000000 0 0x00000000 0x27f80000 0 0x00010000 /* downstream I/O 64KB */
1022                                    0x82000000 0 0x20000000 0x20000000 0 0x07f00000>; /* non-prefetchable memory */
1023                         num-lanes = <1>;
1024                         num-viewport = <4>;
1025                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
1026                         interrupt-names = "msi";
1027                         #interrupt-cells = <1>;
1028                         interrupt-map-mask = <0 0 0 0x7>;
1029                         interrupt-map = <0 0 0 1 &gic GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
1030                                         <0 0 0 2 &gic GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
1031                                         <0 0 0 3 &gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
1032                                         <0 0 0 4 &gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
1033                         fsl,max-link-speed = <2>;
1034                         power-domains = <&pgc_pcie>;
1035                         resets = <&src IMX8MQ_RESET_PCIEPHY2>,
1036                                  <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_EN>,
1037                                  <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF>;
1038                         reset-names = "pciephy", "apps", "turnoff";
1039                         status = "disabled";
1040                 };
1041
1042                 gic: interrupt-controller@38800000 {
1043                         compatible = "arm,gic-v3";
1044                         reg = <0x38800000 0x10000>,     /* GIC Dist */
1045                               <0x38880000 0xc0000>,     /* GICR */
1046                               <0x31000000 0x2000>,      /* GICC */
1047                               <0x31010000 0x2000>,      /* GICV */
1048                               <0x31020000 0x2000>;      /* GICH */
1049                         #interrupt-cells = <3>;
1050                         interrupt-controller;
1051                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
1052                         interrupt-parent = <&gic>;
1053                 };
1054
1055                 ddr-pmu@3d800000 {
1056                         compatible = "fsl,imx8mq-ddr-pmu", "fsl,imx8m-ddr-pmu";
1057                         reg = <0x3d800000 0x400000>;
1058                         interrupt-parent = <&gic>;
1059                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1060                 };
1061         };
1062 };