arch/arm64/boot/dts/freescale/imx8mq.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright 2017 NXP
   4  * Copyright (C) 2017-2018 Pengutronix, Lucas Stach <kernel@pengutronix.de>
   5  */
   6
   7 #include <dt-bindings/clock/imx8mq-clock.h>
   8 #include <dt-bindings/power/imx8mq-power.h>
   9 #include <dt-bindings/reset/imx8mq-reset.h>
  10 #include <dt-bindings/gpio/gpio.h>
  11 #include "dt-bindings/input/input.h"
  12 #include <dt-bindings/interrupt-controller/arm-gic.h>
  13 #include <dt-bindings/thermal/thermal.h>
  14 #include "imx8mq-pinfunc.h"
  15
  16 / {
  17         interrupt-parent = <&gpc>;
  18
  19         #address-cells = <2>;
  20         #size-cells = <2>;
  21
  22         aliases {
  23                 gpio0 = &gpio1;
  24                 gpio1 = &gpio2;
  25                 gpio2 = &gpio3;
  26                 gpio3 = &gpio4;
  27                 gpio4 = &gpio5;
  28                 i2c0 = &i2c1;
  29                 i2c1 = &i2c2;
  30                 i2c2 = &i2c3;
  31                 i2c3 = &i2c4;
  32                 serial0 = &uart1;
  33                 serial1 = &uart2;
  34                 serial2 = &uart3;
  35                 serial3 = &uart4;
  36                 spi0 = &ecspi1;
  37                 spi1 = &ecspi2;
  38                 spi2 = &ecspi3;
  39         };
  40
  41         ckil: clock-ckil {
  42                 compatible = "fixed-clock";
  43                 #clock-cells = <0>;
  44                 clock-frequency = <32768>;
  45                 clock-output-names = "ckil";
  46         };
  47
  48         osc_25m: clock-osc-25m {
  49                 compatible = "fixed-clock";
  50                 #clock-cells = <0>;
  51                 clock-frequency = <25000000>;
  52                 clock-output-names = "osc_25m";
  53         };
  54
  55         osc_27m: clock-osc-27m {
  56                 compatible = "fixed-clock";
  57                 #clock-cells = <0>;
  58                 clock-frequency = <27000000>;
  59                 clock-output-names = "osc_27m";
  60         };
  61
  62         clk_ext1: clock-ext1 {
  63                 compatible = "fixed-clock";
  64                 #clock-cells = <0>;
  65                 clock-frequency = <133000000>;
  66                 clock-output-names = "clk_ext1";
  67         };
  68
  69         clk_ext2: clock-ext2 {
  70                 compatible = "fixed-clock";
  71                 #clock-cells = <0>;
  72                 clock-frequency = <133000000>;
  73                 clock-output-names = "clk_ext2";
  74         };
  75
  76         clk_ext3: clock-ext3 {
  77                 compatible = "fixed-clock";
  78                 #clock-cells = <0>;
  79                 clock-frequency = <133000000>;
  80                 clock-output-names = "clk_ext3";
  81         };
  82
  83         clk_ext4: clock-ext4 {
  84                 compatible = "fixed-clock";
  85                 #clock-cells = <0>;
  86                 clock-frequency= <133000000>;
  87                 clock-output-names = "clk_ext4";
  88         };
  89
  90         cpus {
  91                 #address-cells = <1>;
  92                 #size-cells = <0>;
  93
  94                 A53_0: cpu@0 {
  95                         device_type = "cpu";
  96                         compatible = "arm,cortex-a53";
  97                         reg = <0x0>;
  98                         clock-latency = <61036>; /* two CLK32 periods */
  99                         clocks = <&clk IMX8MQ_CLK_ARM>;
 100                         enable-method = "psci";
 101                         next-level-cache = <&A53_L2>;
 102                         operating-points-v2 = <&a53_opp_table>;
 103                         #cooling-cells = <2>;
 104                         nvmem-cells = <&cpu_speed_grade>;
 105                         nvmem-cell-names = "speed_grade";
 106                 };
 107
 108                 A53_1: cpu@1 {
 109                         device_type = "cpu";
 110                         compatible = "arm,cortex-a53";
 111                         reg = <0x1>;
 112                         clock-latency = <61036>; /* two CLK32 periods */
 113                         clocks = <&clk IMX8MQ_CLK_ARM>;
 114                         enable-method = "psci";
 115                         next-level-cache = <&A53_L2>;
 116                         operating-points-v2 = <&a53_opp_table>;
 117                         #cooling-cells = <2>;
 118                 };
 119
 120                 A53_2: cpu@2 {
 121                         device_type = "cpu";
 122                         compatible = "arm,cortex-a53";
 123                         reg = <0x2>;
 124                         clock-latency = <61036>; /* two CLK32 periods */
 125                         clocks = <&clk IMX8MQ_CLK_ARM>;
 126                         enable-method = "psci";
 127                         next-level-cache = <&A53_L2>;
 128                         operating-points-v2 = <&a53_opp_table>;
 129                         #cooling-cells = <2>;
 130                 };
 131
 132                 A53_3: cpu@3 {
 133                         device_type = "cpu";
 134                         compatible = "arm,cortex-a53";
 135                         reg = <0x3>;
 136                         clock-latency = <61036>; /* two CLK32 periods */
 137                         clocks = <&clk IMX8MQ_CLK_ARM>;
 138                         enable-method = "psci";
 139                         next-level-cache = <&A53_L2>;
 140                         operating-points-v2 = <&a53_opp_table>;
 141                         #cooling-cells = <2>;
 142                 };
 143
 144                 A53_L2: l2-cache0 {
 145                         compatible = "cache";
 146                 };
 147         };
 148
 149         a53_opp_table: opp-table {
 150                 compatible = "operating-points-v2";
 151                 opp-shared;
 152
 153                 opp-800000000 {
 154                         opp-hz = /bits/ 64 <800000000>;
 155                         opp-microvolt = <900000>;
 156                         /* Industrial only */
 157                         opp-supported-hw = <0xf>, <0x4>;
 158                         clock-latency-ns = <150000>;
 159                 };
 160
 161                 opp-1000000000 {
 162                         opp-hz = /bits/ 64 <1000000000>;
 163                         opp-microvolt = <900000>;
 164                         /* Consumer only */
 165                         opp-supported-hw = <0xe>, <0x3>;
 166                         clock-latency-ns = <150000>;
 167                 };
 168
 169                 opp-1300000000 {
 170                         opp-hz = /bits/ 64 <1300000000>;
 171                         opp-microvolt = <1000000>;
 172                         opp-supported-hw = <0xc>, <0x4>;
 173                         clock-latency-ns = <150000>;
 174                 };
 175
 176                 opp-1500000000 {
 177                         opp-hz = /bits/ 64 <1500000000>;
 178                         opp-microvolt = <1000000>;
 179                         opp-supported-hw = <0x8>, <0x3>;
 180                         clock-latency-ns = <150000>;
 181                 };
 182         };
 183
 184         pmu {
 185                 compatible = "arm,cortex-a53-pmu";
 186                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
 187                 interrupt-parent = <&gic>;
 188                 interrupt-affinity = <&A53_0>, <&A53_1>, <&A53_2>, <&A53_3>;
 189         };
 190
 191         psci {
 192                 compatible = "arm,psci-1.0";
 193                 method = "smc";
 194         };
 195
 196         thermal-zones {
 197                 cpu-thermal {
 198                         polling-delay-passive = <250>;
 199                         polling-delay = <2000>;
 200                         thermal-sensors = <&tmu 0>;
 201
 202                         trips {
 203                                 cpu_alert: cpu-alert {
 204                                         temperature = <80000>;
 205                                         hysteresis = <2000>;
 206                                         type = "passive";
 207                                 };
 208
 209                                 cpu-crit {
 210                                         temperature = <90000>;
 211                                         hysteresis = <2000>;
 212                                         type = "critical";
 213                                 };
 214                         };
 215
 216                         cooling-maps {
 217                                 map0 {
 218                                         trip = <&cpu_alert>;
 219                                         cooling-device =
 220                                                 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 221                                                 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 222                                                 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 223                                                 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 224                                 };
 225                         };
 226                 };
 227
 228                 gpu-thermal {
 229                         polling-delay-passive = <250>;
 230                         polling-delay = <2000>;
 231                         thermal-sensors = <&tmu 1>;
 232
 233                         trips {
 234                                 gpu-crit {
 235                                         temperature = <90000>;
 236                                         hysteresis = <2000>;
 237                                         type = "critical";
 238                                 };
 239                         };
 240                 };
 241
 242                 vpu-thermal {
 243                         polling-delay-passive = <250>;
 244                         polling-delay = <2000>;
 245                         thermal-sensors = <&tmu 2>;
 246
 247                         trips {
 248                                 vpu-crit {
 249                                         temperature = <90000>;
 250                                         hysteresis = <2000>;
 251                                         type = "critical";
 252                                 };
 253                         };
 254                 };
 255         };
 256
 257         timer {
 258                 compatible = "arm,armv8-timer";
 259                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */
 260                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */
 261                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */
 262                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */
 263                 interrupt-parent = <&gic>;
 264                 arm,no-tick-in-suspend;
 265         };
 266
 267         soc@0 {
 268                 compatible = "simple-bus";
 269                 #address-cells = <1>;
 270                 #size-cells = <1>;
 271                 ranges = <0x0 0x0 0x0 0x3e000000>;
 272                 dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>;
 273
 274                 bus@30000000 { /* AIPS1 */
 275                         compatible = "fsl,imx8mq-aips-bus", "simple-bus";
 276                         #address-cells = <1>;
 277                         #size-cells = <1>;
 278                         ranges = <0x30000000 0x30000000 0x400000>;
 279
 280                         gpio1: gpio@30200000 {
 281                                 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
 282                                 reg = <0x30200000 0x10000>;
 283                                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
 284                                              <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 285                                 clocks = <&clk IMX8MQ_CLK_GPIO1_ROOT>;
 286                                 gpio-controller;
 287                                 #gpio-cells = <2>;
 288                                 interrupt-controller;
 289                                 #interrupt-cells = <2>;
 290                                 gpio-ranges = <&iomuxc 0 10 30>;
 291                         };
 292
 293                         gpio2: gpio@30210000 {
 294                                 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
 295                                 reg = <0x30210000 0x10000>;
 296                                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
 297                                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 298                                 clocks = <&clk IMX8MQ_CLK_GPIO2_ROOT>;
 299                                 gpio-controller;
 300                                 #gpio-cells = <2>;
 301                                 interrupt-controller;
 302                                 #interrupt-cells = <2>;
 303                                 gpio-ranges = <&iomuxc 0 40 21>;
 304                         };
 305
 306                         gpio3: gpio@30220000 {
 307                                 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
 308                                 reg = <0x30220000 0x10000>;
 309                                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
 310                                              <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 311                                 clocks = <&clk IMX8MQ_CLK_GPIO3_ROOT>;
 312                                 gpio-controller;
 313                                 #gpio-cells = <2>;
 314                                 interrupt-controller;
 315                                 #interrupt-cells = <2>;
 316                                 gpio-ranges = <&iomuxc 0 61 26>;
 317                         };
 318
 319                         gpio4: gpio@30230000 {
 320                                 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
 321                                 reg = <0x30230000 0x10000>;
 322                                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
 323                                              <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 324                                 clocks = <&clk IMX8MQ_CLK_GPIO4_ROOT>;
 325                                 gpio-controller;
 326                                 #gpio-cells = <2>;
 327                                 interrupt-controller;
 328                                 #interrupt-cells = <2>;
 329                                 gpio-ranges = <&iomuxc 0 87 32>;
 330                         };
 331
 332                         gpio5: gpio@30240000 {
 333                                 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
 334                                 reg = <0x30240000 0x10000>;
 335                                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
 336                                              <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 337                                 clocks = <&clk IMX8MQ_CLK_GPIO5_ROOT>;
 338                                 gpio-controller;
 339                                 #gpio-cells = <2>;
 340                                 interrupt-controller;
 341                                 #interrupt-cells = <2>;
 342                                 gpio-ranges = <&iomuxc 0 119 30>;
 343                         };
 344
 345                         tmu: tmu@30260000 {
 346                                 compatible = "fsl,imx8mq-tmu";
 347                                 reg = <0x30260000 0x10000>;
 348                                 interrupt = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
 349                                 little-endian;
 350                                 fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>;
 351                                 fsl,tmu-calibration = <0x00000000 0x00000023
 352                                                        0x00000001 0x00000029
 353                                                        0x00000002 0x0000002f
 354                                                        0x00000003 0x00000035
 355                                                        0x00000004 0x0000003d
 356                                                        0x00000005 0x00000043
 357                                                        0x00000006 0x0000004b
 358                                                        0x00000007 0x00000051
 359                                                        0x00000008 0x00000057
 360                                                        0x00000009 0x0000005f
 361                                                        0x0000000a 0x00000067
 362                                                        0x0000000b 0x0000006f
 363
 364                                                        0x00010000 0x0000001b
 365                                                        0x00010001 0x00000023
 366                                                        0x00010002 0x0000002b
 367                                                        0x00010003 0x00000033
 368                                                        0x00010004 0x0000003b
 369                                                        0x00010005 0x00000043
 370                                                        0x00010006 0x0000004b
 371                                                        0x00010007 0x00000055
 372                                                        0x00010008 0x0000005d
 373                                                        0x00010009 0x00000067
 374                                                        0x0001000a 0x00000070
 375
 376                                                        0x00020000 0x00000017
 377                                                        0x00020001 0x00000023
 378                                                        0x00020002 0x0000002d
 379                                                        0x00020003 0x00000037
 380                                                        0x00020004 0x00000041
 381                                                        0x00020005 0x0000004b
 382                                                        0x00020006 0x00000057
 383                                                        0x00020007 0x00000063
 384                                                        0x00020008 0x0000006f
 385
 386                                                        0x00030000 0x00000015
 387                                                        0x00030001 0x00000021
 388                                                        0x00030002 0x0000002d
 389                                                        0x00030003 0x00000039
 390                                                        0x00030004 0x00000045
 391                                                        0x00030005 0x00000053
 392                                                        0x00030006 0x0000005f
 393                                                        0x00030007 0x00000071>;
 394                                 #thermal-sensor-cells =  <1>;
 395                         };
 396
 397                         wdog1: watchdog@30280000 {
 398                                 compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
 399                                 reg = <0x30280000 0x10000>;
 400                                 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 401                                 clocks = <&clk IMX8MQ_CLK_WDOG1_ROOT>;
 402                                 status = "disabled";
 403                         };
 404
 405                         wdog2: watchdog@30290000 {
 406                                 compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
 407                                 reg = <0x30290000 0x10000>;
 408                                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 409                                 clocks = <&clk IMX8MQ_CLK_WDOG2_ROOT>;
 410                                 status = "disabled";
 411                         };
 412
 413                         wdog3: watchdog@302a0000 {
 414                                 compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
 415                                 reg = <0x302a0000 0x10000>;
 416                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 417                                 clocks = <&clk IMX8MQ_CLK_WDOG3_ROOT>;
 418                                 status = "disabled";
 419                         };
 420
 421                         sdma2: sdma@302c0000 {
 422                                 compatible = "fsl,imx8mq-sdma","fsl,imx7d-sdma";
 423                                 reg = <0x302c0000 0x10000>;
 424                                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 425                                 clocks = <&clk IMX8MQ_CLK_SDMA2_ROOT>,
 426                                          <&clk IMX8MQ_CLK_SDMA2_ROOT>;
 427                                 clock-names = "ipg", "ahb";
 428                                 #dma-cells = <3>;
 429                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
 430                         };
 431
 432                         iomuxc: iomuxc@30330000 {
 433                                 compatible = "fsl,imx8mq-iomuxc";
 434                                 reg = <0x30330000 0x10000>;
 435                         };
 436
 437                         iomuxc_gpr: syscon@30340000 {
 438                                 compatible = "fsl,imx8mq-iomuxc-gpr", "fsl,imx6q-iomuxc-gpr", "syscon";
 439                                 reg = <0x30340000 0x10000>;
 440                         };
 441
 442                         ocotp: ocotp-ctrl@30350000 {
 443                                 compatible = "fsl,imx8mq-ocotp", "syscon";
 444                                 reg = <0x30350000 0x10000>;
 445                                 clocks = <&clk IMX8MQ_CLK_OCOTP_ROOT>;
 446                                 #address-cells = <1>;
 447                                 #size-cells = <1>;
 448
 449                                 cpu_speed_grade: speed-grade@10 {
 450                                         reg = <0x10 4>;
 451                                 };
 452                         };
 453
 454                         anatop: syscon@30360000 {
 455                                 compatible = "fsl,imx8mq-anatop", "syscon";
 456                                 reg = <0x30360000 0x10000>;
 457                                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
 458                         };
 459
 460                         snvs: snvs@30370000 {
 461                                 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
 462                                 reg = <0x30370000 0x10000>;
 463
 464                                 snvs_rtc: snvs-rtc-lp{
 465                                         compatible = "fsl,sec-v4.0-mon-rtc-lp";
 466                                         regmap =<&snvs>;
 467                                         offset = <0x34>;
 468                                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
 469                                                 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 470                                         clocks = <&clk IMX8MQ_CLK_SNVS_ROOT>;
 471                                         clock-names = "snvs-rtc";
 472                                 };
 473
 474                                 snvs_pwrkey: snvs-powerkey {
 475                                         compatible = "fsl,sec-v4.0-pwrkey";
 476                                         regmap = <&snvs>;
 477                                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 478                                         linux,keycode = <KEY_POWER>;
 479                                         wakeup-source;
 480                                         status = "disabled";
 481                                 };
 482                         };
 483
 484                         clk: clock-controller@30380000 {
 485                                 compatible = "fsl,imx8mq-ccm";
 486                                 reg = <0x30380000 0x10000>;
 487                                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
 488                                              <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 489                                 #clock-cells = <1>;
 490                                 clocks = <&ckil>, <&osc_25m>, <&osc_27m>,
 491                                          <&clk_ext1>, <&clk_ext2>,
 492                                          <&clk_ext3>, <&clk_ext4>;
 493                                 clock-names = "ckil", "osc_25m", "osc_27m",
 494                                               "clk_ext1", "clk_ext2",
 495                                               "clk_ext3", "clk_ext4";
 496                         };
 497
 498                         src: reset-controller@30390000 {
 499                                 compatible = "fsl,imx8mq-src", "syscon";
 500                                 reg = <0x30390000 0x10000>;
 501                                 #reset-cells = <1>;
 502                         };
 503
 504                         gpc: gpc@303a0000 {
 505                                 compatible = "fsl,imx8mq-gpc";
 506                                 reg = <0x303a0000 0x10000>;
 507                                 interrupt-parent = <&gic>;
 508                                 interrupt-controller;
 509                                 #interrupt-cells = <3>;
 510
 511                                 pgc {
 512                                         #address-cells = <1>;
 513                                         #size-cells = <0>;
 514
 515                                         pgc_mipi: power-domain@0 {
 516                                                 #power-domain-cells = <0>;
 517                                                 reg = <IMX8M_POWER_DOMAIN_MIPI>;
 518                                         };
 519
 520                                         /*
 521                                          * As per comment in ATF source code:
 522                                          *
 523                                          * PCIE1 and PCIE2 share the
 524                                          * same reset signal, if we
 525                                          * power down PCIE2, PCIE1
 526                                          * will be held in reset too.
 527                                          *
 528                                          * So instead of creating two
 529                                          * separate power domains for
 530                                          * PCIE1 and PCIE2 we create a
 531                                          * link between both and use
 532                                          * it as a shared PCIE power
 533                                          * domain.
 534                                          */
 535                                         pgc_pcie: power-domain@1 {
 536                                                 #power-domain-cells = <0>;
 537                                                 reg = <IMX8M_POWER_DOMAIN_PCIE1>;
 538                                                 power-domains = <&pgc_pcie2>;
 539                                         };
 540
 541                                         pgc_otg1: power-domain@2 {
 542                                                 #power-domain-cells = <0>;
 543                                                 reg = <IMX8M_POWER_DOMAIN_USB_OTG1>;
 544                                         };
 545
 546                                         pgc_otg2: power-domain@3 {
 547                                                 #power-domain-cells = <0>;
 548                                                 reg = <IMX8M_POWER_DOMAIN_USB_OTG2>;
 549                                         };
 550
 551                                         pgc_ddr1: power-domain@4 {
 552                                                 #power-domain-cells = <0>;
 553                                                 reg = <IMX8M_POWER_DOMAIN_DDR1>;
 554                                         };
 555
 556                                         pgc_gpu: power-domain@5 {
 557                                                 #power-domain-cells = <0>;
 558                                                 reg = <IMX8M_POWER_DOMAIN_GPU>;
 559                                                 clocks = <&clk IMX8MQ_CLK_GPU_ROOT>,
 560                                                          <&clk IMX8MQ_CLK_GPU_SHADER_DIV>,
 561                                                          <&clk IMX8MQ_CLK_GPU_AXI>,
 562                                                          <&clk IMX8MQ_CLK_GPU_AHB>;
 563                                         };
 564
 565                                         pgc_vpu: power-domain@6 {
 566                                                 #power-domain-cells = <0>;
 567                                                 reg = <IMX8M_POWER_DOMAIN_VPU>;
 568                                         };
 569
 570                                         pgc_disp: power-domain@7 {
 571                                                 #power-domain-cells = <0>;
 572                                                 reg = <IMX8M_POWER_DOMAIN_DISP>;
 573                                         };
 574
 575                                         pgc_mipi_csi1: power-domain@8 {
 576                                                 #power-domain-cells = <0>;
 577                                                 reg = <IMX8M_POWER_DOMAIN_MIPI_CSI1>;
 578                                         };
 579
 580                                         pgc_mipi_csi2: power-domain@9 {
 581                                                 #power-domain-cells = <0>;
 582                                                 reg = <IMX8M_POWER_DOMAIN_MIPI_CSI2>;
 583                                         };
 584
 585                                         pgc_pcie2: power-domain@a {
 586                                                 #power-domain-cells = <0>;
 587                                                 reg = <IMX8M_POWER_DOMAIN_PCIE2>;
 588                                         };
 589                                 };
 590                         };
 591                 };
 592
 593                 bus@30400000 { /* AIPS2 */
 594                         compatible = "fsl,imx8mq-aips-bus", "simple-bus";
 595                         #address-cells = <1>;
 596                         #size-cells = <1>;
 597                         ranges = <0x30400000 0x30400000 0x400000>;
 598
 599                         pwm1: pwm@30660000 {
 600                                 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
 601                                 reg = <0x30660000 0x10000>;
 602                                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 603                                 clocks = <&clk IMX8MQ_CLK_PWM1_ROOT>,
 604                                          <&clk IMX8MQ_CLK_PWM1_ROOT>;
 605                                 clock-names = "ipg", "per";
 606                                 #pwm-cells = <2>;
 607                                 status = "disabled";
 608                         };
 609
 610                         pwm2: pwm@30670000 {
 611                                 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
 612                                 reg = <0x30670000 0x10000>;
 613                                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 614                                 clocks = <&clk IMX8MQ_CLK_PWM2_ROOT>,
 615                                          <&clk IMX8MQ_CLK_PWM2_ROOT>;
 616                                 clock-names = "ipg", "per";
 617                                 #pwm-cells = <2>;
 618                                 status = "disabled";
 619                         };
 620
 621                         pwm3: pwm@30680000 {
 622                                 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
 623                                 reg = <0x30680000 0x10000>;
 624                                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 625                                 clocks = <&clk IMX8MQ_CLK_PWM3_ROOT>,
 626                                          <&clk IMX8MQ_CLK_PWM3_ROOT>;
 627                                 clock-names = "ipg", "per";
 628                                 #pwm-cells = <2>;
 629                                 status = "disabled";
 630                         };
 631
 632                         pwm4: pwm@30690000 {
 633                                 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
 634                                 reg = <0x30690000 0x10000>;
 635                                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 636                                 clocks = <&clk IMX8MQ_CLK_PWM4_ROOT>,
 637                                          <&clk IMX8MQ_CLK_PWM4_ROOT>;
 638                                 clock-names = "ipg", "per";
 639                                 #pwm-cells = <2>;
 640                                 status = "disabled";
 641                         };
 642                 };
 643
 644                 bus@30800000 { /* AIPS3 */
 645                         compatible = "fsl,imx8mq-aips-bus", "simple-bus";
 646                         #address-cells = <1>;
 647                         #size-cells = <1>;
 648                         ranges = <0x30800000 0x30800000 0x400000>,
 649                                  <0x08000000 0x08000000 0x10000000>;
 650
 651                         ecspi1: spi@30820000 {
 652                                 #address-cells = <1>;
 653                                 #size-cells = <0>;
 654                                 compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi";
 655                                 reg = <0x30820000 0x10000>;
 656                                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 657                                 clocks = <&clk IMX8MQ_CLK_ECSPI1_ROOT>,
 658                                          <&clk IMX8MQ_CLK_ECSPI1_ROOT>;
 659                                 clock-names = "ipg", "per";
 660                                 status = "disabled";
 661                         };
 662
 663                         ecspi2: spi@30830000 {
 664                                 #address-cells = <1>;
 665                                 #size-cells = <0>;
 666                                 compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi";
 667                                 reg = <0x30830000 0x10000>;
 668                                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 669                                 clocks = <&clk IMX8MQ_CLK_ECSPI2_ROOT>,
 670                                          <&clk IMX8MQ_CLK_ECSPI2_ROOT>;
 671                                 clock-names = "ipg", "per";
 672                                 status = "disabled";
 673                         };
 674
 675                         ecspi3: spi@30840000 {
 676                                 #address-cells = <1>;
 677                                 #size-cells = <0>;
 678                                 compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi";
 679                                 reg = <0x30840000 0x10000>;
 680                                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 681                                 clocks = <&clk IMX8MQ_CLK_ECSPI3_ROOT>,
 682                                          <&clk IMX8MQ_CLK_ECSPI3_ROOT>;
 683                                 clock-names = "ipg", "per";
 684                                 status = "disabled";
 685                         };
 686
 687                         uart1: serial@30860000 {
 688                                 compatible = "fsl,imx8mq-uart",
 689                                              "fsl,imx6q-uart";
 690                                 reg = <0x30860000 0x10000>;
 691                                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 692                                 clocks = <&clk IMX8MQ_CLK_UART1_ROOT>,
 693                                          <&clk IMX8MQ_CLK_UART1_ROOT>;
 694                                 clock-names = "ipg", "per";
 695                                 status = "disabled";
 696                         };
 697
 698                         uart3: serial@30880000 {
 699                                 compatible = "fsl,imx8mq-uart",
 700                                              "fsl,imx6q-uart";
 701                                 reg = <0x30880000 0x10000>;
 702                                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 703                                 clocks = <&clk IMX8MQ_CLK_UART3_ROOT>,
 704                                          <&clk IMX8MQ_CLK_UART3_ROOT>;
 705                                 clock-names = "ipg", "per";
 706                                 status = "disabled";
 707                         };
 708
 709                         uart2: serial@30890000 {
 710                                 compatible = "fsl,imx8mq-uart",
 711                                              "fsl,imx6q-uart";
 712                                 reg = <0x30890000 0x10000>;
 713                                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 714                                 clocks = <&clk IMX8MQ_CLK_UART2_ROOT>,
 715                                          <&clk IMX8MQ_CLK_UART2_ROOT>;
 716                                 clock-names = "ipg", "per";
 717                                 status = "disabled";
 718                         };
 719
 720                         sai2: sai@308b0000 {
 721                                 #sound-dai-cells = <0>;
 722                                 compatible = "fsl,imx8mq-sai",
 723                                              "fsl,imx6sx-sai";
 724                                 reg = <0x308b0000 0x10000>;
 725                                 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 726                                 clocks = <&clk IMX8MQ_CLK_SAI2_IPG>,
 727                                          <&clk IMX8MQ_CLK_SAI2_ROOT>,
 728                                          <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>;
 729                                 clock-names = "bus", "mclk1", "mclk2", "mclk3";
 730                                 dmas = <&sdma1 10 24 0>, <&sdma1 11 24 0>;
 731                                 dma-names = "rx", "tx";
 732                                 status = "disabled";
 733                         };
 734
 735                         dphy: dphy@30a00300 {
 736                                 compatible = "fsl,imx8mq-mipi-dphy";
 737                                 reg = <0x30a00300 0x100>;
 738                                 clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>;
 739                                 clock-names = "phy_ref";
 740                                 assigned-clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>;
 741                                 assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>;
 742                                 assigned-clock-rates = <24000000>;
 743                                 #phy-cells = <0>;
 744                                 power-domains = <&pgc_mipi>;
 745                                 status = "disabled";
 746                         };
 747
 748                         i2c1: i2c@30a20000 {
 749                                 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
 750                                 reg = <0x30a20000 0x10000>;
 751                                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 752                                 clocks = <&clk IMX8MQ_CLK_I2C1_ROOT>;
 753                                 #address-cells = <1>;
 754                                 #size-cells = <0>;
 755                                 status = "disabled";
 756                         };
 757
 758                         i2c2: i2c@30a30000 {
 759                                 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
 760                                 reg = <0x30a30000 0x10000>;
 761                                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 762                                 clocks = <&clk IMX8MQ_CLK_I2C2_ROOT>;
 763                                 #address-cells = <1>;
 764                                 #size-cells = <0>;
 765                                 status = "disabled";
 766                         };
 767
 768                         i2c3: i2c@30a40000 {
 769                                 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
 770                                 reg = <0x30a40000 0x10000>;
 771                                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 772                                 clocks = <&clk IMX8MQ_CLK_I2C3_ROOT>;
 773                                 #address-cells = <1>;
 774                                 #size-cells = <0>;
 775                                 status = "disabled";
 776                         };
 777
 778                         i2c4: i2c@30a50000 {
 779                                 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
 780                                 reg = <0x30a50000 0x10000>;
 781                                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 782                                 clocks = <&clk IMX8MQ_CLK_I2C4_ROOT>;
 783                                 #address-cells = <1>;
 784                                 #size-cells = <0>;
 785                                 status = "disabled";
 786                         };
 787
 788                         uart4: serial@30a60000 {
 789                                 compatible = "fsl,imx8mq-uart",
 790                                              "fsl,imx6q-uart";
 791                                 reg = <0x30a60000 0x10000>;
 792                                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 793                                 clocks = <&clk IMX8MQ_CLK_UART4_ROOT>,
 794                                          <&clk IMX8MQ_CLK_UART4_ROOT>;
 795                                 clock-names = "ipg", "per";
 796                                 status = "disabled";
 797                         };
 798
 799                         usdhc1: mmc@30b40000 {
 800                                 compatible = "fsl,imx8mq-usdhc",
 801                                              "fsl,imx7d-usdhc";
 802                                 reg = <0x30b40000 0x10000>;
 803                                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 804                                 clocks = <&clk IMX8MQ_CLK_DUMMY>,
 805                                          <&clk IMX8MQ_CLK_NAND_USDHC_BUS>,
 806                                          <&clk IMX8MQ_CLK_USDHC1_ROOT>;
 807                                 clock-names = "ipg", "ahb", "per";
 808                                 assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>;
 809                                 assigned-clock-rates = <400000000>;
 810                                 fsl,tuning-start-tap = <20>;
 811                                 fsl,tuning-step = <2>;
 812                                 bus-width = <4>;
 813                                 status = "disabled";
 814                         };
 815
 816                         usdhc2: mmc@30b50000 {
 817                                 compatible = "fsl,imx8mq-usdhc",
 818                                              "fsl,imx7d-usdhc";
 819                                 reg = <0x30b50000 0x10000>;
 820                                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 821                                 clocks = <&clk IMX8MQ_CLK_DUMMY>,
 822                                          <&clk IMX8MQ_CLK_NAND_USDHC_BUS>,
 823                                          <&clk IMX8MQ_CLK_USDHC2_ROOT>;
 824                                 clock-names = "ipg", "ahb", "per";
 825                                 fsl,tuning-start-tap = <20>;
 826                                 fsl,tuning-step = <2>;
 827                                 bus-width = <4>;
 828                                 status = "disabled";
 829                         };
 830
 831                         qspi0: spi@30bb0000 {
 832                                 #address-cells = <1>;
 833                                 #size-cells = <0>;
 834                                 compatible = "fsl,imx8mq-qspi", "fsl,imx7d-qspi";
 835                                 reg = <0x30bb0000 0x10000>,
 836                                       <0x08000000 0x10000000>;
 837                                 reg-names = "QuadSPI", "QuadSPI-memory";
 838                                 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 839                                 clocks = <&clk IMX8MQ_CLK_QSPI_ROOT>,
 840                                          <&clk IMX8MQ_CLK_QSPI_ROOT>;
 841                                 clock-names = "qspi_en", "qspi";
 842                                 status = "disabled";
 843                         };
 844
 845                         sdma1: sdma@30bd0000 {
 846                                 compatible = "fsl,imx8mq-sdma","fsl,imx7d-sdma";
 847                                 reg = <0x30bd0000 0x10000>;
 848                                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 849                                 clocks = <&clk IMX8MQ_CLK_SDMA1_ROOT>,
 850                                          <&clk IMX8MQ_CLK_AHB>;
 851                                 clock-names = "ipg", "ahb";
 852                                 #dma-cells = <3>;
 853                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
 854                         };
 855
 856                         fec1: ethernet@30be0000 {
 857                                 compatible = "fsl,imx8mq-fec", "fsl,imx6sx-fec";
 858                                 reg = <0x30be0000 0x10000>;
 859                                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 860                                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
 861                                              <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 862                                 clocks = <&clk IMX8MQ_CLK_ENET1_ROOT>,
 863                                          <&clk IMX8MQ_CLK_ENET1_ROOT>,
 864                                          <&clk IMX8MQ_CLK_ENET_TIMER>,
 865                                          <&clk IMX8MQ_CLK_ENET_REF>,
 866                                          <&clk IMX8MQ_CLK_ENET_PHY_REF>;
 867                                 clock-names = "ipg", "ahb", "ptp",
 868                                               "enet_clk_ref", "enet_out";
 869                                 fsl,num-tx-queues = <3>;
 870                                 fsl,num-rx-queues = <3>;
 871                                 status = "disabled";
 872                         };
 873                 };
 874
 875                 bus@32c00000 { /* AIPS4 */
 876                         compatible = "fsl,imx8mq-aips-bus", "simple-bus";
 877                         #address-cells = <1>;
 878                         #size-cells = <1>;
 879                         ranges = <0x32c00000 0x32c00000 0x400000>;
 880
 881                         irqsteer: interrupt-controller@32e2d000 {
 882                                 compatible = "fsl,imx8m-irqsteer", "fsl,imx-irqsteer";
 883                                 reg = <0x32e2d000 0x1000>;
 884                                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 885                                 clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>;
 886                                 clock-names = "ipg";
 887                                 fsl,channel = <0>;
 888                                 fsl,num-irqs = <64>;
 889                                 interrupt-controller;
 890                                 #interrupt-cells = <1>;
 891                         };
 892                 };
 893
 894                 gpu: gpu@38000000 {
 895                         compatible = "vivante,gc";
 896                         reg = <0x38000000 0x40000>;
 897                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 898                         clocks = <&clk IMX8MQ_CLK_GPU_ROOT>,
 899                                  <&clk IMX8MQ_CLK_GPU_SHADER_DIV>,
 900                                  <&clk IMX8MQ_CLK_GPU_AXI>,
 901                                  <&clk IMX8MQ_CLK_GPU_AHB>;
 902                         clock-names = "core", "shader", "bus", "reg";
 903                         assigned-clocks = <&clk IMX8MQ_CLK_GPU_CORE_SRC>,
 904                                           <&clk IMX8MQ_CLK_GPU_SHADER_SRC>,
 905                                           <&clk IMX8MQ_CLK_GPU_AXI>,
 906                                           <&clk IMX8MQ_CLK_GPU_AHB>,
 907                                           <&clk IMX8MQ_GPU_PLL_BYPASS>;
 908                         assigned-clock-parents = <&clk IMX8MQ_GPU_PLL_OUT>,
 909                                                  <&clk IMX8MQ_GPU_PLL_OUT>,
 910                                                  <&clk IMX8MQ_GPU_PLL_OUT>,
 911                                                  <&clk IMX8MQ_GPU_PLL_OUT>,
 912                                                  <&clk IMX8MQ_GPU_PLL>;
 913                         assigned-clock-rates = <800000000>, <800000000>,
 914                                                <800000000>, <800000000>, <0>;
 915                         power-domains = <&pgc_gpu>;
 916                 };
 917
 918                 usb_dwc3_0: usb@38100000 {
 919                         compatible = "fsl,imx8mq-dwc3", "snps,dwc3";
 920                         reg = <0x38100000 0x10000>;
 921                         clocks = <&clk IMX8MQ_CLK_USB_BUS>,
 922                                  <&clk IMX8MQ_CLK_USB_CORE_REF>,
 923                                  <&clk IMX8MQ_CLK_USB1_CTRL_ROOT>;
 924                         clock-names = "bus_early", "ref", "suspend";
 925                         assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>,
 926                                           <&clk IMX8MQ_CLK_USB_CORE_REF>;
 927                         assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>,
 928                                                  <&clk IMX8MQ_SYS1_PLL_100M>;
 929                         assigned-clock-rates = <500000000>, <100000000>;
 930                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 931                         phys = <&usb3_phy0>, <&usb3_phy0>;
 932                         phy-names = "usb2-phy", "usb3-phy";
 933                         power-domains = <&pgc_otg1>;
 934                         usb3-resume-missing-cas;
 935                         status = "disabled";
 936                 };
 937
 938                 usb3_phy0: usb-phy@381f0040 {
 939                         compatible = "fsl,imx8mq-usb-phy";
 940                         reg = <0x381f0040 0x40>;
 941                         clocks = <&clk IMX8MQ_CLK_USB1_PHY_ROOT>;
 942                         clock-names = "phy";
 943                         assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF>;
 944                         assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>;
 945                         assigned-clock-rates = <100000000>;
 946                         #phy-cells = <0>;
 947                         status = "disabled";
 948                 };
 949
 950                 usb_dwc3_1: usb@38200000 {
 951                         compatible = "fsl,imx8mq-dwc3", "snps,dwc3";
 952                         reg = <0x38200000 0x10000>;
 953                         clocks = <&clk IMX8MQ_CLK_USB_BUS>,
 954                                  <&clk IMX8MQ_CLK_USB_CORE_REF>,
 955                                  <&clk IMX8MQ_CLK_USB2_CTRL_ROOT>;
 956                         clock-names = "bus_early", "ref", "suspend";
 957                         assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>,
 958                                           <&clk IMX8MQ_CLK_USB_CORE_REF>;
 959                         assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>,
 960                                                  <&clk IMX8MQ_SYS1_PLL_100M>;
 961                         assigned-clock-rates = <500000000>, <100000000>;
 962                         interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 963                         phys = <&usb3_phy1>, <&usb3_phy1>;
 964                         phy-names = "usb2-phy", "usb3-phy";
 965                         power-domains = <&pgc_otg2>;
 966                         usb3-resume-missing-cas;
 967                         status = "disabled";
 968                 };
 969
 970                 usb3_phy1: usb-phy@382f0040 {
 971                         compatible = "fsl,imx8mq-usb-phy";
 972                         reg = <0x382f0040 0x40>;
 973                         clocks = <&clk IMX8MQ_CLK_USB2_PHY_ROOT>;
 974                         clock-names = "phy";
 975                         assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF>;
 976                         assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>;
 977                         assigned-clock-rates = <100000000>;
 978                         #phy-cells = <0>;
 979                         status = "disabled";
 980                 };
 981
 982                 pcie0: pcie@33800000 {
 983                         compatible = "fsl,imx8mq-pcie";
 984                         reg = <0x33800000 0x400000>,
 985                               <0x1ff00000 0x80000>;
 986                         reg-names = "dbi", "config";
 987                         #address-cells = <3>;
 988                         #size-cells = <2>;
 989                         device_type = "pci";
 990                         bus-range = <0x00 0xff>;
 991                         ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000 /* downstream I/O 64KB */
 992                                   0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
 993                         num-lanes = <1>;
 994                         num-viewport = <4>;
 995                         interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
 996                         interrupt-names = "msi";
 997                         #interrupt-cells = <1>;
 998                         interrupt-map-mask = <0 0 0 0x7>;
 999                         interrupt-map = <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1000                                         <0 0 0 2 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
1001                                         <0 0 0 3 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1002                                         <0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
1003                         fsl,max-link-speed = <2>;
1004                         power-domains = <&pgc_pcie>;
1005                         resets = <&src IMX8MQ_RESET_PCIEPHY>,
1006                                  <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>,
1007                                  <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>;
1008                         reset-names = "pciephy", "apps", "turnoff";
1009                         status = "disabled";
1010                 };
1011
1012                 pcie1: pcie@33c00000 {
1013                         compatible = "fsl,imx8mq-pcie";
1014                         reg = <0x33c00000 0x400000>,
1015                               <0x27f00000 0x80000>;
1016                         reg-names = "dbi", "config";
1017                         #address-cells = <3>;
1018                         #size-cells = <2>;
1019                         device_type = "pci";
1020                         ranges =  <0x81000000 0 0x00000000 0x27f80000 0 0x00010000 /* downstream I/O 64KB */
1021                                    0x82000000 0 0x20000000 0x20000000 0 0x07f00000>; /* non-prefetchable memory */
1022                         num-lanes = <1>;
1023                         num-viewport = <4>;
1024                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
1025                         interrupt-names = "msi";
1026                         #interrupt-cells = <1>;
1027                         interrupt-map-mask = <0 0 0 0x7>;
1028                         interrupt-map = <0 0 0 1 &gic GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
1029                                         <0 0 0 2 &gic GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
1030                                         <0 0 0 3 &gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
1031                                         <0 0 0 4 &gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
1032                         fsl,max-link-speed = <2>;
1033                         power-domains = <&pgc_pcie>;
1034                         resets = <&src IMX8MQ_RESET_PCIEPHY2>,
1035                                  <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_EN>,
1036                                  <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF>;
1037                         reset-names = "pciephy", "apps", "turnoff";
1038                         status = "disabled";
1039                 };
1040
1041                 gic: interrupt-controller@38800000 {
1042                         compatible = "arm,gic-v3";
1043                         reg = <0x38800000 0x10000>,     /* GIC Dist */
1044                               <0x38880000 0xc0000>,     /* GICR */
1045                               <0x31000000 0x2000>,      /* GICC */
1046                               <0x31010000 0x2000>,      /* GICV */
1047                               <0x31020000 0x2000>;      /* GICH */
1048                         #interrupt-cells = <3>;
1049                         interrupt-controller;
1050                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
1051                         interrupt-parent = <&gic>;
1052                 };
1053
1054                 ddr-pmu@3d800000 {
1055                         compatible = "fsl,imx8mq-ddr-pmu", "fsl,imx8m-ddr-pmu";
1056                         reg = <0x3d800000 0x400000>;
1057                         interrupt-parent = <&gic>;
1058                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1059                 };
1060         };
1061 };