2 * Device Tree Include file for Marvell Armada 37xx family of SoCs.
4 * Copyright (C) 2016 Marvell
6 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * This file is dual-licensed: you can use it either under the terms
9 * of the GPL or the X11 license, at your option. Note that this dual
10 * licensing only applies to this file, and not this project as a
13 * a) This file is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of the
16 * License, or (at your option) any later version.
18 * This file is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
25 * b) Permission is hereby granted, free of charge, to any person
26 * obtaining a copy of this software and associated documentation
27 * files (the "Software"), to deal in the Software without
28 * restriction, including without limitation the rights to use,
29 * copy, modify, merge, publish, distribute, sublicense, and/or
30 * sell copies of the Software, and to permit persons to whom the
31 * Software is furnished to do so, subject to the following
34 * The above copyright notice and this permission notice shall be
35 * included in all copies or substantial portions of the Software.
37 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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47 #include <dt-bindings/interrupt-controller/arm-gic.h>
50 model = "Marvell Armada 37xx SoC";
51 compatible = "marvell,armada3700";
52 interrupt-parent = <&gic>;
65 compatible = "arm,cortex-a53", "arm,armv8";
67 enable-method = "psci";
72 compatible = "arm,psci-0.2";
77 compatible = "arm,armv8-timer";
78 interrupts = <GIC_PPI 13
79 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
81 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
83 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
85 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
89 compatible = "simple-bus";
94 internal-regs@d0000000 {
97 compatible = "simple-bus";
98 /* 32M internal register @ 0xd000_0000 */
99 ranges = <0x0 0x0 0xd0000000 0x2000000>;
102 compatible = "marvell,armada-3700-spi";
103 #address-cells = <1>;
105 reg = <0x10600 0xA00>;
106 clocks = <&nb_periph_clk 7>;
107 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
113 compatible = "marvell,armada-3700-i2c";
114 reg = <0x11000 0x24>;
115 #address-cells = <1>;
117 clocks = <&nb_periph_clk 10>;
118 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
124 compatible = "marvell,armada-3700-i2c";
125 reg = <0x11080 0x24>;
126 #address-cells = <1>;
128 clocks = <&nb_periph_clk 9>;
129 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
134 uart0: serial@12000 {
135 compatible = "marvell,armada-3700-uart";
136 reg = <0x12000 0x400>;
137 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
141 nb_periph_clk: nb-periph-clk@13000 {
142 compatible = "marvell,armada-3700-periph-clock-nb";
143 reg = <0x13000 0x100>;
144 clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>,
145 <&tbg 3>, <&xtalclk>;
149 sb_periph_clk: sb-periph-clk@18000 {
150 compatible = "marvell,armada-3700-periph-clock-sb";
151 reg = <0x18000 0x100>;
152 clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>,
153 <&tbg 3>, <&xtalclk>;
158 compatible = "marvell,armada-3700-tbg-clock";
159 reg = <0x13200 0x100>;
165 compatible = "marvell,mvebu-gpio-3700",
166 "syscon", "simple-mfd";
167 reg = <0x13800 0x500>;
170 compatible = "marvell,armada-3700-xtal-clock";
171 clock-output-names = "xtal";
176 eth0: ethernet@30000 {
177 compatible = "marvell,armada-3700-neta";
178 reg = <0x30000 0x4000>;
179 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
180 clocks = <&sb_periph_clk 8>;
185 #address-cells = <1>;
187 compatible = "marvell,orion-mdio";
191 eth1: ethernet@40000 {
192 compatible = "marvell,armada-3700-neta";
193 reg = <0x40000 0x4000>;
194 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
195 clocks = <&sb_periph_clk 7>;
200 compatible = "marvell,armada3700-xhci",
202 reg = <0x58000 0x4000>;
203 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
204 clocks = <&sb_periph_clk 12>;
209 compatible = "marvell,armada-3700-ehci";
210 reg = <0x5e000 0x2000>;
211 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
216 compatible = "marvell,armada-3700-xor";
221 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
224 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
228 sdhci0: sdhci@d8000 {
229 compatible = "marvell,armada-3700-sdhci",
230 "marvell,sdhci-xenon";
233 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
234 clocks = <&nb_periph_clk 0>;
235 clock-names = "core";
240 compatible = "marvell,armada-3700-ahci";
241 reg = <0xe0000 0x2000>;
242 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
246 gic: interrupt-controller@1d00000 {
247 compatible = "arm,gic-v3";
248 #interrupt-cells = <3>;
249 interrupt-controller;
250 reg = <0x1d00000 0x10000>, /* GICD */
251 <0x1d40000 0x40000>; /* GICR */
255 pcie0: pcie@d0070000 {
256 compatible = "marvell,armada-3700-pcie";
259 reg = <0 0xd0070000 0 0x20000>;
260 #address-cells = <3>;
262 bus-range = <0x00 0xff>;
263 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
264 #interrupt-cells = <1>;
265 msi-parent = <&pcie0>;
267 ranges = <0x82000000 0 0xe8000000 0 0xe8000000 0 0x1000000 /* Port 0 MEM */
268 0x81000000 0 0xe9000000 0 0xe9000000 0 0x10000>; /* Port 0 IO*/
269 interrupt-map-mask = <0 0 0 7>;
270 interrupt-map = <0 0 0 1 &pcie_intc 0>,
271 <0 0 0 2 &pcie_intc 1>,
272 <0 0 0 3 &pcie_intc 2>,
273 <0 0 0 4 &pcie_intc 3>;
274 pcie_intc: interrupt-controller {
275 interrupt-controller;
276 #interrupt-cells = <1>;