arch/arm64/boot/dts/marvell/armada-70x0.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (C) 2017 Marvell Technology Group Ltd.
   4  *
   5  * Device Tree file for the Armada 70x0 SoC
   6  */
   7
   8 / {
   9         aliases {
  10                 gpio1 = &cp0_gpio1;
  11                 gpio2 = &cp0_gpio2;
  12                 spi1 = &cp0_spi0;
  13                 spi2 = &cp0_spi1;
  14         };
  15 };
  16
  17 /*
  18  * Instantiate the CP110
  19  */
  20 #define CP11X_NAME              cp0
  21 #define CP11X_BASE              f2000000
  22 #define CP11X_PCIE_MEM_BASE     0xf6000000
  23 #define CP11X_PCIE0_BASE        f2600000
  24 #define CP11X_PCIE1_BASE        f2620000
  25 #define CP11X_PCIE2_BASE        f2640000
  26
  27 #include "armada-cp110.dtsi"
  28
  29 #undef CP11X_NAME
  30 #undef CP11X_BASE
  31 #undef CP11X_PCIE_MEM_BASE
  32 #undef CP11X_PCIE0_BASE
  33 #undef CP11X_PCIE1_BASE
  34 #undef CP11X_PCIE2_BASE
  35
  36 &cp0_gpio1 {
  37         status = "okay";
  38 };
  39
  40 &cp0_gpio2 {
  41         status = "okay";
  42 };
  43
  44 &cp0_syscon0 {
  45         cp0_pinctrl: pinctrl {
  46                 compatible = "marvell,armada-7k-pinctrl";
  47
  48                 nand_pins: nand-pins {
  49                         marvell,pins =
  50                         "mpp15", "mpp16", "mpp17", "mpp18",
  51                         "mpp19", "mpp20", "mpp21", "mpp22",
  52                         "mpp23", "mpp24", "mpp25", "mpp26",
  53                         "mpp27";
  54                         marvell,function = "dev";
  55                 };
  56
  57                 nand_rb: nand-rb {
  58                         marvell,pins = "mpp13";
  59                         marvell,function = "nf";
  60                 };
  61         };
  62 };