arch/arm64/boot/dts/marvell/armada-8040-db.dts

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (C) 2016 Marvell Technology Group Ltd.
   4  *
   5  * Device Tree file for Marvell Armada 8040 Development board platform
   6  */
   7
   8 #include <dt-bindings/gpio/gpio.h>
   9 #include "armada-8040.dtsi"
  10
  11 / {
  12         model = "Marvell Armada 8040 DB board";
  13         compatible = "marvell,armada8040-db", "marvell,armada8040",
  14                      "marvell,armada-ap806-quad", "marvell,armada-ap806";
  15
  16         chosen {
  17                 stdout-path = "serial0:115200n8";
  18         };
  19
  20         memory@0 {
  21                 device_type = "memory";
  22                 reg = <0x0 0x0 0x0 0x80000000>;
  23         };
  24
  25         aliases {
  26                 ethernet0 = &cp0_eth0;
  27                 ethernet1 = &cp0_eth2;
  28                 ethernet2 = &cp1_eth0;
  29                 ethernet3 = &cp1_eth1;
  30                 i2c1 = &cp0_i2c0;
  31                 i2c2 = &cp1_i2c0;
  32         };
  33
  34         cp0_reg_usb3_0_vbus: cp0-usb3-0-vbus {
  35                 compatible = "regulator-fixed";
  36                 regulator-name = "cp0-usb3h0-vbus";
  37                 regulator-min-microvolt = <5000000>;
  38                 regulator-max-microvolt = <5000000>;
  39                 enable-active-high;
  40                 gpio = <&expander0 0 GPIO_ACTIVE_HIGH>;
  41         };
  42
  43         cp0_reg_usb3_1_vbus: cp0-usb3-1-vbus {
  44                 compatible = "regulator-fixed";
  45                 regulator-name = "cp0-usb3h1-vbus";
  46                 regulator-min-microvolt = <5000000>;
  47                 regulator-max-microvolt = <5000000>;
  48                 enable-active-high;
  49                 gpio = <&expander0 1 GPIO_ACTIVE_HIGH>;
  50         };
  51
  52         cp0_usb3_0_phy: cp0-usb3-0-phy {
  53                 compatible = "usb-nop-xceiv";
  54                 vcc-supply = <&cp0_reg_usb3_0_vbus>;
  55         };
  56
  57         cp0_usb3_1_phy: cp0-usb3-1-phy {
  58                 compatible = "usb-nop-xceiv";
  59                 vcc-supply = <&cp0_reg_usb3_1_vbus>;
  60         };
  61
  62         cp1_reg_usb3_0_vbus: cp1-usb3-0-vbus {
  63                 compatible = "regulator-fixed";
  64                 regulator-name = "cp1-usb3h0-vbus";
  65                 regulator-min-microvolt = <5000000>;
  66                 regulator-max-microvolt = <5000000>;
  67                 enable-active-high;
  68                 gpio = <&expander1 0 GPIO_ACTIVE_HIGH>;
  69         };
  70
  71         cp1_usb3_0_phy: cp1-usb3-0-phy {
  72                 compatible = "usb-nop-xceiv";
  73                 vcc-supply = <&cp1_reg_usb3_0_vbus>;
  74         };
  75 };
  76
  77 &spi0 {
  78         status = "okay";
  79
  80         spi-flash@0 {
  81                 compatible = "jedec,spi-nor";
  82                 reg = <0>;
  83                 spi-max-frequency = <10000000>;
  84
  85                 partitions {
  86                         compatible = "fixed-partitions";
  87                         #address-cells = <1>;
  88                         #size-cells = <1>;
  89
  90                         partition@0 {
  91                                 label = "U-Boot";
  92                                 reg = <0 0x200000>;
  93                         };
  94                         partition@400000 {
  95                                 label = "Filesystem";
  96                                 reg = <0x200000 0xce0000>;
  97                         };
  98                 };
  99         };
 100 };
 101
 102 /* Accessible over the mini-USB CON9 connector on the main board */
 103 &uart0 {
 104         status = "okay";
 105         pinctrl-0 = <&uart0_pins>;
 106         pinctrl-names = "default";
 107 };
 108
 109 /* CON6 on CP0 expansion */
 110 &cp0_pcie0 {
 111         status = "okay";
 112 };
 113
 114 /* CON5 on CP0 expansion */
 115 &cp0_pcie2 {
 116         status = "okay";
 117 };
 118
 119 &cp0_i2c0 {
 120         status = "okay";
 121         clock-frequency = <100000>;
 122
 123         /* U31 */
 124         expander0: pca9555@21 {
 125                 compatible = "nxp,pca9555";
 126                 pinctrl-names = "default";
 127                 gpio-controller;
 128                 #gpio-cells = <2>;
 129                 reg = <0x21>;
 130         };
 131
 132         /* U25 */
 133         expander1: pca9555@25 {
 134                 compatible = "nxp,pca9555";
 135                 pinctrl-names = "default";
 136                 gpio-controller;
 137                 #gpio-cells = <2>;
 138                 reg = <0x25>;
 139         };
 140
 141 };
 142
 143 /* CON4 on CP0 expansion */
 144 &cp0_sata0 {
 145         status = "okay";
 146
 147         sata-port@0 {
 148                 phys = <&cp0_comphy1 0>;
 149                 phy-names = "cp0-sata0-0-phy";
 150         };
 151         sata-port@1 {
 152                 phys = <&cp0_comphy3 1>;
 153                 phy-names = "cp0-sata0-1-phy";
 154         };
 155 };
 156
 157 /* CON9 on CP0 expansion */
 158 &cp0_usb3_0 {
 159         usb-phy = <&cp0_usb3_0_phy>;
 160         status = "okay";
 161 };
 162
 163 /* CON10 on CP0 expansion */
 164 &cp0_usb3_1 {
 165         usb-phy = <&cp0_usb3_1_phy>;
 166         phys = <&cp0_comphy4 1>;
 167         phy-names = "cp0-usb3h1-comphy";
 168         status = "okay";
 169 };
 170
 171 &cp0_mdio {
 172         status = "okay";
 173
 174         phy1: ethernet-phy@1 {
 175                 reg = <1>;
 176         };
 177 };
 178
 179 &cp0_ethernet {
 180         status = "okay";
 181 };
 182
 183 &cp0_eth0 {
 184         status = "okay";
 185         phy-mode = "10gbase-kr";
 186
 187         fixed-link {
 188                 speed = <10000>;
 189                 full-duplex;
 190         };
 191 };
 192
 193 &cp0_eth2 {
 194         status = "okay";
 195         phy = <&phy1>;
 196         phy-mode = "rgmii-id";
 197 };
 198
 199 /* CON6 on CP1 expansion */
 200 &cp1_pcie0 {
 201         status = "okay";
 202 };
 203
 204 /* CON7 on CP1 expansion */
 205 &cp1_pcie1 {
 206         status = "okay";
 207 };
 208
 209 /* CON5 on CP1 expansion */
 210 &cp1_pcie2 {
 211         status = "okay";
 212 };
 213
 214 &cp1_i2c0 {
 215         status = "okay";
 216         clock-frequency = <100000>;
 217 };
 218
 219 &cp1_spi1 {
 220         status = "okay";
 221
 222         spi-flash@0 {
 223                 compatible = "jedec,spi-nor";
 224                 reg = <0x0>;
 225                 spi-max-frequency = <20000000>;
 226
 227                 partitions {
 228                         compatible = "fixed-partitions";
 229                         #address-cells = <1>;
 230                         #size-cells = <1>;
 231
 232                         partition@0 {
 233                                 label = "Boot";
 234                                 reg = <0x0 0x200000>;
 235                         };
 236                         partition@200000 {
 237                                 label = "Filesystem";
 238                                 reg = <0x200000 0xd00000>;
 239                         };
 240                         partition@f00000 {
 241                                 label = "Boot_2nd";
 242                                 reg = <0xf00000 0x100000>;
 243                         };
 244                 };
 245         };
 246 };
 247
 248 /*
 249  * Proper NAND usage will require DPR-76 to be in position 1-2, which disables
 250  * MDIO signal of CP1.
 251  */
 252 &cp1_nand_controller {
 253         pinctrl-0 = <&nand_pins>, <&nand_rb>;
 254         pinctrl-names = "default";
 255
 256         nand@0 {
 257                 reg = <0>;
 258                 nand-rb = <0>;
 259                 nand-on-flash-bbt;
 260                 nand-ecc-strength = <4>;
 261                 nand-ecc-step-size = <512>;
 262
 263                 partitions {
 264                         compatible = "fixed-partitions";
 265                         #address-cells = <1>;
 266                         #size-cells = <1>;
 267
 268                         partition@0 {
 269                                 label = "U-Boot";
 270                                 reg = <0 0x200000>;
 271                         };
 272                         partition@200000 {
 273                                 label = "Linux";
 274                                 reg = <0x200000 0xe00000>;
 275                         };
 276                         partition@1000000 {
 277                                 label = "Filesystem";
 278                                 reg = <0x1000000 0x3f000000>;
 279                         };
 280                 };
 281         };
 282 };
 283
 284 /* CON4 on CP1 expansion */
 285 &cp1_sata0 {
 286         status = "okay";
 287
 288         sata-port@0 {
 289                 phys = <&cp1_comphy1 0>;
 290                 phy-names = "cp1-sata0-0-phy";
 291         };
 292         sata-port@1 {
 293                 phys = <&cp1_comphy3 1>;
 294                 phy-names = "cp1-sata0-1-phy";
 295         };
 296 };
 297
 298 /* CON9 on CP1 expansion */
 299 &cp1_usb3_0 {
 300         usb-phy = <&cp1_usb3_0_phy>;
 301         status = "okay";
 302 };
 303
 304 /* CON10 on CP1 expansion */
 305 &cp1_usb3_1 {
 306         status = "okay";
 307 };
 308
 309 &cp1_mdio {
 310         status = "okay";
 311
 312         phy0: ethernet-phy@0 {
 313                 reg = <0>;
 314         };
 315 };
 316
 317 &cp1_ethernet {
 318         status = "okay";
 319 };
 320
 321 &cp1_eth0 {
 322         status = "okay";
 323         phy-mode = "10gbase-kr";
 324
 325         fixed-link {
 326                 speed = <10000>;
 327                 full-duplex;
 328         };
 329 };
 330
 331 &cp1_eth1 {
 332         status = "okay";
 333         phy = <&phy0>;
 334         phy-mode = "rgmii-id";
 335 };
 336
 337 &ap_sdhci0 {
 338         status = "okay";
 339         bus-width = <4>;
 340         non-removable;
 341 };
 342
 343 &cp0_sdhci0 {
 344         status = "okay";
 345         bus-width = <8>;
 346         non-removable;
 347 };