arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (C) 2016 Marvell Technology Group Ltd.
   4  *
   5  * Device Tree file for MACCHIATOBin Armada 8040 community board platform
   6  */
   7
   8 #include "armada-8040.dtsi"
   9
  10 #include <dt-bindings/gpio/gpio.h>
  11
  12 / {
  13         model = "Marvell 8040 MACCHIATOBin";
  14         compatible = "marvell,armada8040-mcbin", "marvell,armada8040",
  15                         "marvell,armada-ap806-quad", "marvell,armada-ap806";
  16
  17         chosen {
  18                 stdout-path = "serial0:115200n8";
  19         };
  20
  21         memory@0 {
  22                 device_type = "memory";
  23                 reg = <0x0 0x0 0x0 0x80000000>;
  24         };
  25
  26         aliases {
  27                 ethernet0 = &cp0_eth0;
  28                 ethernet1 = &cp1_eth0;
  29                 ethernet2 = &cp1_eth1;
  30                 ethernet3 = &cp1_eth2;
  31         };
  32
  33         /* Regulator labels correspond with schematics */
  34         v_3_3: regulator-3-3v {
  35                 compatible = "regulator-fixed";
  36                 regulator-name = "v_3_3";
  37                 regulator-min-microvolt = <3300000>;
  38                 regulator-max-microvolt = <3300000>;
  39                 regulator-always-on;
  40                 status = "okay";
  41         };
  42
  43         v_vddo_h: regulator-1-8v {
  44                 compatible = "regulator-fixed";
  45                 regulator-name = "v_vddo_h";
  46                 regulator-min-microvolt = <1800000>;
  47                 regulator-max-microvolt = <1800000>;
  48                 regulator-always-on;
  49                 status = "okay";
  50         };
  51
  52         v_5v0_usb3_hst_vbus: regulator-usb3-vbus0 {
  53                 compatible = "regulator-fixed";
  54                 enable-active-high;
  55                 gpio = <&cp0_gpio2 15 GPIO_ACTIVE_HIGH>;
  56                 pinctrl-names = "default";
  57                 pinctrl-0 = <&cp0_xhci_vbus_pins>;
  58                 regulator-name = "v_5v0_usb3_hst_vbus";
  59                 regulator-min-microvolt = <5000000>;
  60                 regulator-max-microvolt = <5000000>;
  61                 status = "okay";
  62         };
  63
  64         usb3h0_phy: usb3_phy0 {
  65                 compatible = "usb-nop-xceiv";
  66                 vcc-supply = <&v_5v0_usb3_hst_vbus>;
  67         };
  68
  69         sfp_eth0: sfp-eth0 {
  70                 /* CON15,16 - CPM lane 4 */
  71                 compatible = "sff,sfp";
  72                 i2c-bus = <&sfpp0_i2c>;
  73                 los-gpio = <&cp1_gpio1 28 GPIO_ACTIVE_HIGH>;
  74                 mod-def0-gpio = <&cp1_gpio1 27 GPIO_ACTIVE_LOW>;
  75                 tx-disable-gpio = <&cp1_gpio1 29 GPIO_ACTIVE_HIGH>;
  76                 tx-fault-gpio  = <&cp1_gpio1 26 GPIO_ACTIVE_HIGH>;
  77                 pinctrl-names = "default";
  78                 pinctrl-0 = <&cp1_sfpp0_pins>;
  79         };
  80
  81         sfp_eth1: sfp-eth1 {
  82                 /* CON17,18 - CPS lane 4 */
  83                 compatible = "sff,sfp";
  84                 i2c-bus = <&sfpp1_i2c>;
  85                 los-gpio = <&cp1_gpio1 8 GPIO_ACTIVE_HIGH>;
  86                 mod-def0-gpio = <&cp1_gpio1 11 GPIO_ACTIVE_LOW>;
  87                 tx-disable-gpio = <&cp1_gpio1 10 GPIO_ACTIVE_HIGH>;
  88                 tx-fault-gpio = <&cp0_gpio2 30 GPIO_ACTIVE_HIGH>;
  89                 pinctrl-names = "default";
  90                 pinctrl-0 = <&cp1_sfpp1_pins &cp0_sfpp1_pins>;
  91         };
  92
  93         sfp_eth3: sfp-eth3 {
  94                 /* CON13,14 - CPS lane 5 */
  95                 compatible = "sff,sfp";
  96                 i2c-bus = <&sfp_1g_i2c>;
  97                 los-gpio = <&cp0_gpio2 22 GPIO_ACTIVE_HIGH>;
  98                 mod-def0-gpio = <&cp0_gpio2 21 GPIO_ACTIVE_LOW>;
  99                 tx-disable-gpio = <&cp1_gpio1 24 GPIO_ACTIVE_HIGH>;
 100                 tx-fault-gpio = <&cp0_gpio2 19 GPIO_ACTIVE_HIGH>;
 101                 pinctrl-names = "default";
 102                 pinctrl-0 = <&cp0_sfp_1g_pins &cp1_sfp_1g_pins>;
 103         };
 104 };
 105
 106 &uart0 {
 107         status = "okay";
 108         pinctrl-0 = <&uart0_pins>;
 109         pinctrl-names = "default";
 110 };
 111
 112 &ap_sdhci0 {
 113         bus-width = <8>;
 114         /*
 115          * Not stable in HS modes - phy needs "more calibration", so add
 116          * the "slow-mode" and disable SDR104, SDR50 and DDR50 modes.
 117          */
 118         marvell,xenon-phy-slow-mode;
 119         no-1-8-v;
 120         no-sd;
 121         no-sdio;
 122         non-removable;
 123         status = "okay";
 124         vqmmc-supply = <&v_vddo_h>;
 125 };
 126
 127 &cp0_i2c0 {
 128         clock-frequency = <100000>;
 129         pinctrl-names = "default";
 130         pinctrl-0 = <&cp0_i2c0_pins>;
 131         status = "okay";
 132 };
 133
 134 &cp0_i2c1 {
 135         clock-frequency = <100000>;
 136         pinctrl-names = "default";
 137         pinctrl-0 = <&cp0_i2c1_pins>;
 138         status = "okay";
 139
 140         i2c-switch@70 {
 141                 compatible = "nxp,pca9548";
 142                 #address-cells = <1>;
 143                 #size-cells = <0>;
 144                 reg = <0x70>;
 145
 146                 sfpp0_i2c: i2c@0 {
 147                         #address-cells = <1>;
 148                         #size-cells = <0>;
 149                         reg = <0>;
 150                 };
 151                 sfpp1_i2c: i2c@1 {
 152                         #address-cells = <1>;
 153                         #size-cells = <0>;
 154                         reg = <1>;
 155                 };
 156                 sfp_1g_i2c: i2c@2 {
 157                         #address-cells = <1>;
 158                         #size-cells = <0>;
 159                         reg = <2>;
 160                 };
 161         };
 162 };
 163
 164 /* J25 UART header */
 165 &cp0_uart1 {
 166         pinctrl-names = "default";
 167         pinctrl-0 = <&cp0_uart1_pins>;
 168         status = "okay";
 169 };
 170
 171 &cp0_mdio {
 172         pinctrl-names = "default";
 173         pinctrl-0 = <&cp0_ge_mdio_pins>;
 174         status = "okay";
 175
 176         ge_phy: ethernet-phy@0 {
 177                 reg = <0>;
 178         };
 179 };
 180
 181 &cp0_pcie0 {
 182         pinctrl-names = "default";
 183         pinctrl-0 = <&cp0_pcie_pins>;
 184         num-lanes = <4>;
 185         num-viewport = <8>;
 186         reset-gpios = <&cp0_gpio2 20 GPIO_ACTIVE_LOW>;
 187         ranges = <0x81000000 0x0 0xf9010000 0x0 0xf9010000 0x0 0x10000
 188                   0x82000000 0x0 0xc0000000 0x0 0xc0000000 0x0 0x20000000>;
 189         status = "okay";
 190 };
 191
 192 &cp0_pinctrl {
 193         cp0_ge_mdio_pins: ge-mdio-pins {
 194                 marvell,pins = "mpp32", "mpp34";
 195                 marvell,function = "ge";
 196         };
 197         cp0_i2c1_pins: i2c1-pins {
 198                 marvell,pins = "mpp35", "mpp36";
 199                 marvell,function = "i2c1";
 200         };
 201         cp0_i2c0_pins: i2c0-pins {
 202                 marvell,pins = "mpp37", "mpp38";
 203                 marvell,function = "i2c0";
 204         };
 205         cp0_uart1_pins: uart1-pins {
 206                 marvell,pins = "mpp40", "mpp41";
 207                 marvell,function = "uart1";
 208         };
 209         cp0_xhci_vbus_pins: xhci0-vbus-pins {
 210                 marvell,pins = "mpp47";
 211                 marvell,function = "gpio";
 212         };
 213         cp0_sfp_1g_pins: sfp-1g-pins {
 214                 marvell,pins = "mpp51", "mpp53", "mpp54";
 215                 marvell,function = "gpio";
 216         };
 217         cp0_pcie_pins: pcie-pins {
 218                 marvell,pins = "mpp52";
 219                 marvell,function = "gpio";
 220         };
 221         cp0_sdhci_pins: sdhci-pins {
 222                 marvell,pins = "mpp55", "mpp56", "mpp57", "mpp58", "mpp59",
 223                                "mpp60", "mpp61";
 224                 marvell,function = "sdio";
 225         };
 226         cp0_sfpp1_pins: sfpp1-pins {
 227                 marvell,pins = "mpp62";
 228                 marvell,function = "gpio";
 229         };
 230 };
 231
 232 &cp0_ethernet {
 233         status = "okay";
 234 };
 235
 236 &cp0_eth0 {
 237         /* Generic PHY, providing serdes lanes */
 238         phys = <&cp0_comphy4 0>;
 239 };
 240
 241 &cp0_sata0 {
 242         status = "okay";
 243
 244         /* CPM Lane 5 - U29 */
 245         sata-port@1 {
 246                 phys = <&cp0_comphy5 1>;
 247                 phy-names = "cp0-sata0-1-phy";
 248         };
 249 };
 250
 251 &cp0_sdhci0 {
 252         /* U6 */
 253         broken-cd;
 254         bus-width = <4>;
 255         pinctrl-names = "default";
 256         pinctrl-0 = <&cp0_sdhci_pins>;
 257         status = "okay";
 258         vqmmc-supply = <&v_3_3>;
 259 };
 260
 261 &cp0_usb3_0 {
 262         /* J38? - USB2.0 only */
 263         status = "okay";
 264 };
 265
 266 &cp0_usb3_1 {
 267         /* J38? - USB2.0 only */
 268         status = "okay";
 269 };
 270
 271 &cp1_ethernet {
 272         status = "okay";
 273 };
 274
 275 &cp1_eth0 {
 276         /* Generic PHY, providing serdes lanes */
 277         phys = <&cp1_comphy4 0>;
 278 };
 279
 280 &cp1_eth1 {
 281         /* CPS Lane 0 - J5 (Gigabit RJ45) */
 282         status = "okay";
 283         /* Network PHY */
 284         phy = <&ge_phy>;
 285         phy-mode = "sgmii";
 286         /* Generic PHY, providing serdes lanes */
 287         phys = <&cp1_comphy0 1>;
 288 };
 289
 290 &cp1_eth2 {
 291         /* CPS Lane 5 */
 292         status = "okay";
 293         /* Network PHY */
 294         phy-mode = "2500base-x";
 295         managed = "in-band-status";
 296         /* Generic PHY, providing serdes lanes */
 297         phys = <&cp1_comphy5 2>;
 298         sfp = <&sfp_eth3>;
 299 };
 300
 301 &cp1_pinctrl {
 302         cp1_sfpp1_pins: sfpp1-pins {
 303                 marvell,pins = "mpp8", "mpp10", "mpp11";
 304                 marvell,function = "gpio";
 305         };
 306         cp1_spi1_pins: spi1-pins {
 307                 marvell,pins = "mpp12", "mpp13", "mpp14", "mpp15", "mpp16";
 308                 marvell,function = "spi1";
 309         };
 310         cp1_uart0_pins: uart0-pins {
 311                 marvell,pins = "mpp6", "mpp7";
 312                 marvell,function = "uart0";
 313         };
 314         cp1_sfp_1g_pins: sfp-1g-pins {
 315                 marvell,pins = "mpp24";
 316                 marvell,function = "gpio";
 317         };
 318         cp1_sfpp0_pins: sfpp0-pins {
 319                 marvell,pins = "mpp26", "mpp27", "mpp28", "mpp29";
 320                 marvell,function = "gpio";
 321         };
 322 };
 323
 324 /* J27 UART header */
 325 &cp1_uart0 {
 326         pinctrl-names = "default";
 327         pinctrl-0 = <&cp1_uart0_pins>;
 328         status = "okay";
 329 };
 330
 331 &cp1_sata0 {
 332         status = "okay";
 333
 334         /* CPS Lane 1 - U32 */
 335         sata-port@0 {
 336                 phys = <&cp1_comphy1 0>;
 337                 phy-names = "cp1-sata0-0-phy";
 338         };
 339
 340         /* CPS Lane 3 - U31 */
 341         sata-port@1 {
 342                 phys = <&cp1_comphy3 1>;
 343                 phy-names = "cp1-sata0-1-phy";
 344         };
 345 };
 346
 347 &cp1_spi1 {
 348         pinctrl-names = "default";
 349         pinctrl-0 = <&cp1_spi1_pins>;
 350         status = "okay";
 351
 352         spi-flash@0 {
 353                 compatible = "st,w25q32";
 354                 spi-max-frequency = <50000000>;
 355                 reg = <0>;
 356         };
 357 };
 358
 359 &cp1_usb3_0 {
 360         /* CPS Lane 2 - CON7 */
 361         usb-phy = <&usb3h0_phy>;
 362         phys = <&cp1_comphy2 0>;
 363         phy-names = "cp1-usb3h0-comphy";
 364         status = "okay";
 365 };