2 * Copyright (C) 2016 Marvell Technology Group Ltd.
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPLv2 or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
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14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
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22 * obtaining a copy of this software and associated documentation
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44 * Device Tree file for Marvell Armada CP110 Slave.
51 compatible = "simple-bus";
52 interrupt-parent = <&gic>;
58 compatible = "simple-bus";
59 interrupt-parent = <&gic>;
60 ranges = <0x0 0x0 0xf4000000 0x2000000>;
62 cps_syscon0: system-controller@440000 {
63 compatible = "marvell,cp110-system-controller0",
65 reg = <0x440000 0x1000>;
67 core-clock-output-names =
68 "cps-apll", "cps-ppv2-core", "cps-eip",
69 "cps-core", "cps-nand-core";
70 gate-clock-output-names =
71 "cps-audio", "cps-communit", "cps-nand",
72 "cps-ppv2", "cps-sdio", "cps-mg-domain",
73 "cps-mg-core", "cps-xor1", "cps-xor0",
74 "cps-gop-dp", "none", "cps-pcie_x10",
75 "cps-pcie_x11", "cps-pcie_x4", "cps-pcie-xor",
76 "cps-sata", "cps-sata-usb", "cps-main",
77 "cps-sd-mmc", "none", "none",
78 "cps-slow-io", "cps-usb3h0", "cps-usb3h1",
79 "cps-usb3dev", "cps-eip150", "cps-eip197";
82 cps_sata0: sata@540000 {
83 compatible = "marvell,armada-8k-ahci";
84 reg = <0x540000 0x30000>;
85 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
86 clocks = <&cps_syscon0 1 15>;
90 cps_usb3_0: usb3@500000 {
91 compatible = "marvell,armada-8k-xhci",
93 reg = <0x500000 0x4000>;
95 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
96 clocks = <&cps_syscon0 1 22>;
100 cps_usb3_1: usb3@510000 {
101 compatible = "marvell,armada-8k-xhci",
103 reg = <0x510000 0x4000>;
105 interrupts = <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
106 clocks = <&cps_syscon0 1 23>;
110 cps_xor0: xor@6a0000 {
111 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
112 reg = <0x6a0000 0x1000>,
115 msi-parent = <&gic_v2m0>;
116 clocks = <&cps_syscon0 1 8>;
119 cps_xor1: xor@6c0000 {
120 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
121 reg = <0x6c0000 0x1000>,
124 msi-parent = <&gic_v2m0>;
125 clocks = <&cps_syscon0 1 7>;
128 cps_spi0: spi@700600 {
129 compatible = "marvell,armada-380-spi";
130 reg = <0x700600 0x50>;
131 #address-cells = <0x1>;
134 clocks = <&cps_syscon0 0 3>;
138 cps_spi1: spi@700680 {
139 compatible = "marvell,armada-380-spi";
140 reg = <0x700680 0x50>;
141 #address-cells = <1>;
144 clocks = <&cps_syscon0 1 21>;
148 cps_i2c0: i2c@701000 {
149 compatible = "marvell,mv78230-i2c";
150 reg = <0x701000 0x20>;
151 #address-cells = <1>;
153 interrupts = <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>;
154 clocks = <&cps_syscon0 1 21>;
158 cps_i2c1: i2c@701100 {
159 compatible = "marvell,mv78230-i2c";
160 reg = <0x701100 0x20>;
161 #address-cells = <1>;
163 interrupts = <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>;
164 clocks = <&cps_syscon0 1 21>;
169 cps_pcie0: pcie@f4600000 {
170 compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
171 reg = <0 0xf4600000 0 0x10000>,
172 <0 0xfaf00000 0 0x80000>;
173 reg-names = "ctrl", "config";
174 #address-cells = <3>;
176 #interrupt-cells = <1>;
179 msi-parent = <&gic_v2m0>;
181 bus-range = <0 0xff>;
184 <0x81000000 0 0xfd000000 0 0xfd000000 0 0x10000
185 /* non-prefetchable memory */
186 0x82000000 0 0xfa000000 0 0xfa000000 0 0xf00000>;
187 interrupt-map-mask = <0 0 0 0>;
188 interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
189 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
191 clocks = <&cps_syscon0 1 13>;
195 cps_pcie1: pcie@f4620000 {
196 compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
197 reg = <0 0xf4620000 0 0x10000>,
198 <0 0xfbf00000 0 0x80000>;
199 reg-names = "ctrl", "config";
200 #address-cells = <3>;
202 #interrupt-cells = <1>;
205 msi-parent = <&gic_v2m0>;
207 bus-range = <0 0xff>;
210 <0x81000000 0 0xfd010000 0 0xfd010000 0 0x10000
211 /* non-prefetchable memory */
212 0x82000000 0 0xfb000000 0 0xfb000000 0 0xf00000>;
213 interrupt-map-mask = <0 0 0 0>;
214 interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>;
215 interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>;
218 clocks = <&cps_syscon0 1 11>;
222 cps_pcie2: pcie@f4640000 {
223 compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
224 reg = <0 0xf4640000 0 0x10000>,
225 <0 0xfcf00000 0 0x80000>;
226 reg-names = "ctrl", "config";
227 #address-cells = <3>;
229 #interrupt-cells = <1>;
232 msi-parent = <&gic_v2m0>;
234 bus-range = <0 0xff>;
237 <0x81000000 0 0xfd020000 0 0xfd020000 0 0x10000
238 /* non-prefetchable memory */
239 0x82000000 0 0xfc000000 0 0xfc000000 0 0xf00000>;
240 interrupt-map-mask = <0 0 0 0>;
241 interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>;
242 interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>;
245 clocks = <&cps_syscon0 1 12>;