1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (C) 2016 Marvell Technology Group Ltd.
5 * Device Tree file for Marvell Armada CP11x.
8 #include <dt-bindings/interrupt-controller/mvebu-icu.h>
9 #include <dt-bindings/thermal/thermal.h>
11 #include "armada-common.dtsi"
13 #define CP11X_PCIEx_MEM_BASE(iface) (CP11X_PCIE_MEM_BASE + (iface * 0x1000000))
14 #define CP11X_PCIEx_CONF_BASE(iface) (CP11X_PCIEx_MEM_BASE(iface) + 0xf00000)
18 * The contents of the node are defined below, in order to
19 * save one indentation level
21 CP11X_NAME: CP11X_NAME { };
24 * CPs only have one sensor in the thermal IC.
26 * The cooling maps are empty as there are no cooling devices.
29 CP11X_LABEL(thermal_ic): CP11X_NODE_NAME(thermal-ic) {
30 polling-delay-passive = <0>; /* Interrupt driven */
31 polling-delay = <0>; /* Interrupt driven */
33 thermal-sensors = <&CP11X_LABEL(thermal) 0>;
36 CP11X_LABEL(crit): crit {
37 temperature = <100000>; /* mC degrees */
38 hysteresis = <2000>; /* mC degrees */
51 compatible = "simple-bus";
52 interrupt-parent = <&CP11X_LABEL(icu_nsr)>;
55 config-space@CP11X_BASE {
58 compatible = "simple-bus";
59 ranges = <0x0 0x0 ADDRESSIFY(CP11X_BASE) 0x2000000>;
61 CP11X_LABEL(ethernet): ethernet@0 {
62 compatible = "marvell,armada-7k-pp22";
63 reg = <0x0 0x100000>, <0x129000 0xb000>;
64 clocks = <&CP11X_LABEL(clk) 1 3>, <&CP11X_LABEL(clk) 1 9>,
65 <&CP11X_LABEL(clk) 1 5>, <&CP11X_LABEL(clk) 1 6>,
66 <&CP11X_LABEL(clk) 1 18>;
67 clock-names = "pp_clk", "gop_clk",
68 "mg_clk", "mg_core_clk", "axi_clk";
69 marvell,system-controller = <&CP11X_LABEL(syscon0)>;
73 CP11X_LABEL(eth0): eth0 {
74 interrupts = <39 IRQ_TYPE_LEVEL_HIGH>,
75 <43 IRQ_TYPE_LEVEL_HIGH>,
76 <47 IRQ_TYPE_LEVEL_HIGH>,
77 <51 IRQ_TYPE_LEVEL_HIGH>,
78 <55 IRQ_TYPE_LEVEL_HIGH>,
79 <59 IRQ_TYPE_LEVEL_HIGH>,
80 <63 IRQ_TYPE_LEVEL_HIGH>,
81 <67 IRQ_TYPE_LEVEL_HIGH>,
82 <71 IRQ_TYPE_LEVEL_HIGH>,
83 <129 IRQ_TYPE_LEVEL_HIGH>;
84 interrupt-names = "hif0", "hif1", "hif2",
85 "hif3", "hif4", "hif5", "hif6", "hif7",
92 CP11X_LABEL(eth1): eth1 {
93 interrupts = <40 IRQ_TYPE_LEVEL_HIGH>,
94 <44 IRQ_TYPE_LEVEL_HIGH>,
95 <48 IRQ_TYPE_LEVEL_HIGH>,
96 <52 IRQ_TYPE_LEVEL_HIGH>,
97 <56 IRQ_TYPE_LEVEL_HIGH>,
98 <60 IRQ_TYPE_LEVEL_HIGH>,
99 <64 IRQ_TYPE_LEVEL_HIGH>,
100 <68 IRQ_TYPE_LEVEL_HIGH>,
101 <72 IRQ_TYPE_LEVEL_HIGH>,
102 <128 IRQ_TYPE_LEVEL_HIGH>;
103 interrupt-names = "hif0", "hif1", "hif2",
104 "hif3", "hif4", "hif5", "hif6", "hif7",
111 CP11X_LABEL(eth2): eth2 {
112 interrupts = <41 IRQ_TYPE_LEVEL_HIGH>,
113 <45 IRQ_TYPE_LEVEL_HIGH>,
114 <49 IRQ_TYPE_LEVEL_HIGH>,
115 <53 IRQ_TYPE_LEVEL_HIGH>,
116 <57 IRQ_TYPE_LEVEL_HIGH>,
117 <61 IRQ_TYPE_LEVEL_HIGH>,
118 <65 IRQ_TYPE_LEVEL_HIGH>,
119 <69 IRQ_TYPE_LEVEL_HIGH>,
120 <73 IRQ_TYPE_LEVEL_HIGH>,
121 <127 IRQ_TYPE_LEVEL_HIGH>;
122 interrupt-names = "hif0", "hif1", "hif2",
123 "hif3", "hif4", "hif5", "hif6", "hif7",
131 CP11X_LABEL(comphy): phy@120000 {
132 compatible = "marvell,comphy-cp110";
133 reg = <0x120000 0x6000>;
134 marvell,system-controller = <&CP11X_LABEL(syscon0)>;
135 clocks = <&CP11X_LABEL(clk) 1 5>, <&CP11X_LABEL(clk) 1 6>,
136 <&CP11X_LABEL(clk) 1 18>;
137 clock-names = "mg_clk", "mg_core_clk", "axi_clk";
138 #address-cells = <1>;
141 CP11X_LABEL(comphy0): phy@0 {
146 CP11X_LABEL(comphy1): phy@1 {
151 CP11X_LABEL(comphy2): phy@2 {
156 CP11X_LABEL(comphy3): phy@3 {
161 CP11X_LABEL(comphy4): phy@4 {
166 CP11X_LABEL(comphy5): phy@5 {
172 CP11X_LABEL(mdio): mdio@12a200 {
173 #address-cells = <1>;
175 compatible = "marvell,orion-mdio";
176 reg = <0x12a200 0x10>;
177 clocks = <&CP11X_LABEL(clk) 1 9>, <&CP11X_LABEL(clk) 1 5>,
178 <&CP11X_LABEL(clk) 1 6>, <&CP11X_LABEL(clk) 1 18>;
182 CP11X_LABEL(xmdio): mdio@12a600 {
183 #address-cells = <1>;
185 compatible = "marvell,xmdio";
186 reg = <0x12a600 0x10>;
187 clocks = <&CP11X_LABEL(clk) 1 5>,
188 <&CP11X_LABEL(clk) 1 6>, <&CP11X_LABEL(clk) 1 18>;
192 CP11X_LABEL(icu): interrupt-controller@1e0000 {
193 compatible = "marvell,cp110-icu";
194 reg = <0x1e0000 0x440>;
195 #address-cells = <1>;
198 CP11X_LABEL(icu_nsr): interrupt-controller@10 {
199 compatible = "marvell,cp110-icu-nsr";
201 #interrupt-cells = <2>;
202 interrupt-controller;
203 msi-parent = <&gicp>;
206 CP11X_LABEL(icu_sei): interrupt-controller@50 {
207 compatible = "marvell,cp110-icu-sei";
209 #interrupt-cells = <2>;
210 interrupt-controller;
215 CP11X_LABEL(rtc): rtc@284000 {
216 compatible = "marvell,armada-8k-rtc";
217 reg = <0x284000 0x20>, <0x284080 0x24>;
218 reg-names = "rtc", "rtc-soc";
219 interrupts = <77 IRQ_TYPE_LEVEL_HIGH>;
222 CP11X_LABEL(syscon0): system-controller@440000 {
223 compatible = "syscon", "simple-mfd";
224 reg = <0x440000 0x2000>;
226 CP11X_LABEL(clk): clock {
227 compatible = "marvell,cp110-clock";
231 CP11X_LABEL(gpio1): gpio@100 {
232 compatible = "marvell,armada-8k-gpio";
237 gpio-ranges = <&CP11X_LABEL(pinctrl) 0 0 32>;
238 interrupt-controller;
239 interrupts = <86 IRQ_TYPE_LEVEL_HIGH>,
240 <85 IRQ_TYPE_LEVEL_HIGH>,
241 <84 IRQ_TYPE_LEVEL_HIGH>,
242 <83 IRQ_TYPE_LEVEL_HIGH>;
243 #interrupt-cells = <2>;
247 CP11X_LABEL(gpio2): gpio@140 {
248 compatible = "marvell,armada-8k-gpio";
253 gpio-ranges = <&CP11X_LABEL(pinctrl) 0 32 31>;
254 interrupt-controller;
255 interrupts = <82 IRQ_TYPE_LEVEL_HIGH>,
256 <81 IRQ_TYPE_LEVEL_HIGH>,
257 <80 IRQ_TYPE_LEVEL_HIGH>,
258 <79 IRQ_TYPE_LEVEL_HIGH>;
259 #interrupt-cells = <2>;
264 CP11X_LABEL(syscon1): system-controller@400000 {
265 compatible = "syscon", "simple-mfd";
266 reg = <0x400000 0x1000>;
267 #address-cells = <1>;
270 CP11X_LABEL(thermal): thermal-sensor@70 {
271 compatible = "marvell,armada-cp110-thermal";
273 interrupts-extended =
274 <&CP11X_LABEL(icu_sei) 116 IRQ_TYPE_LEVEL_HIGH>;
275 #thermal-sensor-cells = <1>;
279 CP11X_LABEL(usb3_0): usb3@500000 {
280 compatible = "marvell,armada-8k-xhci",
282 reg = <0x500000 0x4000>;
284 interrupts = <106 IRQ_TYPE_LEVEL_HIGH>;
285 clock-names = "core", "reg";
286 clocks = <&CP11X_LABEL(clk) 1 22>,
287 <&CP11X_LABEL(clk) 1 16>;
291 CP11X_LABEL(usb3_1): usb3@510000 {
292 compatible = "marvell,armada-8k-xhci",
294 reg = <0x510000 0x4000>;
296 interrupts = <105 IRQ_TYPE_LEVEL_HIGH>;
297 clock-names = "core", "reg";
298 clocks = <&CP11X_LABEL(clk) 1 23>,
299 <&CP11X_LABEL(clk) 1 16>;
303 CP11X_LABEL(sata0): sata@540000 {
304 compatible = "marvell,armada-8k-ahci",
306 reg = <0x540000 0x30000>;
308 interrupts = <107 IRQ_TYPE_LEVEL_HIGH>;
309 clocks = <&CP11X_LABEL(clk) 1 15>,
310 <&CP11X_LABEL(clk) 1 16>;
311 #address-cells = <1>;
324 CP11X_LABEL(xor0): xor@6a0000 {
325 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
326 reg = <0x6a0000 0x1000>, <0x6b0000 0x1000>;
328 msi-parent = <&gic_v2m0>;
329 clock-names = "core", "reg";
330 clocks = <&CP11X_LABEL(clk) 1 8>,
331 <&CP11X_LABEL(clk) 1 14>;
334 CP11X_LABEL(xor1): xor@6c0000 {
335 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
336 reg = <0x6c0000 0x1000>, <0x6d0000 0x1000>;
338 msi-parent = <&gic_v2m0>;
339 clock-names = "core", "reg";
340 clocks = <&CP11X_LABEL(clk) 1 7>,
341 <&CP11X_LABEL(clk) 1 14>;
344 CP11X_LABEL(spi0): spi@700600 {
345 compatible = "marvell,armada-380-spi";
346 reg = <0x700600 0x50>;
347 #address-cells = <0x1>;
349 clock-names = "core", "axi";
350 clocks = <&CP11X_LABEL(clk) 1 21>,
351 <&CP11X_LABEL(clk) 1 17>;
355 CP11X_LABEL(spi1): spi@700680 {
356 compatible = "marvell,armada-380-spi";
357 reg = <0x700680 0x50>;
358 #address-cells = <1>;
360 clock-names = "core", "axi";
361 clocks = <&CP11X_LABEL(clk) 1 21>,
362 <&CP11X_LABEL(clk) 1 17>;
366 CP11X_LABEL(i2c0): i2c@701000 {
367 compatible = "marvell,mv78230-i2c";
368 reg = <0x701000 0x20>;
369 #address-cells = <1>;
371 interrupts = <120 IRQ_TYPE_LEVEL_HIGH>;
372 clock-names = "core", "reg";
373 clocks = <&CP11X_LABEL(clk) 1 21>,
374 <&CP11X_LABEL(clk) 1 17>;
378 CP11X_LABEL(i2c1): i2c@701100 {
379 compatible = "marvell,mv78230-i2c";
380 reg = <0x701100 0x20>;
381 #address-cells = <1>;
383 interrupts = <121 IRQ_TYPE_LEVEL_HIGH>;
384 clock-names = "core", "reg";
385 clocks = <&CP11X_LABEL(clk) 1 21>,
386 <&CP11X_LABEL(clk) 1 17>;
390 CP11X_LABEL(uart0): serial@702000 {
391 compatible = "snps,dw-apb-uart";
392 reg = <0x702000 0x100>;
394 interrupts = <122 IRQ_TYPE_LEVEL_HIGH>;
396 clock-names = "baudclk", "apb_pclk";
397 clocks = <&CP11X_LABEL(clk) 1 21>,
398 <&CP11X_LABEL(clk) 1 17>;
402 CP11X_LABEL(uart1): serial@702100 {
403 compatible = "snps,dw-apb-uart";
404 reg = <0x702100 0x100>;
406 interrupts = <123 IRQ_TYPE_LEVEL_HIGH>;
408 clock-names = "baudclk", "apb_pclk";
409 clocks = <&CP11X_LABEL(clk) 1 21>,
410 <&CP11X_LABEL(clk) 1 17>;
414 CP11X_LABEL(uart2): serial@702200 {
415 compatible = "snps,dw-apb-uart";
416 reg = <0x702200 0x100>;
418 interrupts = <124 IRQ_TYPE_LEVEL_HIGH>;
420 clock-names = "baudclk", "apb_pclk";
421 clocks = <&CP11X_LABEL(clk) 1 21>,
422 <&CP11X_LABEL(clk) 1 17>;
426 CP11X_LABEL(uart3): serial@702300 {
427 compatible = "snps,dw-apb-uart";
428 reg = <0x702300 0x100>;
430 interrupts = <125 IRQ_TYPE_LEVEL_HIGH>;
432 clock-names = "baudclk", "apb_pclk";
433 clocks = <&CP11X_LABEL(clk) 1 21>,
434 <&CP11X_LABEL(clk) 1 17>;
438 CP11X_LABEL(nand_controller): nand@720000 {
440 * Due to the limitation of the pins available
441 * this controller is only usable on the CPM
442 * for A7K and on the CPS for A8K.
444 compatible = "marvell,armada-8k-nand-controller",
445 "marvell,armada370-nand-controller";
446 reg = <0x720000 0x54>;
447 #address-cells = <1>;
449 interrupts = <115 IRQ_TYPE_LEVEL_HIGH>;
450 clock-names = "core", "reg";
451 clocks = <&CP11X_LABEL(clk) 1 2>,
452 <&CP11X_LABEL(clk) 1 17>;
453 marvell,system-controller = <&CP11X_LABEL(syscon0)>;
457 CP11X_LABEL(trng): trng@760000 {
458 compatible = "marvell,armada-8k-rng",
459 "inside-secure,safexcel-eip76";
460 reg = <0x760000 0x7d>;
461 interrupts = <95 IRQ_TYPE_LEVEL_HIGH>;
462 clock-names = "core", "reg";
463 clocks = <&CP11X_LABEL(clk) 1 25>,
464 <&CP11X_LABEL(clk) 1 17>;
468 CP11X_LABEL(sdhci0): sdhci@780000 {
469 compatible = "marvell,armada-cp110-sdhci";
470 reg = <0x780000 0x300>;
471 interrupts = <27 IRQ_TYPE_LEVEL_HIGH>;
472 clock-names = "core", "axi";
473 clocks = <&CP11X_LABEL(clk) 1 4>, <&CP11X_LABEL(clk) 1 18>;
478 CP11X_LABEL(crypto): crypto@800000 {
479 compatible = "inside-secure,safexcel-eip197b";
480 reg = <0x800000 0x200000>;
481 interrupts = <87 IRQ_TYPE_LEVEL_HIGH>,
482 <88 IRQ_TYPE_LEVEL_HIGH>,
483 <89 IRQ_TYPE_LEVEL_HIGH>,
484 <90 IRQ_TYPE_LEVEL_HIGH>,
485 <91 IRQ_TYPE_LEVEL_HIGH>,
486 <92 IRQ_TYPE_LEVEL_HIGH>;
487 interrupt-names = "mem", "ring0", "ring1",
488 "ring2", "ring3", "eip";
489 clock-names = "core", "reg";
490 clocks = <&CP11X_LABEL(clk) 1 26>,
491 <&CP11X_LABEL(clk) 1 17>;
496 CP11X_LABEL(pcie0): pcie@CP11X_PCIE0_BASE {
497 compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
498 reg = <0 ADDRESSIFY(CP11X_PCIE0_BASE) 0 0x10000>,
499 <0 CP11X_PCIEx_CONF_BASE(0) 0 0x80000>;
500 reg-names = "ctrl", "config";
501 #address-cells = <3>;
503 #interrupt-cells = <1>;
506 msi-parent = <&gic_v2m0>;
508 bus-range = <0 0xff>;
509 /* non-prefetchable memory */
510 ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(0) 0 CP11X_PCIEx_MEM_BASE(0) 0 0xf00000>;
511 interrupt-map-mask = <0 0 0 0>;
512 interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 22 IRQ_TYPE_LEVEL_HIGH>;
513 interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
515 clock-names = "core", "reg";
516 clocks = <&CP11X_LABEL(clk) 1 13>, <&CP11X_LABEL(clk) 1 14>;
520 CP11X_LABEL(pcie1): pcie@CP11X_PCIE1_BASE {
521 compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
522 reg = <0 ADDRESSIFY(CP11X_PCIE1_BASE) 0 0x10000>,
523 <0 CP11X_PCIEx_CONF_BASE(1) 0 0x80000>;
524 reg-names = "ctrl", "config";
525 #address-cells = <3>;
527 #interrupt-cells = <1>;
530 msi-parent = <&gic_v2m0>;
532 bus-range = <0 0xff>;
533 /* non-prefetchable memory */
534 ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(1) 0 CP11X_PCIEx_MEM_BASE(1) 0 0xf00000>;
535 interrupt-map-mask = <0 0 0 0>;
536 interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 24 IRQ_TYPE_LEVEL_HIGH>;
537 interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
540 clock-names = "core", "reg";
541 clocks = <&CP11X_LABEL(clk) 1 11>, <&CP11X_LABEL(clk) 1 14>;
545 CP11X_LABEL(pcie2): pcie@CP11X_PCIE2_BASE {
546 compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
547 reg = <0 ADDRESSIFY(CP11X_PCIE2_BASE) 0 0x10000>,
548 <0 CP11X_PCIEx_CONF_BASE(2) 0 0x80000>;
549 reg-names = "ctrl", "config";
550 #address-cells = <3>;
552 #interrupt-cells = <1>;
555 msi-parent = <&gic_v2m0>;
557 bus-range = <0 0xff>;
558 /* non-prefetchable memory */
559 ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(2) 0 CP11X_PCIEx_MEM_BASE(2) 0 0xf00000>;
560 interrupt-map-mask = <0 0 0 0>;
561 interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 23 IRQ_TYPE_LEVEL_HIGH>;
562 interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
565 clock-names = "core", "reg";
566 clocks = <&CP11X_LABEL(clk) 1 12>, <&CP11X_LABEL(clk) 1 14>;