2 * Copyright (c) 2018 MediaTek Inc.
3 * Author: Ryder Lee <ryder.lee@mediatek.com>
5 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/gpio/gpio.h>
12 #include "mt7622.dtsi"
13 #include "mt6380.dtsi"
16 model = "Bananapi BPI-R64";
17 compatible = "bananapi,bpi-r64", "mediatek,mt7622";
20 bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n1 swiotlb=512";
25 proc-supply = <&mt6380_vcpu_reg>;
26 sram-supply = <&mt6380_vm_reg>;
30 proc-supply = <&mt6380_vcpu_reg>;
31 sram-supply = <&mt6380_vm_reg>;
36 compatible = "gpio-keys";
41 gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
46 linux,code = <KEY_WPS_BUTTON>;
47 gpios = <&pio 102 GPIO_ACTIVE_HIGH>;
52 compatible = "gpio-leds";
55 label = "bpi-r64:pio:green";
56 gpios = <&pio 89 GPIO_ACTIVE_HIGH>;
57 default-state = "off";
61 label = "bpi-r64:pio:red";
62 gpios = <&pio 88 GPIO_ACTIVE_HIGH>;
63 default-state = "off";
68 reg = <0 0x40000000 0 0x40000000>;
71 reg_1p8v: regulator-1p8v {
72 compatible = "regulator-fixed";
73 regulator-name = "fixed-1.8V";
74 regulator-min-microvolt = <1800000>;
75 regulator-max-microvolt = <1800000>;
79 reg_3p3v: regulator-3p3v {
80 compatible = "regulator-fixed";
81 regulator-name = "fixed-3.3V";
82 regulator-min-microvolt = <3300000>;
83 regulator-max-microvolt = <3300000>;
88 reg_5v: regulator-5v {
89 compatible = "regulator-fixed";
90 regulator-name = "fixed-5V";
91 regulator-min-microvolt = <5000000>;
92 regulator-max-microvolt = <5000000>;
107 pinctrl-names = "default";
108 pinctrl-0 = <&irrx_pins>;
113 pinctrl-names = "default";
114 pinctrl-0 = <ð_pins>;
118 compatible = "mediatek,eth-mac";
120 phy-handle = <&phy5>;
124 #address-cells = <1>;
127 phy5: ethernet-phy@5 {
135 pinctrl-names = "default";
136 pinctrl-0 = <&i2c1_pins>;
141 pinctrl-names = "default";
142 pinctrl-0 = <&i2c2_pins>;
147 pinctrl-names = "default", "state_uhs";
148 pinctrl-0 = <&emmc_pins_default>;
149 pinctrl-1 = <&emmc_pins_uhs>;
152 max-frequency = <50000000>;
155 vmmc-supply = <®_3p3v>;
156 vqmmc-supply = <®_1p8v>;
157 assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>;
158 assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
163 pinctrl-names = "default", "state_uhs";
164 pinctrl-0 = <&sd0_pins_default>;
165 pinctrl-1 = <&sd0_pins_uhs>;
168 max-frequency = <50000000>;
171 cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>;
172 vmmc-supply = <®_3p3v>;
173 vqmmc-supply = <®_3p3v>;
174 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
175 assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
179 pinctrl-names = "default";
180 pinctrl-0 = <¶llel_nand_pins>;
185 pinctrl-names = "default";
186 pinctrl-0 = <&spi_nor_pins>;
190 compatible = "jedec,spi-nor";
196 pinctrl-names = "default";
197 pinctrl-0 = <&pcie0_pins>, <&pcie1_pins>;
210 /* Attention: GPIO 90 is used to switch between PCIe@1,0 and
211 * SATA functions. i.e. output-high: PCIe, output-low: SATA
215 gpios = <90 GPIO_ACTIVE_HIGH>;
219 /* eMMC is shared pin with parallel NAND */
220 emmc_pins_default: emmc-pins-default {
222 function = "emmc", "emmc_rst";
226 /* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7",
227 * "NRB","NCLE" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4,
228 * DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively
231 pins = "NDL0", "NDL1", "NDL2",
232 "NDL3", "NDL4", "NDL5",
233 "NDL6", "NDL7", "NRB";
244 emmc_pins_uhs: emmc-pins-uhs {
251 pins = "NDL0", "NDL1", "NDL2",
252 "NDL3", "NDL4", "NDL5",
253 "NDL6", "NDL7", "NRB";
255 drive-strength = <4>;
261 drive-strength = <4>;
269 groups = "mdc_mdio", "rgmii_via_gmac2";
273 i2c1_pins: i2c1-pins {
280 i2c2_pins: i2c2-pins {
287 i2s1_pins: i2s1-pins {
290 groups = "i2s_out_mclk_bclk_ws",
296 pins = "I2S1_IN", "I2S1_OUT", "I2S_BCLK",
297 "I2S_WS", "I2S_MCLK";
298 drive-strength = <12>;
303 irrx_pins: irrx-pins {
310 irtx_pins: irtx-pins {
317 /* Parallel nand is shared pin with eMMC */
318 parallel_nand_pins: parallel-nand-pins {
325 pcie0_pins: pcie0-pins {
328 groups = "pcie0_pad_perst",
334 pcie1_pins: pcie1-pins {
337 groups = "pcie1_pad_perst",
343 pmic_bus_pins: pmic-bus-pins {
350 pwm7_pins: pwm1-2-pins {
353 groups = "pwm_ch7_2";
357 wled_pins: wled-pins {
364 sd0_pins_default: sd0-pins-default {
370 /* "I2S2_OUT, "I2S4_IN"", "I2S3_IN", "I2S2_IN",
371 * "I2S4_OUT", "I2S3_OUT" are used as DAT0, DAT1,
372 * DAT2, DAT3, CMD, CLK for SD respectively.
375 pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
376 "I2S2_IN","I2S4_OUT";
378 drive-strength = <8>;
383 drive-strength = <12>;
392 sd0_pins_uhs: sd0-pins-uhs {
399 pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
400 "I2S2_IN","I2S4_OUT";
411 /* Serial NAND is shared pin with SPI-NOR */
412 serial_nand_pins: serial-nand-pins {
419 spic0_pins: spic0-pins {
426 spic1_pins: spic1-pins {
433 /* SPI-NOR is shared pin with serial NAND */
434 spi_nor_pins: spi-nor-pins {
441 /* serial NAND is shared pin with SPI-NOR */
442 serial_nand_pins: serial-nand-pins {
449 uart0_pins: uart0-pins {
452 groups = "uart0_0_tx_rx" ;
456 uart2_pins: uart2-pins {
459 groups = "uart2_1_tx_rx" ;
463 watchdog_pins: watchdog-pins {
465 function = "watchdog";
472 pinctrl-names = "default";
473 pinctrl-0 = <&pwm7_pins>;
478 pinctrl-names = "default";
479 pinctrl-0 = <&pmic_bus_pins>;
493 pinctrl-names = "default";
494 pinctrl-0 = <&spic0_pins>;
499 pinctrl-names = "default";
500 pinctrl-0 = <&spic1_pins>;
505 vusb33-supply = <®_3p3v>;
506 vbus-supply = <®_5v>;
515 pinctrl-names = "default";
516 pinctrl-0 = <&uart0_pins>;
521 pinctrl-names = "default";
522 pinctrl-0 = <&uart2_pins>;
527 pinctrl-names = "default";
528 pinctrl-0 = <&watchdog_pins>;