2 * Copyright (c) 2014 MediaTek Inc.
3 * Author: Eddie Huang <eddie.huang@mediatek.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #include <dt-bindings/clock/mt8173-clk.h>
15 #include <dt-bindings/interrupt-controller/irq.h>
16 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 #include <dt-bindings/memory/mt8173-larb-port.h>
18 #include <dt-bindings/phy/phy.h>
19 #include <dt-bindings/power/mt8173-power.h>
20 #include <dt-bindings/reset/mt8173-resets.h>
21 #include "mt8173-pinfunc.h"
24 compatible = "mediatek,mt8173";
25 interrupt-parent = <&sysirq>;
44 mdp_rdma0 = &mdp_rdma0;
45 mdp_rdma1 = &mdp_rdma1;
49 mdp_wdma0 = &mdp_wdma0;
50 mdp_wrot0 = &mdp_wrot0;
51 mdp_wrot1 = &mdp_wrot1;
80 compatible = "arm,cortex-a53";
82 enable-method = "psci";
83 cpu-idle-states = <&CPU_SLEEP_0>;
88 compatible = "arm,cortex-a53";
90 enable-method = "psci";
91 cpu-idle-states = <&CPU_SLEEP_0>;
96 compatible = "arm,cortex-a57";
98 enable-method = "psci";
99 cpu-idle-states = <&CPU_SLEEP_0>;
104 compatible = "arm,cortex-a57";
106 enable-method = "psci";
107 cpu-idle-states = <&CPU_SLEEP_0>;
111 entry-method = "psci";
113 CPU_SLEEP_0: cpu-sleep-0 {
114 compatible = "arm,idle-state";
116 entry-latency-us = <639>;
117 exit-latency-us = <680>;
118 min-residency-us = <1088>;
119 arm,psci-suspend-param = <0x0010000>;
125 compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci";
127 cpu_suspend = <0x84000001>;
128 cpu_off = <0x84000002>;
129 cpu_on = <0x84000003>;
132 clk26m: oscillator@0 {
133 compatible = "fixed-clock";
135 clock-frequency = <26000000>;
136 clock-output-names = "clk26m";
139 clk32k: oscillator@1 {
140 compatible = "fixed-clock";
142 clock-frequency = <32000>;
143 clock-output-names = "clk32k";
146 cpum_ck: oscillator@2 {
147 compatible = "fixed-clock";
149 clock-frequency = <0>;
150 clock-output-names = "cpum_ck";
154 cpu_thermal: cpu_thermal {
155 polling-delay-passive = <1000>; /* milliseconds */
156 polling-delay = <1000>; /* milliseconds */
158 thermal-sensors = <&thermal>;
159 sustainable-power = <1500>; /* milliwatts */
162 threshold: trip-point@0 {
163 temperature = <68000>;
168 target: trip-point@1 {
169 temperature = <85000>;
174 cpu_crit: cpu_crit@0 {
175 temperature = <115000>;
184 cooling-device = <&cpu0 0 0>;
185 contribution = <3072>;
189 cooling-device = <&cpu2 0 0>;
190 contribution = <1024>;
197 #address-cells = <2>;
200 vpu_dma_reserved: vpu_dma_mem_region {
201 compatible = "shared-dma-pool";
202 reg = <0 0xb7000000 0 0x500000>;
203 alignment = <0x1000>;
209 compatible = "arm,armv8-timer";
210 interrupt-parent = <&gic>;
211 interrupts = <GIC_PPI 13
212 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
214 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
216 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
218 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
222 #address-cells = <2>;
224 compatible = "simple-bus";
227 topckgen: clock-controller@10000000 {
228 compatible = "mediatek,mt8173-topckgen";
229 reg = <0 0x10000000 0 0x1000>;
233 infracfg: power-controller@10001000 {
234 compatible = "mediatek,mt8173-infracfg", "syscon";
235 reg = <0 0x10001000 0 0x1000>;
240 pericfg: power-controller@10003000 {
241 compatible = "mediatek,mt8173-pericfg", "syscon";
242 reg = <0 0x10003000 0 0x1000>;
247 syscfg_pctl_a: syscfg_pctl_a@10005000 {
248 compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon";
249 reg = <0 0x10005000 0 0x1000>;
252 pio: pinctrl@0x10005000 {
253 compatible = "mediatek,mt8173-pinctrl";
254 reg = <0 0x1000b000 0 0x1000>;
255 mediatek,pctl-regmap = <&syscfg_pctl_a>;
259 interrupt-controller;
260 #interrupt-cells = <2>;
261 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
262 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
263 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
269 pinmux = <MT8173_PIN_21_HTPLG__FUNC_HTPLG>;
277 pinmux = <MT8173_PIN_45_SDA0__FUNC_SDA0>,
278 <MT8173_PIN_46_SCL0__FUNC_SCL0>;
285 pinmux = <MT8173_PIN_125_SDA1__FUNC_SDA1>,
286 <MT8173_PIN_126_SCL1__FUNC_SCL1>;
293 pinmux = <MT8173_PIN_43_SDA2__FUNC_SDA2>,
294 <MT8173_PIN_44_SCL2__FUNC_SCL2>;
301 pinmux = <MT8173_PIN_106_SDA3__FUNC_SDA3>,
302 <MT8173_PIN_107_SCL3__FUNC_SCL3>;
309 pinmux = <MT8173_PIN_133_SDA4__FUNC_SDA4>,
310 <MT8173_PIN_134_SCL4__FUNC_SCL4>;
317 pinmux = <MT8173_PIN_100_MSDC2_DAT0__FUNC_SDA5>,
318 <MT8173_PIN_101_MSDC2_DAT1__FUNC_SCL5>;
324 scpsys: scpsys@10006000 {
325 compatible = "mediatek,mt8173-scpsys";
326 #power-domain-cells = <1>;
327 reg = <0 0x10006000 0 0x1000>;
329 <&topckgen CLK_TOP_MM_SEL>,
330 <&topckgen CLK_TOP_VENC_SEL>,
331 <&topckgen CLK_TOP_VENC_LT_SEL>;
332 clock-names = "mfg", "mm", "venc", "venc_lt";
333 infracfg = <&infracfg>;
336 watchdog: watchdog@10007000 {
337 compatible = "mediatek,mt8173-wdt",
338 "mediatek,mt6589-wdt";
339 reg = <0 0x10007000 0 0x100>;
342 timer: timer@10008000 {
343 compatible = "mediatek,mt8173-timer",
344 "mediatek,mt6577-timer";
345 reg = <0 0x10008000 0 0x1000>;
346 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>;
347 clocks = <&infracfg CLK_INFRA_CLK_13M>,
348 <&topckgen CLK_TOP_RTC_SEL>;
351 pwrap: pwrap@1000d000 {
352 compatible = "mediatek,mt8173-pwrap";
353 reg = <0 0x1000d000 0 0x1000>;
355 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
356 resets = <&infracfg MT8173_INFRA_PMIC_WRAP_RST>;
357 reset-names = "pwrap";
358 clocks = <&infracfg CLK_INFRA_PMICSPI>, <&infracfg CLK_INFRA_PMICWRAP>;
359 clock-names = "spi", "wrap";
363 compatible = "mediatek,mt8173-cec";
364 reg = <0 0x10013000 0 0xbc>;
365 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>;
366 clocks = <&infracfg CLK_INFRA_CEC>;
371 compatible = "mediatek,mt8173-vpu";
372 reg = <0 0x10020000 0 0x30000>,
373 <0 0x10050000 0 0x100>;
374 reg-names = "tcm", "cfg_reg";
375 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
376 clocks = <&topckgen CLK_TOP_SCP_SEL>;
377 clock-names = "main";
378 memory-region = <&vpu_dma_reserved>;
381 sysirq: intpol-controller@10200620 {
382 compatible = "mediatek,mt8173-sysirq",
383 "mediatek,mt6577-sysirq";
384 interrupt-controller;
385 #interrupt-cells = <3>;
386 interrupt-parent = <&gic>;
387 reg = <0 0x10200620 0 0x20>;
390 iommu: iommu@10205000 {
391 compatible = "mediatek,mt8173-m4u";
392 reg = <0 0x10205000 0 0x1000>;
393 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>;
394 clocks = <&infracfg CLK_INFRA_M4U>;
395 clock-names = "bclk";
396 mediatek,larbs = <&larb0 &larb1 &larb2
397 &larb3 &larb4 &larb5>;
401 efuse: efuse@10206000 {
402 compatible = "mediatek,mt8173-efuse";
403 reg = <0 0x10206000 0 0x1000>;
404 #address-cells = <1>;
406 thermal_calibration: calib@528 {
411 apmixedsys: clock-controller@10209000 {
412 compatible = "mediatek,mt8173-apmixedsys";
413 reg = <0 0x10209000 0 0x1000>;
417 hdmi_phy: hdmi-phy@10209100 {
418 compatible = "mediatek,mt8173-hdmi-phy";
419 reg = <0 0x10209100 0 0x24>;
420 clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>;
421 clock-names = "pll_ref";
422 clock-output-names = "hdmitx_dig_cts";
423 mediatek,ibias = <0xa>;
424 mediatek,ibias_up = <0x1c>;
430 mipi_tx0: mipi-dphy@10215000 {
431 compatible = "mediatek,mt8173-mipi-tx";
432 reg = <0 0x10215000 0 0x1000>;
434 clock-output-names = "mipi_tx0_pll";
440 mipi_tx1: mipi-dphy@10216000 {
441 compatible = "mediatek,mt8173-mipi-tx";
442 reg = <0 0x10216000 0 0x1000>;
444 clock-output-names = "mipi_tx1_pll";
450 gic: interrupt-controller@10220000 {
451 compatible = "arm,gic-400";
452 #interrupt-cells = <3>;
453 interrupt-parent = <&gic>;
454 interrupt-controller;
455 reg = <0 0x10221000 0 0x1000>,
456 <0 0x10222000 0 0x2000>,
457 <0 0x10224000 0 0x2000>,
458 <0 0x10226000 0 0x2000>;
459 interrupts = <GIC_PPI 9
460 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
463 auxadc: auxadc@11001000 {
464 compatible = "mediatek,mt8173-auxadc";
465 reg = <0 0x11001000 0 0x1000>;
466 clocks = <&pericfg CLK_PERI_AUXADC>;
467 clock-names = "main";
468 #io-channel-cells = <1>;
471 uart0: serial@11002000 {
472 compatible = "mediatek,mt8173-uart",
473 "mediatek,mt6577-uart";
474 reg = <0 0x11002000 0 0x400>;
475 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>;
476 clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>;
477 clock-names = "baud", "bus";
481 uart1: serial@11003000 {
482 compatible = "mediatek,mt8173-uart",
483 "mediatek,mt6577-uart";
484 reg = <0 0x11003000 0 0x400>;
485 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
486 clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>;
487 clock-names = "baud", "bus";
491 uart2: serial@11004000 {
492 compatible = "mediatek,mt8173-uart",
493 "mediatek,mt6577-uart";
494 reg = <0 0x11004000 0 0x400>;
495 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
496 clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>;
497 clock-names = "baud", "bus";
501 uart3: serial@11005000 {
502 compatible = "mediatek,mt8173-uart",
503 "mediatek,mt6577-uart";
504 reg = <0 0x11005000 0 0x400>;
505 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
506 clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>;
507 clock-names = "baud", "bus";
512 compatible = "mediatek,mt8173-i2c";
513 reg = <0 0x11007000 0 0x70>,
514 <0 0x11000100 0 0x80>;
515 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>;
517 clocks = <&pericfg CLK_PERI_I2C0>,
518 <&pericfg CLK_PERI_AP_DMA>;
519 clock-names = "main", "dma";
520 pinctrl-names = "default";
521 pinctrl-0 = <&i2c0_pins_a>;
522 #address-cells = <1>;
528 compatible = "mediatek,mt8173-i2c";
529 reg = <0 0x11008000 0 0x70>,
530 <0 0x11000180 0 0x80>;
531 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
533 clocks = <&pericfg CLK_PERI_I2C1>,
534 <&pericfg CLK_PERI_AP_DMA>;
535 clock-names = "main", "dma";
536 pinctrl-names = "default";
537 pinctrl-0 = <&i2c1_pins_a>;
538 #address-cells = <1>;
544 compatible = "mediatek,mt8173-i2c";
545 reg = <0 0x11009000 0 0x70>,
546 <0 0x11000200 0 0x80>;
547 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
549 clocks = <&pericfg CLK_PERI_I2C2>,
550 <&pericfg CLK_PERI_AP_DMA>;
551 clock-names = "main", "dma";
552 pinctrl-names = "default";
553 pinctrl-0 = <&i2c2_pins_a>;
554 #address-cells = <1>;
560 compatible = "mediatek,mt8173-spi";
561 #address-cells = <1>;
563 reg = <0 0x1100a000 0 0x1000>;
564 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>;
565 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
566 <&topckgen CLK_TOP_SPI_SEL>,
567 <&pericfg CLK_PERI_SPI0>;
568 clock-names = "parent-clk", "sel-clk", "spi-clk";
572 thermal: thermal@1100b000 {
573 #thermal-sensor-cells = <0>;
574 compatible = "mediatek,mt8173-thermal";
575 reg = <0 0x1100b000 0 0x1000>;
576 interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>;
577 clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>;
578 clock-names = "therm", "auxadc";
579 resets = <&pericfg MT8173_PERI_THERM_SW_RST>;
580 mediatek,auxadc = <&auxadc>;
581 mediatek,apmixedsys = <&apmixedsys>;
582 nvmem-cells = <&thermal_calibration>;
583 nvmem-cell-names = "calibration-data";
586 nor_flash: spi@1100d000 {
587 compatible = "mediatek,mt8173-nor";
588 reg = <0 0x1100d000 0 0xe0>;
589 clocks = <&pericfg CLK_PERI_SPI>,
590 <&topckgen CLK_TOP_SPINFI_IFR_SEL>;
591 clock-names = "spi", "sf";
592 #address-cells = <1>;
598 compatible = "mediatek,mt8173-i2c";
599 reg = <0 0x11010000 0 0x70>,
600 <0 0x11000280 0 0x80>;
601 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
603 clocks = <&pericfg CLK_PERI_I2C3>,
604 <&pericfg CLK_PERI_AP_DMA>;
605 clock-names = "main", "dma";
606 pinctrl-names = "default";
607 pinctrl-0 = <&i2c3_pins_a>;
608 #address-cells = <1>;
614 compatible = "mediatek,mt8173-i2c";
615 reg = <0 0x11011000 0 0x70>,
616 <0 0x11000300 0 0x80>;
617 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>;
619 clocks = <&pericfg CLK_PERI_I2C4>,
620 <&pericfg CLK_PERI_AP_DMA>;
621 clock-names = "main", "dma";
622 pinctrl-names = "default";
623 pinctrl-0 = <&i2c4_pins_a>;
624 #address-cells = <1>;
629 hdmiddc0: i2c@11012000 {
630 compatible = "mediatek,mt8173-hdmi-ddc";
631 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>;
632 reg = <0 0x11012000 0 0x1C>;
633 clocks = <&pericfg CLK_PERI_I2C5>;
634 clock-names = "ddc-i2c";
638 compatible = "mediatek,mt8173-i2c";
639 reg = <0 0x11013000 0 0x70>,
640 <0 0x11000080 0 0x80>;
641 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>;
643 clocks = <&pericfg CLK_PERI_I2C6>,
644 <&pericfg CLK_PERI_AP_DMA>;
645 clock-names = "main", "dma";
646 pinctrl-names = "default";
647 pinctrl-0 = <&i2c6_pins_a>;
648 #address-cells = <1>;
653 afe: audio-controller@11220000 {
654 compatible = "mediatek,mt8173-afe-pcm";
655 reg = <0 0x11220000 0 0x1000>;
656 interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_FALLING>;
657 power-domains = <&scpsys MT8173_POWER_DOMAIN_AUDIO>;
658 clocks = <&infracfg CLK_INFRA_AUDIO>,
659 <&topckgen CLK_TOP_AUDIO_SEL>,
660 <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
661 <&topckgen CLK_TOP_APLL1_DIV0>,
662 <&topckgen CLK_TOP_APLL2_DIV0>,
663 <&topckgen CLK_TOP_I2S0_M_SEL>,
664 <&topckgen CLK_TOP_I2S1_M_SEL>,
665 <&topckgen CLK_TOP_I2S2_M_SEL>,
666 <&topckgen CLK_TOP_I2S3_M_SEL>,
667 <&topckgen CLK_TOP_I2S3_B_SEL>;
668 clock-names = "infra_sys_audio_clk",
670 "top_pdn_aud_intbus",
678 assigned-clocks = <&topckgen CLK_TOP_AUD_1_SEL>,
679 <&topckgen CLK_TOP_AUD_2_SEL>;
680 assigned-clock-parents = <&topckgen CLK_TOP_APLL1>,
681 <&topckgen CLK_TOP_APLL2>;
685 compatible = "mediatek,mt8173-mmc",
686 "mediatek,mt8135-mmc";
687 reg = <0 0x11230000 0 0x1000>;
688 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_LOW>;
689 clocks = <&pericfg CLK_PERI_MSDC30_0>,
690 <&topckgen CLK_TOP_MSDC50_0_H_SEL>;
691 clock-names = "source", "hclk";
696 compatible = "mediatek,mt8173-mmc",
697 "mediatek,mt8135-mmc";
698 reg = <0 0x11240000 0 0x1000>;
699 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>;
700 clocks = <&pericfg CLK_PERI_MSDC30_1>,
701 <&topckgen CLK_TOP_AXI_SEL>;
702 clock-names = "source", "hclk";
707 compatible = "mediatek,mt8173-mmc",
708 "mediatek,mt8135-mmc";
709 reg = <0 0x11250000 0 0x1000>;
710 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_LOW>;
711 clocks = <&pericfg CLK_PERI_MSDC30_2>,
712 <&topckgen CLK_TOP_AXI_SEL>;
713 clock-names = "source", "hclk";
718 compatible = "mediatek,mt8173-mmc",
719 "mediatek,mt8135-mmc";
720 reg = <0 0x11260000 0 0x1000>;
721 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_LOW>;
722 clocks = <&pericfg CLK_PERI_MSDC30_3>,
723 <&topckgen CLK_TOP_MSDC50_2_H_SEL>;
724 clock-names = "source", "hclk";
728 ssusb: usb@11271000 {
729 compatible = "mediatek,mt8173-mtu3";
730 reg = <0 0x11271000 0 0x3000>,
731 <0 0x11280700 0 0x0100>;
732 reg-names = "mac", "ippc";
733 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_LOW>;
734 phys = <&phy_port0 PHY_TYPE_USB3>,
735 <&phy_port1 PHY_TYPE_USB2>;
736 power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>;
737 clocks = <&topckgen CLK_TOP_USB30_SEL>,
738 <&pericfg CLK_PERI_USB0>,
739 <&pericfg CLK_PERI_USB1>;
740 clock-names = "sys_ck",
743 mediatek,syscon-wakeup = <&pericfg>;
744 #address-cells = <2>;
749 usb_host: xhci@11270000 {
750 compatible = "mediatek,mt8173-xhci";
751 reg = <0 0x11270000 0 0x1000>;
753 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>;
754 power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>;
755 clocks = <&topckgen CLK_TOP_USB30_SEL>;
756 clock-names = "sys_ck";
761 u3phy: usb-phy@11290000 {
762 compatible = "mediatek,mt8173-u3phy";
763 reg = <0 0x11290000 0 0x800>;
764 clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;
765 clock-names = "u3phya_ref";
766 #address-cells = <2>;
771 phy_port0: port@11290800 {
772 reg = <0 0x11290800 0 0x800>;
777 phy_port1: port@11291000 {
778 reg = <0 0x11291000 0 0x800>;
784 mmsys: clock-controller@14000000 {
785 compatible = "mediatek,mt8173-mmsys", "syscon";
786 reg = <0 0x14000000 0 0x1000>;
787 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
788 assigned-clocks = <&topckgen CLK_TOP_MM_SEL>;
789 assigned-clock-rates = <400000000>;
794 compatible = "mediatek,mt8173-mdp";
795 #address-cells = <2>;
798 mediatek,vpu = <&vpu>;
800 mdp_rdma0: rdma@14001000 {
801 compatible = "mediatek,mt8173-mdp-rdma";
802 reg = <0 0x14001000 0 0x1000>;
803 clocks = <&mmsys CLK_MM_MDP_RDMA0>,
804 <&mmsys CLK_MM_MUTEX_32K>;
805 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
806 iommus = <&iommu M4U_PORT_MDP_RDMA0>;
807 mediatek,larb = <&larb0>;
810 mdp_rdma1: rdma@14002000 {
811 compatible = "mediatek,mt8173-mdp-rdma";
812 reg = <0 0x14002000 0 0x1000>;
813 clocks = <&mmsys CLK_MM_MDP_RDMA1>,
814 <&mmsys CLK_MM_MUTEX_32K>;
815 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
816 iommus = <&iommu M4U_PORT_MDP_RDMA1>;
817 mediatek,larb = <&larb4>;
820 mdp_rsz0: rsz@14003000 {
821 compatible = "mediatek,mt8173-mdp-rsz";
822 reg = <0 0x14003000 0 0x1000>;
823 clocks = <&mmsys CLK_MM_MDP_RSZ0>;
824 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
827 mdp_rsz1: rsz@14004000 {
828 compatible = "mediatek,mt8173-mdp-rsz";
829 reg = <0 0x14004000 0 0x1000>;
830 clocks = <&mmsys CLK_MM_MDP_RSZ1>;
831 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
834 mdp_rsz2: rsz@14005000 {
835 compatible = "mediatek,mt8173-mdp-rsz";
836 reg = <0 0x14005000 0 0x1000>;
837 clocks = <&mmsys CLK_MM_MDP_RSZ2>;
838 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
841 mdp_wdma0: wdma@14006000 {
842 compatible = "mediatek,mt8173-mdp-wdma";
843 reg = <0 0x14006000 0 0x1000>;
844 clocks = <&mmsys CLK_MM_MDP_WDMA>;
845 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
846 iommus = <&iommu M4U_PORT_MDP_WDMA>;
847 mediatek,larb = <&larb0>;
850 mdp_wrot0: wrot@14007000 {
851 compatible = "mediatek,mt8173-mdp-wrot";
852 reg = <0 0x14007000 0 0x1000>;
853 clocks = <&mmsys CLK_MM_MDP_WROT0>;
854 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
855 iommus = <&iommu M4U_PORT_MDP_WROT0>;
856 mediatek,larb = <&larb0>;
859 mdp_wrot1: wrot@14008000 {
860 compatible = "mediatek,mt8173-mdp-wrot";
861 reg = <0 0x14008000 0 0x1000>;
862 clocks = <&mmsys CLK_MM_MDP_WROT1>;
863 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
864 iommus = <&iommu M4U_PORT_MDP_WROT1>;
865 mediatek,larb = <&larb4>;
870 compatible = "mediatek,mt8173-disp-ovl";
871 reg = <0 0x1400c000 0 0x1000>;
872 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>;
873 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
874 clocks = <&mmsys CLK_MM_DISP_OVL0>;
875 iommus = <&iommu M4U_PORT_DISP_OVL0>;
876 mediatek,larb = <&larb0>;
880 compatible = "mediatek,mt8173-disp-ovl";
881 reg = <0 0x1400d000 0 0x1000>;
882 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_LOW>;
883 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
884 clocks = <&mmsys CLK_MM_DISP_OVL1>;
885 iommus = <&iommu M4U_PORT_DISP_OVL1>;
886 mediatek,larb = <&larb4>;
889 rdma0: rdma@1400e000 {
890 compatible = "mediatek,mt8173-disp-rdma";
891 reg = <0 0x1400e000 0 0x1000>;
892 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>;
893 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
894 clocks = <&mmsys CLK_MM_DISP_RDMA0>;
895 iommus = <&iommu M4U_PORT_DISP_RDMA0>;
896 mediatek,larb = <&larb0>;
899 rdma1: rdma@1400f000 {
900 compatible = "mediatek,mt8173-disp-rdma";
901 reg = <0 0x1400f000 0 0x1000>;
902 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_LOW>;
903 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
904 clocks = <&mmsys CLK_MM_DISP_RDMA1>;
905 iommus = <&iommu M4U_PORT_DISP_RDMA1>;
906 mediatek,larb = <&larb4>;
909 rdma2: rdma@14010000 {
910 compatible = "mediatek,mt8173-disp-rdma";
911 reg = <0 0x14010000 0 0x1000>;
912 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_LOW>;
913 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
914 clocks = <&mmsys CLK_MM_DISP_RDMA2>;
915 iommus = <&iommu M4U_PORT_DISP_RDMA2>;
916 mediatek,larb = <&larb4>;
919 wdma0: wdma@14011000 {
920 compatible = "mediatek,mt8173-disp-wdma";
921 reg = <0 0x14011000 0 0x1000>;
922 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>;
923 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
924 clocks = <&mmsys CLK_MM_DISP_WDMA0>;
925 iommus = <&iommu M4U_PORT_DISP_WDMA0>;
926 mediatek,larb = <&larb0>;
929 wdma1: wdma@14012000 {
930 compatible = "mediatek,mt8173-disp-wdma";
931 reg = <0 0x14012000 0 0x1000>;
932 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_LOW>;
933 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
934 clocks = <&mmsys CLK_MM_DISP_WDMA1>;
935 iommus = <&iommu M4U_PORT_DISP_WDMA1>;
936 mediatek,larb = <&larb4>;
939 color0: color@14013000 {
940 compatible = "mediatek,mt8173-disp-color";
941 reg = <0 0x14013000 0 0x1000>;
942 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>;
943 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
944 clocks = <&mmsys CLK_MM_DISP_COLOR0>;
947 color1: color@14014000 {
948 compatible = "mediatek,mt8173-disp-color";
949 reg = <0 0x14014000 0 0x1000>;
950 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_LOW>;
951 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
952 clocks = <&mmsys CLK_MM_DISP_COLOR1>;
956 compatible = "mediatek,mt8173-disp-aal";
957 reg = <0 0x14015000 0 0x1000>;
958 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>;
959 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
960 clocks = <&mmsys CLK_MM_DISP_AAL>;
964 compatible = "mediatek,mt8173-disp-gamma";
965 reg = <0 0x14016000 0 0x1000>;
966 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>;
967 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
968 clocks = <&mmsys CLK_MM_DISP_GAMMA>;
972 compatible = "mediatek,mt8173-disp-merge";
973 reg = <0 0x14017000 0 0x1000>;
974 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
975 clocks = <&mmsys CLK_MM_DISP_MERGE>;
978 split0: split@14018000 {
979 compatible = "mediatek,mt8173-disp-split";
980 reg = <0 0x14018000 0 0x1000>;
981 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
982 clocks = <&mmsys CLK_MM_DISP_SPLIT0>;
985 split1: split@14019000 {
986 compatible = "mediatek,mt8173-disp-split";
987 reg = <0 0x14019000 0 0x1000>;
988 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
989 clocks = <&mmsys CLK_MM_DISP_SPLIT1>;
993 compatible = "mediatek,mt8173-disp-ufoe";
994 reg = <0 0x1401a000 0 0x1000>;
995 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>;
996 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
997 clocks = <&mmsys CLK_MM_DISP_UFOE>;
1000 dsi0: dsi@1401b000 {
1001 compatible = "mediatek,mt8173-dsi";
1002 reg = <0 0x1401b000 0 0x1000>;
1003 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_LOW>;
1004 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1005 clocks = <&mmsys CLK_MM_DSI0_ENGINE>,
1006 <&mmsys CLK_MM_DSI0_DIGITAL>,
1008 clock-names = "engine", "digital", "hs";
1011 status = "disabled";
1014 dsi1: dsi@1401c000 {
1015 compatible = "mediatek,mt8173-dsi";
1016 reg = <0 0x1401c000 0 0x1000>;
1017 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>;
1018 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1019 clocks = <&mmsys CLK_MM_DSI1_ENGINE>,
1020 <&mmsys CLK_MM_DSI1_DIGITAL>,
1022 clock-names = "engine", "digital", "hs";
1025 status = "disabled";
1028 dpi0: dpi@1401d000 {
1029 compatible = "mediatek,mt8173-dpi";
1030 reg = <0 0x1401d000 0 0x1000>;
1031 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
1032 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1033 clocks = <&mmsys CLK_MM_DPI_PIXEL>,
1034 <&mmsys CLK_MM_DPI_ENGINE>,
1035 <&apmixedsys CLK_APMIXED_TVDPLL>;
1036 clock-names = "pixel", "engine", "pll";
1037 status = "disabled";
1040 dpi0_out: endpoint {
1041 remote-endpoint = <&hdmi0_in>;
1046 pwm0: pwm@1401e000 {
1047 compatible = "mediatek,mt8173-disp-pwm",
1048 "mediatek,mt6595-disp-pwm";
1049 reg = <0 0x1401e000 0 0x1000>;
1051 clocks = <&mmsys CLK_MM_DISP_PWM026M>,
1052 <&mmsys CLK_MM_DISP_PWM0MM>;
1053 clock-names = "main", "mm";
1054 status = "disabled";
1057 pwm1: pwm@1401f000 {
1058 compatible = "mediatek,mt8173-disp-pwm",
1059 "mediatek,mt6595-disp-pwm";
1060 reg = <0 0x1401f000 0 0x1000>;
1062 clocks = <&mmsys CLK_MM_DISP_PWM126M>,
1063 <&mmsys CLK_MM_DISP_PWM1MM>;
1064 clock-names = "main", "mm";
1065 status = "disabled";
1068 mutex: mutex@14020000 {
1069 compatible = "mediatek,mt8173-disp-mutex";
1070 reg = <0 0x14020000 0 0x1000>;
1071 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>;
1072 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1073 clocks = <&mmsys CLK_MM_MUTEX_32K>;
1076 larb0: larb@14021000 {
1077 compatible = "mediatek,mt8173-smi-larb";
1078 reg = <0 0x14021000 0 0x1000>;
1079 mediatek,smi = <&smi_common>;
1080 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1081 clocks = <&mmsys CLK_MM_SMI_LARB0>,
1082 <&mmsys CLK_MM_SMI_LARB0>;
1083 clock-names = "apb", "smi";
1086 smi_common: smi@14022000 {
1087 compatible = "mediatek,mt8173-smi-common";
1088 reg = <0 0x14022000 0 0x1000>;
1089 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1090 clocks = <&mmsys CLK_MM_SMI_COMMON>,
1091 <&mmsys CLK_MM_SMI_COMMON>;
1092 clock-names = "apb", "smi";
1096 compatible = "mediatek,mt8173-disp-od";
1097 reg = <0 0x14023000 0 0x1000>;
1098 clocks = <&mmsys CLK_MM_DISP_OD>;
1101 hdmi0: hdmi@14025000 {
1102 compatible = "mediatek,mt8173-hdmi";
1103 reg = <0 0x14025000 0 0x400>;
1104 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_LOW>;
1105 clocks = <&mmsys CLK_MM_HDMI_PIXEL>,
1106 <&mmsys CLK_MM_HDMI_PLLCK>,
1107 <&mmsys CLK_MM_HDMI_AUDIO>,
1108 <&mmsys CLK_MM_HDMI_SPDIF>;
1109 clock-names = "pixel", "pll", "bclk", "spdif";
1110 pinctrl-names = "default";
1111 pinctrl-0 = <&hdmi_pin>;
1114 mediatek,syscon-hdmi = <&mmsys 0x900>;
1115 assigned-clocks = <&topckgen CLK_TOP_HDMI_SEL>;
1116 assigned-clock-parents = <&hdmi_phy>;
1117 status = "disabled";
1120 #address-cells = <1>;
1126 hdmi0_in: endpoint {
1127 remote-endpoint = <&dpi0_out>;
1133 larb4: larb@14027000 {
1134 compatible = "mediatek,mt8173-smi-larb";
1135 reg = <0 0x14027000 0 0x1000>;
1136 mediatek,smi = <&smi_common>;
1137 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1138 clocks = <&mmsys CLK_MM_SMI_LARB4>,
1139 <&mmsys CLK_MM_SMI_LARB4>;
1140 clock-names = "apb", "smi";
1143 imgsys: clock-controller@15000000 {
1144 compatible = "mediatek,mt8173-imgsys", "syscon";
1145 reg = <0 0x15000000 0 0x1000>;
1149 larb2: larb@15001000 {
1150 compatible = "mediatek,mt8173-smi-larb";
1151 reg = <0 0x15001000 0 0x1000>;
1152 mediatek,smi = <&smi_common>;
1153 power-domains = <&scpsys MT8173_POWER_DOMAIN_ISP>;
1154 clocks = <&imgsys CLK_IMG_LARB2_SMI>,
1155 <&imgsys CLK_IMG_LARB2_SMI>;
1156 clock-names = "apb", "smi";
1159 vdecsys: clock-controller@16000000 {
1160 compatible = "mediatek,mt8173-vdecsys", "syscon";
1161 reg = <0 0x16000000 0 0x1000>;
1165 vcodec_dec: vcodec@16000000 {
1166 compatible = "mediatek,mt8173-vcodec-dec";
1167 reg = <0 0x16000000 0 0x100>, /* VDEC_SYS */
1168 <0 0x16020000 0 0x1000>, /* VDEC_MISC */
1169 <0 0x16021000 0 0x800>, /* VDEC_LD */
1170 <0 0x16021800 0 0x800>, /* VDEC_TOP */
1171 <0 0x16022000 0 0x1000>, /* VDEC_CM */
1172 <0 0x16023000 0 0x1000>, /* VDEC_AD */
1173 <0 0x16024000 0 0x1000>, /* VDEC_AV */
1174 <0 0x16025000 0 0x1000>, /* VDEC_PP */
1175 <0 0x16026800 0 0x800>, /* VDEC_HWD */
1176 <0 0x16027000 0 0x800>, /* VDEC_HWQ */
1177 <0 0x16027800 0 0x800>, /* VDEC_HWB */
1178 <0 0x16028400 0 0x400>; /* VDEC_HWG */
1179 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_LOW>;
1180 mediatek,larb = <&larb1>;
1181 iommus = <&iommu M4U_PORT_HW_VDEC_MC_EXT>,
1182 <&iommu M4U_PORT_HW_VDEC_PP_EXT>,
1183 <&iommu M4U_PORT_HW_VDEC_AVC_MV_EXT>,
1184 <&iommu M4U_PORT_HW_VDEC_PRED_RD_EXT>,
1185 <&iommu M4U_PORT_HW_VDEC_PRED_WR_EXT>,
1186 <&iommu M4U_PORT_HW_VDEC_UFO_EXT>,
1187 <&iommu M4U_PORT_HW_VDEC_VLD_EXT>,
1188 <&iommu M4U_PORT_HW_VDEC_VLD2_EXT>;
1189 mediatek,vpu = <&vpu>;
1190 power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>;
1191 clocks = <&apmixedsys CLK_APMIXED_VCODECPLL>,
1192 <&topckgen CLK_TOP_UNIVPLL_D2>,
1193 <&topckgen CLK_TOP_CCI400_SEL>,
1194 <&topckgen CLK_TOP_VDEC_SEL>,
1195 <&topckgen CLK_TOP_VCODECPLL>,
1196 <&apmixedsys CLK_APMIXED_VENCPLL>,
1197 <&topckgen CLK_TOP_VENC_LT_SEL>,
1198 <&topckgen CLK_TOP_VCODECPLL_370P5>;
1199 clock-names = "vcodecpll",
1209 larb1: larb@16010000 {
1210 compatible = "mediatek,mt8173-smi-larb";
1211 reg = <0 0x16010000 0 0x1000>;
1212 mediatek,smi = <&smi_common>;
1213 power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>;
1214 clocks = <&vdecsys CLK_VDEC_CKEN>,
1215 <&vdecsys CLK_VDEC_LARB_CKEN>;
1216 clock-names = "apb", "smi";
1219 vencsys: clock-controller@18000000 {
1220 compatible = "mediatek,mt8173-vencsys", "syscon";
1221 reg = <0 0x18000000 0 0x1000>;
1225 larb3: larb@18001000 {
1226 compatible = "mediatek,mt8173-smi-larb";
1227 reg = <0 0x18001000 0 0x1000>;
1228 mediatek,smi = <&smi_common>;
1229 power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC>;
1230 clocks = <&vencsys CLK_VENC_CKE1>,
1231 <&vencsys CLK_VENC_CKE0>;
1232 clock-names = "apb", "smi";
1235 vcodec_enc: vcodec@18002000 {
1236 compatible = "mediatek,mt8173-vcodec-enc";
1237 reg = <0 0x18002000 0 0x1000>, /* VENC_SYS */
1238 <0 0x19002000 0 0x1000>; /* VENC_LT_SYS */
1239 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>,
1240 <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>;
1241 mediatek,larb = <&larb3>,
1243 iommus = <&iommu M4U_PORT_VENC_RCPU>,
1244 <&iommu M4U_PORT_VENC_REC>,
1245 <&iommu M4U_PORT_VENC_BSDMA>,
1246 <&iommu M4U_PORT_VENC_SV_COMV>,
1247 <&iommu M4U_PORT_VENC_RD_COMV>,
1248 <&iommu M4U_PORT_VENC_CUR_LUMA>,
1249 <&iommu M4U_PORT_VENC_CUR_CHROMA>,
1250 <&iommu M4U_PORT_VENC_REF_LUMA>,
1251 <&iommu M4U_PORT_VENC_REF_CHROMA>,
1252 <&iommu M4U_PORT_VENC_NBM_RDMA>,
1253 <&iommu M4U_PORT_VENC_NBM_WDMA>,
1254 <&iommu M4U_PORT_VENC_RCPU_SET2>,
1255 <&iommu M4U_PORT_VENC_REC_FRM_SET2>,
1256 <&iommu M4U_PORT_VENC_BSDMA_SET2>,
1257 <&iommu M4U_PORT_VENC_SV_COMA_SET2>,
1258 <&iommu M4U_PORT_VENC_RD_COMA_SET2>,
1259 <&iommu M4U_PORT_VENC_CUR_LUMA_SET2>,
1260 <&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>,
1261 <&iommu M4U_PORT_VENC_REF_LUMA_SET2>,
1262 <&iommu M4U_PORT_VENC_REC_CHROMA_SET2>;
1263 mediatek,vpu = <&vpu>;
1264 clocks = <&topckgen CLK_TOP_VENCPLL_D2>,
1265 <&topckgen CLK_TOP_VENC_SEL>,
1266 <&topckgen CLK_TOP_UNIVPLL1_D2>,
1267 <&topckgen CLK_TOP_VENC_LT_SEL>;
1268 clock-names = "venc_sel_src",
1274 vencltsys: clock-controller@19000000 {
1275 compatible = "mediatek,mt8173-vencltsys", "syscon";
1276 reg = <0 0x19000000 0 0x1000>;
1280 larb5: larb@19001000 {
1281 compatible = "mediatek,mt8173-smi-larb";
1282 reg = <0 0x19001000 0 0x1000>;
1283 mediatek,smi = <&smi_common>;
1284 power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC_LT>;
1285 clocks = <&vencltsys CLK_VENCLT_CKE1>,
1286 <&vencltsys CLK_VENCLT_CKE0>;
1287 clock-names = "apb", "smi";