2 * Copyright (c) 2014 MediaTek Inc.
3 * Author: Eddie Huang <eddie.huang@mediatek.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #include <dt-bindings/clock/mt8173-clk.h>
15 #include <dt-bindings/interrupt-controller/irq.h>
16 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 #include <dt-bindings/memory/mt8173-larb-port.h>
18 #include <dt-bindings/phy/phy.h>
19 #include <dt-bindings/power/mt8173-power.h>
20 #include <dt-bindings/reset/mt8173-resets.h>
21 #include "mt8173-pinfunc.h"
24 compatible = "mediatek,mt8173";
25 interrupt-parent = <&sysirq>;
44 mdp_rdma0 = &mdp_rdma0;
45 mdp_rdma1 = &mdp_rdma1;
49 mdp_wdma0 = &mdp_wdma0;
50 mdp_wrot0 = &mdp_wrot0;
51 mdp_wrot1 = &mdp_wrot1;
80 compatible = "arm,cortex-a53";
82 enable-method = "psci";
83 cpu-idle-states = <&CPU_SLEEP_0>;
88 compatible = "arm,cortex-a53";
90 enable-method = "psci";
91 cpu-idle-states = <&CPU_SLEEP_0>;
96 compatible = "arm,cortex-a57";
98 enable-method = "psci";
99 cpu-idle-states = <&CPU_SLEEP_0>;
104 compatible = "arm,cortex-a57";
106 enable-method = "psci";
107 cpu-idle-states = <&CPU_SLEEP_0>;
111 entry-method = "psci";
113 CPU_SLEEP_0: cpu-sleep-0 {
114 compatible = "arm,idle-state";
116 entry-latency-us = <639>;
117 exit-latency-us = <680>;
118 min-residency-us = <1088>;
119 arm,psci-suspend-param = <0x0010000>;
125 compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci";
127 cpu_suspend = <0x84000001>;
128 cpu_off = <0x84000002>;
129 cpu_on = <0x84000003>;
132 clk26m: oscillator@0 {
133 compatible = "fixed-clock";
135 clock-frequency = <26000000>;
136 clock-output-names = "clk26m";
139 clk32k: oscillator@1 {
140 compatible = "fixed-clock";
142 clock-frequency = <32000>;
143 clock-output-names = "clk32k";
146 cpum_ck: oscillator@2 {
147 compatible = "fixed-clock";
149 clock-frequency = <0>;
150 clock-output-names = "cpum_ck";
154 cpu_thermal: cpu_thermal {
155 polling-delay-passive = <1000>; /* milliseconds */
156 polling-delay = <1000>; /* milliseconds */
158 thermal-sensors = <&thermal>;
159 sustainable-power = <1500>; /* milliwatts */
162 threshold: trip-point@0 {
163 temperature = <68000>;
168 target: trip-point@1 {
169 temperature = <85000>;
174 cpu_crit: cpu_crit@0 {
175 temperature = <115000>;
184 cooling-device = <&cpu0 0 0>;
185 contribution = <1024>;
189 cooling-device = <&cpu2 0 0>;
190 contribution = <2048>;
197 #address-cells = <2>;
200 vpu_dma_reserved: vpu_dma_mem_region {
201 compatible = "shared-dma-pool";
202 reg = <0 0xb7000000 0 0x500000>;
203 alignment = <0x1000>;
209 compatible = "arm,armv8-timer";
210 interrupt-parent = <&gic>;
211 interrupts = <GIC_PPI 13
212 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
214 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
216 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
218 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
222 #address-cells = <2>;
224 compatible = "simple-bus";
227 topckgen: clock-controller@10000000 {
228 compatible = "mediatek,mt8173-topckgen";
229 reg = <0 0x10000000 0 0x1000>;
233 infracfg: power-controller@10001000 {
234 compatible = "mediatek,mt8173-infracfg", "syscon";
235 reg = <0 0x10001000 0 0x1000>;
240 pericfg: power-controller@10003000 {
241 compatible = "mediatek,mt8173-pericfg", "syscon";
242 reg = <0 0x10003000 0 0x1000>;
247 syscfg_pctl_a: syscfg_pctl_a@10005000 {
248 compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon";
249 reg = <0 0x10005000 0 0x1000>;
252 pio: pinctrl@0x10005000 {
253 compatible = "mediatek,mt8173-pinctrl";
254 reg = <0 0x1000b000 0 0x1000>;
255 mediatek,pctl-regmap = <&syscfg_pctl_a>;
259 interrupt-controller;
260 #interrupt-cells = <2>;
261 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
262 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
263 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
269 pinmux = <MT8173_PIN_21_HTPLG__FUNC_HTPLG>;
277 pinmux = <MT8173_PIN_45_SDA0__FUNC_SDA0>,
278 <MT8173_PIN_46_SCL0__FUNC_SCL0>;
285 pinmux = <MT8173_PIN_125_SDA1__FUNC_SDA1>,
286 <MT8173_PIN_126_SCL1__FUNC_SCL1>;
293 pinmux = <MT8173_PIN_43_SDA2__FUNC_SDA2>,
294 <MT8173_PIN_44_SCL2__FUNC_SCL2>;
301 pinmux = <MT8173_PIN_106_SDA3__FUNC_SDA3>,
302 <MT8173_PIN_107_SCL3__FUNC_SCL3>;
309 pinmux = <MT8173_PIN_133_SDA4__FUNC_SDA4>,
310 <MT8173_PIN_134_SCL4__FUNC_SCL4>;
317 pinmux = <MT8173_PIN_100_MSDC2_DAT0__FUNC_SDA5>,
318 <MT8173_PIN_101_MSDC2_DAT1__FUNC_SCL5>;
324 scpsys: scpsys@10006000 {
325 compatible = "mediatek,mt8173-scpsys";
326 #power-domain-cells = <1>;
327 reg = <0 0x10006000 0 0x1000>;
329 <&topckgen CLK_TOP_MM_SEL>,
330 <&topckgen CLK_TOP_VENC_SEL>,
331 <&topckgen CLK_TOP_VENC_LT_SEL>;
332 clock-names = "mfg", "mm", "venc", "venc_lt";
333 infracfg = <&infracfg>;
336 watchdog: watchdog@10007000 {
337 compatible = "mediatek,mt8173-wdt",
338 "mediatek,mt6589-wdt";
339 reg = <0 0x10007000 0 0x100>;
342 timer: timer@10008000 {
343 compatible = "mediatek,mt8173-timer",
344 "mediatek,mt6577-timer";
345 reg = <0 0x10008000 0 0x1000>;
346 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>;
347 clocks = <&infracfg CLK_INFRA_CLK_13M>,
348 <&topckgen CLK_TOP_RTC_SEL>;
351 pwrap: pwrap@1000d000 {
352 compatible = "mediatek,mt8173-pwrap";
353 reg = <0 0x1000d000 0 0x1000>;
355 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
356 resets = <&infracfg MT8173_INFRA_PMIC_WRAP_RST>;
357 reset-names = "pwrap";
358 clocks = <&infracfg CLK_INFRA_PMICSPI>, <&infracfg CLK_INFRA_PMICWRAP>;
359 clock-names = "spi", "wrap";
363 compatible = "mediatek,mt8173-cec";
364 reg = <0 0x10013000 0 0xbc>;
365 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>;
366 clocks = <&infracfg CLK_INFRA_CEC>;
371 compatible = "mediatek,mt8173-vpu";
372 reg = <0 0x10020000 0 0x30000>,
373 <0 0x10050000 0 0x100>;
374 reg-names = "tcm", "cfg_reg";
375 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
376 clocks = <&topckgen CLK_TOP_SCP_SEL>;
377 clock-names = "main";
378 memory-region = <&vpu_dma_reserved>;
381 sysirq: intpol-controller@10200620 {
382 compatible = "mediatek,mt8173-sysirq",
383 "mediatek,mt6577-sysirq";
384 interrupt-controller;
385 #interrupt-cells = <3>;
386 interrupt-parent = <&gic>;
387 reg = <0 0x10200620 0 0x20>;
390 iommu: iommu@10205000 {
391 compatible = "mediatek,mt8173-m4u";
392 reg = <0 0x10205000 0 0x1000>;
393 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>;
394 clocks = <&infracfg CLK_INFRA_M4U>;
395 clock-names = "bclk";
396 mediatek,larbs = <&larb0 &larb1 &larb2
397 &larb3 &larb4 &larb5>;
401 efuse: efuse@10206000 {
402 compatible = "mediatek,mt8173-efuse";
403 reg = <0 0x10206000 0 0x1000>;
406 apmixedsys: clock-controller@10209000 {
407 compatible = "mediatek,mt8173-apmixedsys";
408 reg = <0 0x10209000 0 0x1000>;
412 hdmi_phy: hdmi-phy@10209100 {
413 compatible = "mediatek,mt8173-hdmi-phy";
414 reg = <0 0x10209100 0 0x24>;
415 clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>;
416 clock-names = "pll_ref";
417 clock-output-names = "hdmitx_dig_cts";
418 mediatek,ibias = <0xa>;
419 mediatek,ibias_up = <0x1c>;
425 mipi_tx0: mipi-dphy@10215000 {
426 compatible = "mediatek,mt8173-mipi-tx";
427 reg = <0 0x10215000 0 0x1000>;
429 clock-output-names = "mipi_tx0_pll";
435 mipi_tx1: mipi-dphy@10216000 {
436 compatible = "mediatek,mt8173-mipi-tx";
437 reg = <0 0x10216000 0 0x1000>;
439 clock-output-names = "mipi_tx1_pll";
445 gic: interrupt-controller@10220000 {
446 compatible = "arm,gic-400";
447 #interrupt-cells = <3>;
448 interrupt-parent = <&gic>;
449 interrupt-controller;
450 reg = <0 0x10221000 0 0x1000>,
451 <0 0x10222000 0 0x2000>,
452 <0 0x10224000 0 0x2000>,
453 <0 0x10226000 0 0x2000>;
454 interrupts = <GIC_PPI 9
455 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
458 auxadc: auxadc@11001000 {
459 compatible = "mediatek,mt8173-auxadc";
460 reg = <0 0x11001000 0 0x1000>;
461 clocks = <&pericfg CLK_PERI_AUXADC>;
462 clock-names = "main";
463 #io-channel-cells = <1>;
466 uart0: serial@11002000 {
467 compatible = "mediatek,mt8173-uart",
468 "mediatek,mt6577-uart";
469 reg = <0 0x11002000 0 0x400>;
470 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>;
471 clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>;
472 clock-names = "baud", "bus";
476 uart1: serial@11003000 {
477 compatible = "mediatek,mt8173-uart",
478 "mediatek,mt6577-uart";
479 reg = <0 0x11003000 0 0x400>;
480 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
481 clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>;
482 clock-names = "baud", "bus";
486 uart2: serial@11004000 {
487 compatible = "mediatek,mt8173-uart",
488 "mediatek,mt6577-uart";
489 reg = <0 0x11004000 0 0x400>;
490 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
491 clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>;
492 clock-names = "baud", "bus";
496 uart3: serial@11005000 {
497 compatible = "mediatek,mt8173-uart",
498 "mediatek,mt6577-uart";
499 reg = <0 0x11005000 0 0x400>;
500 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
501 clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>;
502 clock-names = "baud", "bus";
507 compatible = "mediatek,mt8173-i2c";
508 reg = <0 0x11007000 0 0x70>,
509 <0 0x11000100 0 0x80>;
510 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>;
512 clocks = <&pericfg CLK_PERI_I2C0>,
513 <&pericfg CLK_PERI_AP_DMA>;
514 clock-names = "main", "dma";
515 pinctrl-names = "default";
516 pinctrl-0 = <&i2c0_pins_a>;
517 #address-cells = <1>;
523 compatible = "mediatek,mt8173-i2c";
524 reg = <0 0x11008000 0 0x70>,
525 <0 0x11000180 0 0x80>;
526 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
528 clocks = <&pericfg CLK_PERI_I2C1>,
529 <&pericfg CLK_PERI_AP_DMA>;
530 clock-names = "main", "dma";
531 pinctrl-names = "default";
532 pinctrl-0 = <&i2c1_pins_a>;
533 #address-cells = <1>;
539 compatible = "mediatek,mt8173-i2c";
540 reg = <0 0x11009000 0 0x70>,
541 <0 0x11000200 0 0x80>;
542 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
544 clocks = <&pericfg CLK_PERI_I2C2>,
545 <&pericfg CLK_PERI_AP_DMA>;
546 clock-names = "main", "dma";
547 pinctrl-names = "default";
548 pinctrl-0 = <&i2c2_pins_a>;
549 #address-cells = <1>;
555 compatible = "mediatek,mt8173-spi";
556 #address-cells = <1>;
558 reg = <0 0x1100a000 0 0x1000>;
559 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>;
560 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
561 <&topckgen CLK_TOP_SPI_SEL>,
562 <&pericfg CLK_PERI_SPI0>;
563 clock-names = "parent-clk", "sel-clk", "spi-clk";
567 thermal: thermal@1100b000 {
568 #thermal-sensor-cells = <0>;
569 compatible = "mediatek,mt8173-thermal";
570 reg = <0 0x1100b000 0 0x1000>;
571 interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>;
572 clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>;
573 clock-names = "therm", "auxadc";
574 resets = <&pericfg MT8173_PERI_THERM_SW_RST>;
575 mediatek,auxadc = <&auxadc>;
576 mediatek,apmixedsys = <&apmixedsys>;
579 nor_flash: spi@1100d000 {
580 compatible = "mediatek,mt8173-nor";
581 reg = <0 0x1100d000 0 0xe0>;
582 clocks = <&pericfg CLK_PERI_SPI>,
583 <&topckgen CLK_TOP_SPINFI_IFR_SEL>;
584 clock-names = "spi", "sf";
585 #address-cells = <1>;
591 compatible = "mediatek,mt8173-i2c";
592 reg = <0 0x11010000 0 0x70>,
593 <0 0x11000280 0 0x80>;
594 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
596 clocks = <&pericfg CLK_PERI_I2C3>,
597 <&pericfg CLK_PERI_AP_DMA>;
598 clock-names = "main", "dma";
599 pinctrl-names = "default";
600 pinctrl-0 = <&i2c3_pins_a>;
601 #address-cells = <1>;
607 compatible = "mediatek,mt8173-i2c";
608 reg = <0 0x11011000 0 0x70>,
609 <0 0x11000300 0 0x80>;
610 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>;
612 clocks = <&pericfg CLK_PERI_I2C4>,
613 <&pericfg CLK_PERI_AP_DMA>;
614 clock-names = "main", "dma";
615 pinctrl-names = "default";
616 pinctrl-0 = <&i2c4_pins_a>;
617 #address-cells = <1>;
622 hdmiddc0: i2c@11012000 {
623 compatible = "mediatek,mt8173-hdmi-ddc";
624 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>;
625 reg = <0 0x11012000 0 0x1C>;
626 clocks = <&pericfg CLK_PERI_I2C5>;
627 clock-names = "ddc-i2c";
631 compatible = "mediatek,mt8173-i2c";
632 reg = <0 0x11013000 0 0x70>,
633 <0 0x11000080 0 0x80>;
634 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>;
636 clocks = <&pericfg CLK_PERI_I2C6>,
637 <&pericfg CLK_PERI_AP_DMA>;
638 clock-names = "main", "dma";
639 pinctrl-names = "default";
640 pinctrl-0 = <&i2c6_pins_a>;
641 #address-cells = <1>;
646 afe: audio-controller@11220000 {
647 compatible = "mediatek,mt8173-afe-pcm";
648 reg = <0 0x11220000 0 0x1000>;
649 interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_FALLING>;
650 power-domains = <&scpsys MT8173_POWER_DOMAIN_AUDIO>;
651 clocks = <&infracfg CLK_INFRA_AUDIO>,
652 <&topckgen CLK_TOP_AUDIO_SEL>,
653 <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
654 <&topckgen CLK_TOP_APLL1_DIV0>,
655 <&topckgen CLK_TOP_APLL2_DIV0>,
656 <&topckgen CLK_TOP_I2S0_M_SEL>,
657 <&topckgen CLK_TOP_I2S1_M_SEL>,
658 <&topckgen CLK_TOP_I2S2_M_SEL>,
659 <&topckgen CLK_TOP_I2S3_M_SEL>,
660 <&topckgen CLK_TOP_I2S3_B_SEL>;
661 clock-names = "infra_sys_audio_clk",
663 "top_pdn_aud_intbus",
671 assigned-clocks = <&topckgen CLK_TOP_AUD_1_SEL>,
672 <&topckgen CLK_TOP_AUD_2_SEL>;
673 assigned-clock-parents = <&topckgen CLK_TOP_APLL1>,
674 <&topckgen CLK_TOP_APLL2>;
678 compatible = "mediatek,mt8173-mmc",
679 "mediatek,mt8135-mmc";
680 reg = <0 0x11230000 0 0x1000>;
681 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_LOW>;
682 clocks = <&pericfg CLK_PERI_MSDC30_0>,
683 <&topckgen CLK_TOP_MSDC50_0_H_SEL>;
684 clock-names = "source", "hclk";
689 compatible = "mediatek,mt8173-mmc",
690 "mediatek,mt8135-mmc";
691 reg = <0 0x11240000 0 0x1000>;
692 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>;
693 clocks = <&pericfg CLK_PERI_MSDC30_1>,
694 <&topckgen CLK_TOP_AXI_SEL>;
695 clock-names = "source", "hclk";
700 compatible = "mediatek,mt8173-mmc",
701 "mediatek,mt8135-mmc";
702 reg = <0 0x11250000 0 0x1000>;
703 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_LOW>;
704 clocks = <&pericfg CLK_PERI_MSDC30_2>,
705 <&topckgen CLK_TOP_AXI_SEL>;
706 clock-names = "source", "hclk";
711 compatible = "mediatek,mt8173-mmc",
712 "mediatek,mt8135-mmc";
713 reg = <0 0x11260000 0 0x1000>;
714 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_LOW>;
715 clocks = <&pericfg CLK_PERI_MSDC30_3>,
716 <&topckgen CLK_TOP_MSDC50_2_H_SEL>;
717 clock-names = "source", "hclk";
721 ssusb: usb@11271000 {
722 compatible = "mediatek,mt8173-mtu3";
723 reg = <0 0x11271000 0 0x3000>,
724 <0 0x11280700 0 0x0100>;
725 reg-names = "mac", "ippc";
726 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_LOW>;
727 phys = <&phy_port0 PHY_TYPE_USB3>,
728 <&phy_port1 PHY_TYPE_USB2>;
729 power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>;
730 clocks = <&topckgen CLK_TOP_USB30_SEL>,
731 <&pericfg CLK_PERI_USB0>,
732 <&pericfg CLK_PERI_USB1>;
733 clock-names = "sys_ck",
736 mediatek,syscon-wakeup = <&pericfg>;
737 #address-cells = <2>;
742 usb_host: xhci@11270000 {
743 compatible = "mediatek,mt8173-xhci";
744 reg = <0 0x11270000 0 0x1000>;
746 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>;
747 power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>;
748 clocks = <&topckgen CLK_TOP_USB30_SEL>;
749 clock-names = "sys_ck";
754 u3phy: usb-phy@11290000 {
755 compatible = "mediatek,mt8173-u3phy";
756 reg = <0 0x11290000 0 0x800>;
757 clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;
758 clock-names = "u3phya_ref";
759 #address-cells = <2>;
764 phy_port0: port@11290800 {
765 reg = <0 0x11290800 0 0x800>;
770 phy_port1: port@11291000 {
771 reg = <0 0x11291000 0 0x800>;
777 mmsys: clock-controller@14000000 {
778 compatible = "mediatek,mt8173-mmsys", "syscon";
779 reg = <0 0x14000000 0 0x1000>;
780 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
785 compatible = "mediatek,mt8173-mdp";
786 #address-cells = <2>;
789 mediatek,vpu = <&vpu>;
791 mdp_rdma0: rdma@14001000 {
792 compatible = "mediatek,mt8173-mdp-rdma";
793 reg = <0 0x14001000 0 0x1000>;
794 clocks = <&mmsys CLK_MM_MDP_RDMA0>,
795 <&mmsys CLK_MM_MUTEX_32K>;
796 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
797 iommus = <&iommu M4U_PORT_MDP_RDMA0>;
798 mediatek,larb = <&larb0>;
801 mdp_rdma1: rdma@14002000 {
802 compatible = "mediatek,mt8173-mdp-rdma";
803 reg = <0 0x14002000 0 0x1000>;
804 clocks = <&mmsys CLK_MM_MDP_RDMA1>,
805 <&mmsys CLK_MM_MUTEX_32K>;
806 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
807 iommus = <&iommu M4U_PORT_MDP_RDMA1>;
808 mediatek,larb = <&larb4>;
811 mdp_rsz0: rsz@14003000 {
812 compatible = "mediatek,mt8173-mdp-rsz";
813 reg = <0 0x14003000 0 0x1000>;
814 clocks = <&mmsys CLK_MM_MDP_RSZ0>;
815 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
818 mdp_rsz1: rsz@14004000 {
819 compatible = "mediatek,mt8173-mdp-rsz";
820 reg = <0 0x14004000 0 0x1000>;
821 clocks = <&mmsys CLK_MM_MDP_RSZ1>;
822 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
825 mdp_rsz2: rsz@14005000 {
826 compatible = "mediatek,mt8173-mdp-rsz";
827 reg = <0 0x14005000 0 0x1000>;
828 clocks = <&mmsys CLK_MM_MDP_RSZ2>;
829 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
832 mdp_wdma0: wdma@14006000 {
833 compatible = "mediatek,mt8173-mdp-wdma";
834 reg = <0 0x14006000 0 0x1000>;
835 clocks = <&mmsys CLK_MM_MDP_WDMA>;
836 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
837 iommus = <&iommu M4U_PORT_MDP_WDMA>;
838 mediatek,larb = <&larb0>;
841 mdp_wrot0: wrot@14007000 {
842 compatible = "mediatek,mt8173-mdp-wrot";
843 reg = <0 0x14007000 0 0x1000>;
844 clocks = <&mmsys CLK_MM_MDP_WROT0>;
845 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
846 iommus = <&iommu M4U_PORT_MDP_WROT0>;
847 mediatek,larb = <&larb0>;
850 mdp_wrot1: wrot@14008000 {
851 compatible = "mediatek,mt8173-mdp-wrot";
852 reg = <0 0x14008000 0 0x1000>;
853 clocks = <&mmsys CLK_MM_MDP_WROT1>;
854 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
855 iommus = <&iommu M4U_PORT_MDP_WROT1>;
856 mediatek,larb = <&larb4>;
861 compatible = "mediatek,mt8173-disp-ovl";
862 reg = <0 0x1400c000 0 0x1000>;
863 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>;
864 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
865 clocks = <&mmsys CLK_MM_DISP_OVL0>;
866 iommus = <&iommu M4U_PORT_DISP_OVL0>;
867 mediatek,larb = <&larb0>;
871 compatible = "mediatek,mt8173-disp-ovl";
872 reg = <0 0x1400d000 0 0x1000>;
873 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_LOW>;
874 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
875 clocks = <&mmsys CLK_MM_DISP_OVL1>;
876 iommus = <&iommu M4U_PORT_DISP_OVL1>;
877 mediatek,larb = <&larb4>;
880 rdma0: rdma@1400e000 {
881 compatible = "mediatek,mt8173-disp-rdma";
882 reg = <0 0x1400e000 0 0x1000>;
883 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>;
884 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
885 clocks = <&mmsys CLK_MM_DISP_RDMA0>;
886 iommus = <&iommu M4U_PORT_DISP_RDMA0>;
887 mediatek,larb = <&larb0>;
890 rdma1: rdma@1400f000 {
891 compatible = "mediatek,mt8173-disp-rdma";
892 reg = <0 0x1400f000 0 0x1000>;
893 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_LOW>;
894 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
895 clocks = <&mmsys CLK_MM_DISP_RDMA1>;
896 iommus = <&iommu M4U_PORT_DISP_RDMA1>;
897 mediatek,larb = <&larb4>;
900 rdma2: rdma@14010000 {
901 compatible = "mediatek,mt8173-disp-rdma";
902 reg = <0 0x14010000 0 0x1000>;
903 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_LOW>;
904 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
905 clocks = <&mmsys CLK_MM_DISP_RDMA2>;
906 iommus = <&iommu M4U_PORT_DISP_RDMA2>;
907 mediatek,larb = <&larb4>;
910 wdma0: wdma@14011000 {
911 compatible = "mediatek,mt8173-disp-wdma";
912 reg = <0 0x14011000 0 0x1000>;
913 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>;
914 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
915 clocks = <&mmsys CLK_MM_DISP_WDMA0>;
916 iommus = <&iommu M4U_PORT_DISP_WDMA0>;
917 mediatek,larb = <&larb0>;
920 wdma1: wdma@14012000 {
921 compatible = "mediatek,mt8173-disp-wdma";
922 reg = <0 0x14012000 0 0x1000>;
923 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_LOW>;
924 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
925 clocks = <&mmsys CLK_MM_DISP_WDMA1>;
926 iommus = <&iommu M4U_PORT_DISP_WDMA1>;
927 mediatek,larb = <&larb4>;
930 color0: color@14013000 {
931 compatible = "mediatek,mt8173-disp-color";
932 reg = <0 0x14013000 0 0x1000>;
933 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>;
934 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
935 clocks = <&mmsys CLK_MM_DISP_COLOR0>;
938 color1: color@14014000 {
939 compatible = "mediatek,mt8173-disp-color";
940 reg = <0 0x14014000 0 0x1000>;
941 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_LOW>;
942 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
943 clocks = <&mmsys CLK_MM_DISP_COLOR1>;
947 compatible = "mediatek,mt8173-disp-aal";
948 reg = <0 0x14015000 0 0x1000>;
949 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>;
950 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
951 clocks = <&mmsys CLK_MM_DISP_AAL>;
955 compatible = "mediatek,mt8173-disp-gamma";
956 reg = <0 0x14016000 0 0x1000>;
957 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>;
958 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
959 clocks = <&mmsys CLK_MM_DISP_GAMMA>;
963 compatible = "mediatek,mt8173-disp-merge";
964 reg = <0 0x14017000 0 0x1000>;
965 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
966 clocks = <&mmsys CLK_MM_DISP_MERGE>;
969 split0: split@14018000 {
970 compatible = "mediatek,mt8173-disp-split";
971 reg = <0 0x14018000 0 0x1000>;
972 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
973 clocks = <&mmsys CLK_MM_DISP_SPLIT0>;
976 split1: split@14019000 {
977 compatible = "mediatek,mt8173-disp-split";
978 reg = <0 0x14019000 0 0x1000>;
979 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
980 clocks = <&mmsys CLK_MM_DISP_SPLIT1>;
984 compatible = "mediatek,mt8173-disp-ufoe";
985 reg = <0 0x1401a000 0 0x1000>;
986 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>;
987 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
988 clocks = <&mmsys CLK_MM_DISP_UFOE>;
992 compatible = "mediatek,mt8173-dsi";
993 reg = <0 0x1401b000 0 0x1000>;
994 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_LOW>;
995 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
996 clocks = <&mmsys CLK_MM_DSI0_ENGINE>,
997 <&mmsys CLK_MM_DSI0_DIGITAL>,
999 clock-names = "engine", "digital", "hs";
1002 status = "disabled";
1005 dsi1: dsi@1401c000 {
1006 compatible = "mediatek,mt8173-dsi";
1007 reg = <0 0x1401c000 0 0x1000>;
1008 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>;
1009 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1010 clocks = <&mmsys CLK_MM_DSI1_ENGINE>,
1011 <&mmsys CLK_MM_DSI1_DIGITAL>,
1013 clock-names = "engine", "digital", "hs";
1016 status = "disabled";
1019 dpi0: dpi@1401d000 {
1020 compatible = "mediatek,mt8173-dpi";
1021 reg = <0 0x1401d000 0 0x1000>;
1022 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
1023 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1024 clocks = <&mmsys CLK_MM_DPI_PIXEL>,
1025 <&mmsys CLK_MM_DPI_ENGINE>,
1026 <&apmixedsys CLK_APMIXED_TVDPLL>;
1027 clock-names = "pixel", "engine", "pll";
1028 status = "disabled";
1031 dpi0_out: endpoint {
1032 remote-endpoint = <&hdmi0_in>;
1037 pwm0: pwm@1401e000 {
1038 compatible = "mediatek,mt8173-disp-pwm",
1039 "mediatek,mt6595-disp-pwm";
1040 reg = <0 0x1401e000 0 0x1000>;
1042 clocks = <&mmsys CLK_MM_DISP_PWM026M>,
1043 <&mmsys CLK_MM_DISP_PWM0MM>;
1044 clock-names = "main", "mm";
1045 status = "disabled";
1048 pwm1: pwm@1401f000 {
1049 compatible = "mediatek,mt8173-disp-pwm",
1050 "mediatek,mt6595-disp-pwm";
1051 reg = <0 0x1401f000 0 0x1000>;
1053 clocks = <&mmsys CLK_MM_DISP_PWM126M>,
1054 <&mmsys CLK_MM_DISP_PWM1MM>;
1055 clock-names = "main", "mm";
1056 status = "disabled";
1059 mutex: mutex@14020000 {
1060 compatible = "mediatek,mt8173-disp-mutex";
1061 reg = <0 0x14020000 0 0x1000>;
1062 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>;
1063 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1064 clocks = <&mmsys CLK_MM_MUTEX_32K>;
1067 larb0: larb@14021000 {
1068 compatible = "mediatek,mt8173-smi-larb";
1069 reg = <0 0x14021000 0 0x1000>;
1070 mediatek,smi = <&smi_common>;
1071 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1072 clocks = <&mmsys CLK_MM_SMI_LARB0>,
1073 <&mmsys CLK_MM_SMI_LARB0>;
1074 clock-names = "apb", "smi";
1077 smi_common: smi@14022000 {
1078 compatible = "mediatek,mt8173-smi-common";
1079 reg = <0 0x14022000 0 0x1000>;
1080 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1081 clocks = <&mmsys CLK_MM_SMI_COMMON>,
1082 <&mmsys CLK_MM_SMI_COMMON>;
1083 clock-names = "apb", "smi";
1087 compatible = "mediatek,mt8173-disp-od";
1088 reg = <0 0x14023000 0 0x1000>;
1089 clocks = <&mmsys CLK_MM_DISP_OD>;
1092 hdmi0: hdmi@14025000 {
1093 compatible = "mediatek,mt8173-hdmi";
1094 reg = <0 0x14025000 0 0x400>;
1095 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_LOW>;
1096 clocks = <&mmsys CLK_MM_HDMI_PIXEL>,
1097 <&mmsys CLK_MM_HDMI_PLLCK>,
1098 <&mmsys CLK_MM_HDMI_AUDIO>,
1099 <&mmsys CLK_MM_HDMI_SPDIF>;
1100 clock-names = "pixel", "pll", "bclk", "spdif";
1101 pinctrl-names = "default";
1102 pinctrl-0 = <&hdmi_pin>;
1105 mediatek,syscon-hdmi = <&mmsys 0x900>;
1106 assigned-clocks = <&topckgen CLK_TOP_HDMI_SEL>;
1107 assigned-clock-parents = <&hdmi_phy>;
1108 status = "disabled";
1111 #address-cells = <1>;
1117 hdmi0_in: endpoint {
1118 remote-endpoint = <&dpi0_out>;
1124 larb4: larb@14027000 {
1125 compatible = "mediatek,mt8173-smi-larb";
1126 reg = <0 0x14027000 0 0x1000>;
1127 mediatek,smi = <&smi_common>;
1128 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1129 clocks = <&mmsys CLK_MM_SMI_LARB4>,
1130 <&mmsys CLK_MM_SMI_LARB4>;
1131 clock-names = "apb", "smi";
1134 imgsys: clock-controller@15000000 {
1135 compatible = "mediatek,mt8173-imgsys", "syscon";
1136 reg = <0 0x15000000 0 0x1000>;
1140 larb2: larb@15001000 {
1141 compatible = "mediatek,mt8173-smi-larb";
1142 reg = <0 0x15001000 0 0x1000>;
1143 mediatek,smi = <&smi_common>;
1144 power-domains = <&scpsys MT8173_POWER_DOMAIN_ISP>;
1145 clocks = <&imgsys CLK_IMG_LARB2_SMI>,
1146 <&imgsys CLK_IMG_LARB2_SMI>;
1147 clock-names = "apb", "smi";
1150 vdecsys: clock-controller@16000000 {
1151 compatible = "mediatek,mt8173-vdecsys", "syscon";
1152 reg = <0 0x16000000 0 0x1000>;
1156 vcodec_dec: vcodec@16000000 {
1157 compatible = "mediatek,mt8173-vcodec-dec";
1158 reg = <0 0x16000000 0 0x100>, /* VDEC_SYS */
1159 <0 0x16020000 0 0x1000>, /* VDEC_MISC */
1160 <0 0x16021000 0 0x800>, /* VDEC_LD */
1161 <0 0x16021800 0 0x800>, /* VDEC_TOP */
1162 <0 0x16022000 0 0x1000>, /* VDEC_CM */
1163 <0 0x16023000 0 0x1000>, /* VDEC_AD */
1164 <0 0x16024000 0 0x1000>, /* VDEC_AV */
1165 <0 0x16025000 0 0x1000>, /* VDEC_PP */
1166 <0 0x16026800 0 0x800>, /* VDEC_HWD */
1167 <0 0x16027000 0 0x800>, /* VDEC_HWQ */
1168 <0 0x16027800 0 0x800>, /* VDEC_HWB */
1169 <0 0x16028400 0 0x400>; /* VDEC_HWG */
1170 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_LOW>;
1171 mediatek,larb = <&larb1>;
1172 iommus = <&iommu M4U_PORT_HW_VDEC_MC_EXT>,
1173 <&iommu M4U_PORT_HW_VDEC_PP_EXT>,
1174 <&iommu M4U_PORT_HW_VDEC_AVC_MV_EXT>,
1175 <&iommu M4U_PORT_HW_VDEC_PRED_RD_EXT>,
1176 <&iommu M4U_PORT_HW_VDEC_PRED_WR_EXT>,
1177 <&iommu M4U_PORT_HW_VDEC_UFO_EXT>,
1178 <&iommu M4U_PORT_HW_VDEC_VLD_EXT>,
1179 <&iommu M4U_PORT_HW_VDEC_VLD2_EXT>;
1180 mediatek,vpu = <&vpu>;
1181 power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>;
1182 clocks = <&apmixedsys CLK_APMIXED_VCODECPLL>,
1183 <&topckgen CLK_TOP_UNIVPLL_D2>,
1184 <&topckgen CLK_TOP_CCI400_SEL>,
1185 <&topckgen CLK_TOP_VDEC_SEL>,
1186 <&topckgen CLK_TOP_VCODECPLL>,
1187 <&apmixedsys CLK_APMIXED_VENCPLL>,
1188 <&topckgen CLK_TOP_VENC_LT_SEL>,
1189 <&topckgen CLK_TOP_VCODECPLL_370P5>;
1190 clock-names = "vcodecpll",
1200 larb1: larb@16010000 {
1201 compatible = "mediatek,mt8173-smi-larb";
1202 reg = <0 0x16010000 0 0x1000>;
1203 mediatek,smi = <&smi_common>;
1204 power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>;
1205 clocks = <&vdecsys CLK_VDEC_CKEN>,
1206 <&vdecsys CLK_VDEC_LARB_CKEN>;
1207 clock-names = "apb", "smi";
1210 vencsys: clock-controller@18000000 {
1211 compatible = "mediatek,mt8173-vencsys", "syscon";
1212 reg = <0 0x18000000 0 0x1000>;
1216 larb3: larb@18001000 {
1217 compatible = "mediatek,mt8173-smi-larb";
1218 reg = <0 0x18001000 0 0x1000>;
1219 mediatek,smi = <&smi_common>;
1220 power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC>;
1221 clocks = <&vencsys CLK_VENC_CKE1>,
1222 <&vencsys CLK_VENC_CKE0>;
1223 clock-names = "apb", "smi";
1226 vcodec_enc: vcodec@18002000 {
1227 compatible = "mediatek,mt8173-vcodec-enc";
1228 reg = <0 0x18002000 0 0x1000>, /* VENC_SYS */
1229 <0 0x19002000 0 0x1000>; /* VENC_LT_SYS */
1230 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>,
1231 <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>;
1232 mediatek,larb = <&larb3>,
1234 iommus = <&iommu M4U_PORT_VENC_RCPU>,
1235 <&iommu M4U_PORT_VENC_REC>,
1236 <&iommu M4U_PORT_VENC_BSDMA>,
1237 <&iommu M4U_PORT_VENC_SV_COMV>,
1238 <&iommu M4U_PORT_VENC_RD_COMV>,
1239 <&iommu M4U_PORT_VENC_CUR_LUMA>,
1240 <&iommu M4U_PORT_VENC_CUR_CHROMA>,
1241 <&iommu M4U_PORT_VENC_REF_LUMA>,
1242 <&iommu M4U_PORT_VENC_REF_CHROMA>,
1243 <&iommu M4U_PORT_VENC_NBM_RDMA>,
1244 <&iommu M4U_PORT_VENC_NBM_WDMA>,
1245 <&iommu M4U_PORT_VENC_RCPU_SET2>,
1246 <&iommu M4U_PORT_VENC_REC_FRM_SET2>,
1247 <&iommu M4U_PORT_VENC_BSDMA_SET2>,
1248 <&iommu M4U_PORT_VENC_SV_COMA_SET2>,
1249 <&iommu M4U_PORT_VENC_RD_COMA_SET2>,
1250 <&iommu M4U_PORT_VENC_CUR_LUMA_SET2>,
1251 <&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>,
1252 <&iommu M4U_PORT_VENC_REF_LUMA_SET2>,
1253 <&iommu M4U_PORT_VENC_REC_CHROMA_SET2>;
1254 mediatek,vpu = <&vpu>;
1255 clocks = <&topckgen CLK_TOP_VENCPLL_D2>,
1256 <&topckgen CLK_TOP_VENC_SEL>,
1257 <&topckgen CLK_TOP_UNIVPLL1_D2>,
1258 <&topckgen CLK_TOP_VENC_LT_SEL>;
1259 clock-names = "venc_sel_src",
1265 vencltsys: clock-controller@19000000 {
1266 compatible = "mediatek,mt8173-vencltsys", "syscon";
1267 reg = <0 0x19000000 0 0x1000>;
1271 larb5: larb@19001000 {
1272 compatible = "mediatek,mt8173-smi-larb";
1273 reg = <0 0x19001000 0 0x1000>;
1274 mediatek,smi = <&smi_common>;
1275 power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC_LT>;
1276 clocks = <&vencltsys CLK_VENCLT_CKE1>,
1277 <&vencltsys CLK_VENCLT_CKE0>;
1278 clock-names = "apb", "smi";