1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra194-clock.h>
3 #include <dt-bindings/gpio/tegra194-gpio.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mailbox/tegra186-hsp.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
7 #include <dt-bindings/power/tegra194-powergate.h>
8 #include <dt-bindings/reset/tegra194-reset.h>
9 #include <dt-bindings/thermal/tegra194-bpmp-thermal.h>
12 compatible = "nvidia,tegra194";
13 interrupt-parent = <&gic>;
17 /* control backbone */
19 compatible = "simple-bus";
22 ranges = <0x0 0x0 0x0 0x40000000>;
25 compatible = "nvidia,tegra194-gpio";
26 reg-names = "security", "gpio";
27 reg = <0x2200000 0x10000>,
29 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>,
30 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
31 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
32 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
33 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
34 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>;
35 #interrupt-cells = <2>;
42 compatible = "nvidia,tegra186-eqos",
43 "snps,dwc-qos-ethernet-4.10";
44 reg = <0x02490000 0x10000>;
45 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
46 clocks = <&bpmp TEGRA194_CLK_AXI_CBB>,
47 <&bpmp TEGRA194_CLK_EQOS_AXI>,
48 <&bpmp TEGRA194_CLK_EQOS_RX>,
49 <&bpmp TEGRA194_CLK_EQOS_TX>,
50 <&bpmp TEGRA194_CLK_EQOS_PTP_REF>;
51 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref";
52 resets = <&bpmp TEGRA194_RESET_EQOS>;
56 snps,write-requests = <1>;
57 snps,read-requests = <3>;
58 snps,burst-map = <0x7>;
64 compatible = "nvidia,tegra194-aconnect",
65 "nvidia,tegra210-aconnect";
66 clocks = <&bpmp TEGRA194_CLK_APE>,
67 <&bpmp TEGRA194_CLK_APB2APE>;
68 clock-names = "ape", "apb2ape";
69 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_AUD>;
72 ranges = <0x02900000 0x02900000 0x200000>;
75 dma-controller@2930000 {
76 compatible = "nvidia,tegra194-adma",
77 "nvidia,tegra186-adma";
78 reg = <0x02930000 0x20000>;
79 interrupt-parent = <&agic>;
80 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
81 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
82 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
83 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
84 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
85 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
86 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
87 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
88 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
89 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
90 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
91 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
92 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
93 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
94 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
95 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
96 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
97 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
98 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
99 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
100 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
101 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
102 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
103 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
104 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
105 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
106 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
107 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
108 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
109 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
110 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
111 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
113 clocks = <&bpmp TEGRA194_CLK_AHUB>;
114 clock-names = "d_audio";
118 agic: interrupt-controller@2a40000 {
119 compatible = "nvidia,tegra194-agic",
120 "nvidia,tegra210-agic";
121 #interrupt-cells = <3>;
122 interrupt-controller;
123 reg = <0x02a41000 0x1000>,
125 interrupts = <GIC_SPI 145
126 (GIC_CPU_MASK_SIMPLE(4) |
127 IRQ_TYPE_LEVEL_HIGH)>;
128 clocks = <&bpmp TEGRA194_CLK_APE>;
134 pinmux: pinmux@2430000 {
135 compatible = "nvidia,tegra194-pinmux";
136 reg = <0x2430000 0x17000
141 pex_rst_c5_out_state: pex_rst_c5_out {
143 nvidia,pins = "pex_l5_rst_n_pgg1";
144 nvidia,schmitt = <TEGRA_PIN_DISABLE>;
145 nvidia,lpdr = <TEGRA_PIN_ENABLE>;
146 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
147 nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
148 nvidia,tristate = <TEGRA_PIN_DISABLE>;
149 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
153 clkreq_c5_bi_dir_state: clkreq_c5_bi_dir {
155 nvidia,pins = "pex_l5_clkreq_n_pgg0";
156 nvidia,schmitt = <TEGRA_PIN_DISABLE>;
157 nvidia,lpdr = <TEGRA_PIN_ENABLE>;
158 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
159 nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
160 nvidia,tristate = <TEGRA_PIN_DISABLE>;
161 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
166 uarta: serial@3100000 {
167 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
168 reg = <0x03100000 0x40>;
170 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
171 clocks = <&bpmp TEGRA194_CLK_UARTA>;
172 clock-names = "serial";
173 resets = <&bpmp TEGRA194_RESET_UARTA>;
174 reset-names = "serial";
178 uartb: serial@3110000 {
179 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
180 reg = <0x03110000 0x40>;
182 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
183 clocks = <&bpmp TEGRA194_CLK_UARTB>;
184 clock-names = "serial";
185 resets = <&bpmp TEGRA194_RESET_UARTB>;
186 reset-names = "serial";
190 uartd: serial@3130000 {
191 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
192 reg = <0x03130000 0x40>;
194 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
195 clocks = <&bpmp TEGRA194_CLK_UARTD>;
196 clock-names = "serial";
197 resets = <&bpmp TEGRA194_RESET_UARTD>;
198 reset-names = "serial";
202 uarte: serial@3140000 {
203 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
204 reg = <0x03140000 0x40>;
206 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
207 clocks = <&bpmp TEGRA194_CLK_UARTE>;
208 clock-names = "serial";
209 resets = <&bpmp TEGRA194_RESET_UARTE>;
210 reset-names = "serial";
214 uartf: serial@3150000 {
215 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
216 reg = <0x03150000 0x40>;
218 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
219 clocks = <&bpmp TEGRA194_CLK_UARTF>;
220 clock-names = "serial";
221 resets = <&bpmp TEGRA194_RESET_UARTF>;
222 reset-names = "serial";
226 gen1_i2c: i2c@3160000 {
227 compatible = "nvidia,tegra194-i2c";
228 reg = <0x03160000 0x10000>;
229 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
230 #address-cells = <1>;
232 clocks = <&bpmp TEGRA194_CLK_I2C1>;
233 clock-names = "div-clk";
234 resets = <&bpmp TEGRA194_RESET_I2C1>;
239 uarth: serial@3170000 {
240 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
241 reg = <0x03170000 0x40>;
243 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
244 clocks = <&bpmp TEGRA194_CLK_UARTH>;
245 clock-names = "serial";
246 resets = <&bpmp TEGRA194_RESET_UARTH>;
247 reset-names = "serial";
251 cam_i2c: i2c@3180000 {
252 compatible = "nvidia,tegra194-i2c";
253 reg = <0x03180000 0x10000>;
254 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
255 #address-cells = <1>;
257 clocks = <&bpmp TEGRA194_CLK_I2C3>;
258 clock-names = "div-clk";
259 resets = <&bpmp TEGRA194_RESET_I2C3>;
264 /* shares pads with dpaux1 */
265 dp_aux_ch1_i2c: i2c@3190000 {
266 compatible = "nvidia,tegra194-i2c";
267 reg = <0x03190000 0x10000>;
268 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
269 #address-cells = <1>;
271 clocks = <&bpmp TEGRA194_CLK_I2C4>;
272 clock-names = "div-clk";
273 resets = <&bpmp TEGRA194_RESET_I2C4>;
278 /* shares pads with dpaux0 */
279 dp_aux_ch0_i2c: i2c@31b0000 {
280 compatible = "nvidia,tegra194-i2c";
281 reg = <0x031b0000 0x10000>;
282 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
283 #address-cells = <1>;
285 clocks = <&bpmp TEGRA194_CLK_I2C6>;
286 clock-names = "div-clk";
287 resets = <&bpmp TEGRA194_RESET_I2C6>;
292 gen7_i2c: i2c@31c0000 {
293 compatible = "nvidia,tegra194-i2c";
294 reg = <0x031c0000 0x10000>;
295 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
296 #address-cells = <1>;
298 clocks = <&bpmp TEGRA194_CLK_I2C7>;
299 clock-names = "div-clk";
300 resets = <&bpmp TEGRA194_RESET_I2C7>;
305 gen9_i2c: i2c@31e0000 {
306 compatible = "nvidia,tegra194-i2c";
307 reg = <0x031e0000 0x10000>;
308 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
309 #address-cells = <1>;
311 clocks = <&bpmp TEGRA194_CLK_I2C9>;
312 clock-names = "div-clk";
313 resets = <&bpmp TEGRA194_RESET_I2C9>;
319 compatible = "nvidia,tegra194-pwm",
320 "nvidia,tegra186-pwm";
321 reg = <0x3280000 0x10000>;
322 clocks = <&bpmp TEGRA194_CLK_PWM1>;
324 resets = <&bpmp TEGRA194_RESET_PWM1>;
331 compatible = "nvidia,tegra194-pwm",
332 "nvidia,tegra186-pwm";
333 reg = <0x3290000 0x10000>;
334 clocks = <&bpmp TEGRA194_CLK_PWM2>;
336 resets = <&bpmp TEGRA194_RESET_PWM2>;
343 compatible = "nvidia,tegra194-pwm",
344 "nvidia,tegra186-pwm";
345 reg = <0x32a0000 0x10000>;
346 clocks = <&bpmp TEGRA194_CLK_PWM3>;
348 resets = <&bpmp TEGRA194_RESET_PWM3>;
355 compatible = "nvidia,tegra194-pwm",
356 "nvidia,tegra186-pwm";
357 reg = <0x32c0000 0x10000>;
358 clocks = <&bpmp TEGRA194_CLK_PWM5>;
360 resets = <&bpmp TEGRA194_RESET_PWM5>;
367 compatible = "nvidia,tegra194-pwm",
368 "nvidia,tegra186-pwm";
369 reg = <0x32d0000 0x10000>;
370 clocks = <&bpmp TEGRA194_CLK_PWM6>;
372 resets = <&bpmp TEGRA194_RESET_PWM6>;
379 compatible = "nvidia,tegra194-pwm",
380 "nvidia,tegra186-pwm";
381 reg = <0x32e0000 0x10000>;
382 clocks = <&bpmp TEGRA194_CLK_PWM7>;
384 resets = <&bpmp TEGRA194_RESET_PWM7>;
391 compatible = "nvidia,tegra194-pwm",
392 "nvidia,tegra186-pwm";
393 reg = <0x32f0000 0x10000>;
394 clocks = <&bpmp TEGRA194_CLK_PWM8>;
396 resets = <&bpmp TEGRA194_RESET_PWM8>;
402 sdmmc1: sdhci@3400000 {
403 compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci";
404 reg = <0x03400000 0x10000>;
405 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
406 clocks = <&bpmp TEGRA194_CLK_SDMMC1>;
407 clock-names = "sdhci";
408 resets = <&bpmp TEGRA194_RESET_SDMMC1>;
409 reset-names = "sdhci";
410 nvidia,pad-autocal-pull-up-offset-3v3-timeout =
412 nvidia,pad-autocal-pull-down-offset-3v3-timeout =
414 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>;
415 nvidia,pad-autocal-pull-down-offset-1v8-timeout =
417 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>;
418 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>;
419 nvidia,default-tap = <0x9>;
420 nvidia,default-trim = <0x5>;
424 sdmmc3: sdhci@3440000 {
425 compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci";
426 reg = <0x03440000 0x10000>;
427 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
428 clocks = <&bpmp TEGRA194_CLK_SDMMC3>;
429 clock-names = "sdhci";
430 resets = <&bpmp TEGRA194_RESET_SDMMC3>;
431 reset-names = "sdhci";
432 nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>;
433 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>;
434 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
435 nvidia,pad-autocal-pull-down-offset-3v3-timeout =
437 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>;
438 nvidia,pad-autocal-pull-down-offset-1v8-timeout =
440 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>;
441 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>;
442 nvidia,default-tap = <0x9>;
443 nvidia,default-trim = <0x5>;
447 sdmmc4: sdhci@3460000 {
448 compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci";
449 reg = <0x03460000 0x10000>;
450 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
451 clocks = <&bpmp TEGRA194_CLK_SDMMC4>;
452 clock-names = "sdhci";
453 assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC4>,
454 <&bpmp TEGRA194_CLK_PLLC4>;
455 assigned-clock-parents =
456 <&bpmp TEGRA194_CLK_PLLC4>;
457 resets = <&bpmp TEGRA194_RESET_SDMMC4>;
458 reset-names = "sdhci";
459 nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>;
460 nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>;
461 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>;
462 nvidia,pad-autocal-pull-down-offset-1v8-timeout =
464 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>;
465 nvidia,pad-autocal-pull-down-offset-3v3-timeout =
467 nvidia,default-tap = <0x8>;
468 nvidia,default-trim = <0x14>;
469 nvidia,dqs-trim = <40>;
475 compatible = "nvidia,tegra194-hda", "nvidia,tegra30-hda";
476 reg = <0x3510000 0x10000>;
477 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
478 clocks = <&bpmp TEGRA194_CLK_HDA>,
479 <&bpmp TEGRA194_CLK_HDA2CODEC_2X>,
480 <&bpmp TEGRA194_CLK_HDA2HDMICODEC>;
481 clock-names = "hda", "hda2codec_2x", "hda2hdmi";
482 resets = <&bpmp TEGRA194_RESET_HDA>,
483 <&bpmp TEGRA194_RESET_HDA2CODEC_2X>,
484 <&bpmp TEGRA194_RESET_HDA2HDMICODEC>;
485 reset-names = "hda", "hda2codec_2x", "hda2hdmi";
486 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
490 gic: interrupt-controller@3881000 {
491 compatible = "arm,gic-400";
492 #interrupt-cells = <3>;
493 interrupt-controller;
494 reg = <0x03881000 0x1000>,
498 interrupts = <GIC_PPI 9
499 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
500 interrupt-parent = <&gic>;
504 compatible = "nvidia,tegra194-cec";
505 reg = <0x03960000 0x10000>;
506 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
507 clocks = <&bpmp TEGRA194_CLK_CEC>;
512 hsp_top0: hsp@3c00000 {
513 compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp";
514 reg = <0x03c00000 0xa0000>;
515 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
516 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
517 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
518 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
519 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
520 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
521 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
522 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
523 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
524 interrupt-names = "doorbell", "shared0", "shared1", "shared2",
525 "shared3", "shared4", "shared5", "shared6",
530 p2u_hsio_0: phy@3e10000 {
531 compatible = "nvidia,tegra194-p2u";
532 reg = <0x03e10000 0x10000>;
538 p2u_hsio_1: phy@3e20000 {
539 compatible = "nvidia,tegra194-p2u";
540 reg = <0x03e20000 0x10000>;
546 p2u_hsio_2: phy@3e30000 {
547 compatible = "nvidia,tegra194-p2u";
548 reg = <0x03e30000 0x10000>;
554 p2u_hsio_3: phy@3e40000 {
555 compatible = "nvidia,tegra194-p2u";
556 reg = <0x03e40000 0x10000>;
562 p2u_hsio_4: phy@3e50000 {
563 compatible = "nvidia,tegra194-p2u";
564 reg = <0x03e50000 0x10000>;
570 p2u_hsio_5: phy@3e60000 {
571 compatible = "nvidia,tegra194-p2u";
572 reg = <0x03e60000 0x10000>;
578 p2u_hsio_6: phy@3e70000 {
579 compatible = "nvidia,tegra194-p2u";
580 reg = <0x03e70000 0x10000>;
586 p2u_hsio_7: phy@3e80000 {
587 compatible = "nvidia,tegra194-p2u";
588 reg = <0x03e80000 0x10000>;
594 p2u_hsio_8: phy@3e90000 {
595 compatible = "nvidia,tegra194-p2u";
596 reg = <0x03e90000 0x10000>;
602 p2u_hsio_9: phy@3ea0000 {
603 compatible = "nvidia,tegra194-p2u";
604 reg = <0x03ea0000 0x10000>;
610 p2u_nvhs_0: phy@3eb0000 {
611 compatible = "nvidia,tegra194-p2u";
612 reg = <0x03eb0000 0x10000>;
618 p2u_nvhs_1: phy@3ec0000 {
619 compatible = "nvidia,tegra194-p2u";
620 reg = <0x03ec0000 0x10000>;
626 p2u_nvhs_2: phy@3ed0000 {
627 compatible = "nvidia,tegra194-p2u";
628 reg = <0x03ed0000 0x10000>;
634 p2u_nvhs_3: phy@3ee0000 {
635 compatible = "nvidia,tegra194-p2u";
636 reg = <0x03ee0000 0x10000>;
642 p2u_nvhs_4: phy@3ef0000 {
643 compatible = "nvidia,tegra194-p2u";
644 reg = <0x03ef0000 0x10000>;
650 p2u_nvhs_5: phy@3f00000 {
651 compatible = "nvidia,tegra194-p2u";
652 reg = <0x03f00000 0x10000>;
658 p2u_nvhs_6: phy@3f10000 {
659 compatible = "nvidia,tegra194-p2u";
660 reg = <0x03f10000 0x10000>;
666 p2u_nvhs_7: phy@3f20000 {
667 compatible = "nvidia,tegra194-p2u";
668 reg = <0x03f20000 0x10000>;
674 p2u_hsio_10: phy@3f30000 {
675 compatible = "nvidia,tegra194-p2u";
676 reg = <0x03f30000 0x10000>;
682 p2u_hsio_11: phy@3f40000 {
683 compatible = "nvidia,tegra194-p2u";
684 reg = <0x03f40000 0x10000>;
690 hsp_aon: hsp@c150000 {
691 compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp";
692 reg = <0x0c150000 0xa0000>;
693 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
694 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
695 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
696 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
698 * Shared interrupt 0 is routed only to AON/SPE, so
699 * we only have 4 shared interrupts for the CCPLEX.
701 interrupt-names = "shared1", "shared2", "shared3", "shared4";
705 gen2_i2c: i2c@c240000 {
706 compatible = "nvidia,tegra194-i2c";
707 reg = <0x0c240000 0x10000>;
708 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
709 #address-cells = <1>;
711 clocks = <&bpmp TEGRA194_CLK_I2C2>;
712 clock-names = "div-clk";
713 resets = <&bpmp TEGRA194_RESET_I2C2>;
718 gen8_i2c: i2c@c250000 {
719 compatible = "nvidia,tegra194-i2c";
720 reg = <0x0c250000 0x10000>;
721 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
722 #address-cells = <1>;
724 clocks = <&bpmp TEGRA194_CLK_I2C8>;
725 clock-names = "div-clk";
726 resets = <&bpmp TEGRA194_RESET_I2C8>;
731 uartc: serial@c280000 {
732 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
733 reg = <0x0c280000 0x40>;
735 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
736 clocks = <&bpmp TEGRA194_CLK_UARTC>;
737 clock-names = "serial";
738 resets = <&bpmp TEGRA194_RESET_UARTC>;
739 reset-names = "serial";
743 uartg: serial@c290000 {
744 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
745 reg = <0x0c290000 0x40>;
747 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
748 clocks = <&bpmp TEGRA194_CLK_UARTG>;
749 clock-names = "serial";
750 resets = <&bpmp TEGRA194_RESET_UARTG>;
751 reset-names = "serial";
756 compatible = "nvidia,tegra194-rtc", "nvidia,tegra20-rtc";
757 reg = <0x0c2a0000 0x10000>;
758 interrupt-parent = <&pmc>;
759 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>;
760 clocks = <&bpmp TEGRA194_CLK_CLK_32K>;
765 gpio_aon: gpio@c2f0000 {
766 compatible = "nvidia,tegra194-gpio-aon";
767 reg-names = "security", "gpio";
768 reg = <0xc2f0000 0x1000>,
770 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
771 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
772 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
773 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
776 interrupt-controller;
777 #interrupt-cells = <2>;
781 compatible = "nvidia,tegra194-pwm",
782 "nvidia,tegra186-pwm";
783 reg = <0xc340000 0x10000>;
784 clocks = <&bpmp TEGRA194_CLK_PWM4>;
786 resets = <&bpmp TEGRA194_RESET_PWM4>;
793 compatible = "nvidia,tegra194-pmc";
794 reg = <0x0c360000 0x10000>,
795 <0x0c370000 0x10000>,
796 <0x0c380000 0x10000>,
797 <0x0c390000 0x10000>,
798 <0x0c3a0000 0x10000>;
799 reg-names = "pmc", "wake", "aotag", "scratch", "misc";
801 #interrupt-cells = <2>;
802 interrupt-controller;
806 compatible = "nvidia,tegra194-host1x", "simple-bus";
807 reg = <0x13e00000 0x10000>,
808 <0x13e10000 0x10000>;
809 reg-names = "hypervisor", "vm";
810 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
811 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
812 clocks = <&bpmp TEGRA194_CLK_HOST1X>;
813 clock-names = "host1x";
814 resets = <&bpmp TEGRA194_RESET_HOST1X>;
815 reset-names = "host1x";
817 #address-cells = <1>;
820 ranges = <0x15000000 0x15000000 0x01000000>;
822 display-hub@15200000 {
823 compatible = "nvidia,tegra194-display", "simple-bus";
824 reg = <0x15200000 0x00040000>;
825 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>,
826 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>,
827 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>,
828 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>,
829 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>,
830 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>,
831 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>;
832 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2",
833 "wgrp3", "wgrp4", "wgrp5";
834 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>,
835 <&bpmp TEGRA194_CLK_NVDISPLAYHUB>;
836 clock-names = "disp", "hub";
839 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
841 #address-cells = <1>;
844 ranges = <0x15200000 0x15200000 0x40000>;
847 compatible = "nvidia,tegra194-dc";
848 reg = <0x15200000 0x10000>;
849 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
850 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>;
852 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>;
855 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
857 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
862 compatible = "nvidia,tegra194-dc";
863 reg = <0x15210000 0x10000>;
864 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
865 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>;
867 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>;
870 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>;
872 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
877 compatible = "nvidia,tegra194-dc";
878 reg = <0x15220000 0x10000>;
879 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
880 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>;
882 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>;
885 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>;
887 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
892 compatible = "nvidia,tegra194-dc";
893 reg = <0x15230000 0x10000>;
894 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
895 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>;
897 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>;
900 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>;
902 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
908 compatible = "nvidia,tegra194-vic";
909 reg = <0x15340000 0x00040000>;
910 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
911 clocks = <&bpmp TEGRA194_CLK_VIC>;
913 resets = <&bpmp TEGRA194_RESET_VIC>;
916 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_VIC>;
919 dpaux0: dpaux@155c0000 {
920 compatible = "nvidia,tegra194-dpaux";
921 reg = <0x155c0000 0x10000>;
922 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
923 clocks = <&bpmp TEGRA194_CLK_DPAUX>,
924 <&bpmp TEGRA194_CLK_PLLDP>;
925 clock-names = "dpaux", "parent";
926 resets = <&bpmp TEGRA194_RESET_DPAUX>;
927 reset-names = "dpaux";
930 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
932 state_dpaux0_aux: pinmux-aux {
937 state_dpaux0_i2c: pinmux-i2c {
942 state_dpaux0_off: pinmux-off {
948 #address-cells = <1>;
953 dpaux1: dpaux@155d0000 {
954 compatible = "nvidia,tegra194-dpaux";
955 reg = <0x155d0000 0x10000>;
956 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
957 clocks = <&bpmp TEGRA194_CLK_DPAUX1>,
958 <&bpmp TEGRA194_CLK_PLLDP>;
959 clock-names = "dpaux", "parent";
960 resets = <&bpmp TEGRA194_RESET_DPAUX1>;
961 reset-names = "dpaux";
964 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
966 state_dpaux1_aux: pinmux-aux {
971 state_dpaux1_i2c: pinmux-i2c {
976 state_dpaux1_off: pinmux-off {
982 #address-cells = <1>;
987 dpaux2: dpaux@155e0000 {
988 compatible = "nvidia,tegra194-dpaux";
989 reg = <0x155e0000 0x10000>;
990 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
991 clocks = <&bpmp TEGRA194_CLK_DPAUX2>,
992 <&bpmp TEGRA194_CLK_PLLDP>;
993 clock-names = "dpaux", "parent";
994 resets = <&bpmp TEGRA194_RESET_DPAUX2>;
995 reset-names = "dpaux";
998 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1000 state_dpaux2_aux: pinmux-aux {
1001 groups = "dpaux-io";
1005 state_dpaux2_i2c: pinmux-i2c {
1006 groups = "dpaux-io";
1010 state_dpaux2_off: pinmux-off {
1011 groups = "dpaux-io";
1016 #address-cells = <1>;
1021 dpaux3: dpaux@155f0000 {
1022 compatible = "nvidia,tegra194-dpaux";
1023 reg = <0x155f0000 0x10000>;
1024 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
1025 clocks = <&bpmp TEGRA194_CLK_DPAUX3>,
1026 <&bpmp TEGRA194_CLK_PLLDP>;
1027 clock-names = "dpaux", "parent";
1028 resets = <&bpmp TEGRA194_RESET_DPAUX3>;
1029 reset-names = "dpaux";
1030 status = "disabled";
1032 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1034 state_dpaux3_aux: pinmux-aux {
1035 groups = "dpaux-io";
1039 state_dpaux3_i2c: pinmux-i2c {
1040 groups = "dpaux-io";
1044 state_dpaux3_off: pinmux-off {
1045 groups = "dpaux-io";
1050 #address-cells = <1>;
1055 sor0: sor@15b00000 {
1056 compatible = "nvidia,tegra194-sor";
1057 reg = <0x15b00000 0x40000>;
1058 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
1059 clocks = <&bpmp TEGRA194_CLK_SOR0_REF>,
1060 <&bpmp TEGRA194_CLK_SOR0_OUT>,
1061 <&bpmp TEGRA194_CLK_PLLD>,
1062 <&bpmp TEGRA194_CLK_PLLDP>,
1063 <&bpmp TEGRA194_CLK_SOR_SAFE>,
1064 <&bpmp TEGRA194_CLK_SOR0_PAD_CLKOUT>;
1065 clock-names = "sor", "out", "parent", "dp", "safe",
1067 resets = <&bpmp TEGRA194_RESET_SOR0>;
1068 reset-names = "sor";
1069 pinctrl-0 = <&state_dpaux0_aux>;
1070 pinctrl-1 = <&state_dpaux0_i2c>;
1071 pinctrl-2 = <&state_dpaux0_off>;
1072 pinctrl-names = "aux", "i2c", "off";
1073 status = "disabled";
1075 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1076 nvidia,interface = <0>;
1079 sor1: sor@15b40000 {
1080 compatible = "nvidia,tegra194-sor";
1081 reg = <0x155c0000 0x40000>;
1082 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
1083 clocks = <&bpmp TEGRA194_CLK_SOR1_REF>,
1084 <&bpmp TEGRA194_CLK_SOR1_OUT>,
1085 <&bpmp TEGRA194_CLK_PLLD2>,
1086 <&bpmp TEGRA194_CLK_PLLDP>,
1087 <&bpmp TEGRA194_CLK_SOR_SAFE>,
1088 <&bpmp TEGRA194_CLK_SOR1_PAD_CLKOUT>;
1089 clock-names = "sor", "out", "parent", "dp", "safe",
1091 resets = <&bpmp TEGRA194_RESET_SOR1>;
1092 reset-names = "sor";
1093 pinctrl-0 = <&state_dpaux1_aux>;
1094 pinctrl-1 = <&state_dpaux1_i2c>;
1095 pinctrl-2 = <&state_dpaux1_off>;
1096 pinctrl-names = "aux", "i2c", "off";
1097 status = "disabled";
1099 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1100 nvidia,interface = <1>;
1103 sor2: sor@15b80000 {
1104 compatible = "nvidia,tegra194-sor";
1105 reg = <0x15b80000 0x40000>;
1106 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
1107 clocks = <&bpmp TEGRA194_CLK_SOR2_REF>,
1108 <&bpmp TEGRA194_CLK_SOR2_OUT>,
1109 <&bpmp TEGRA194_CLK_PLLD3>,
1110 <&bpmp TEGRA194_CLK_PLLDP>,
1111 <&bpmp TEGRA194_CLK_SOR_SAFE>,
1112 <&bpmp TEGRA194_CLK_SOR2_PAD_CLKOUT>;
1113 clock-names = "sor", "out", "parent", "dp", "safe",
1115 resets = <&bpmp TEGRA194_RESET_SOR2>;
1116 reset-names = "sor";
1117 pinctrl-0 = <&state_dpaux2_aux>;
1118 pinctrl-1 = <&state_dpaux2_i2c>;
1119 pinctrl-2 = <&state_dpaux2_off>;
1120 pinctrl-names = "aux", "i2c", "off";
1121 status = "disabled";
1123 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1124 nvidia,interface = <2>;
1127 sor3: sor@15bc0000 {
1128 compatible = "nvidia,tegra194-sor";
1129 reg = <0x15bc0000 0x40000>;
1130 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
1131 clocks = <&bpmp TEGRA194_CLK_SOR3_REF>,
1132 <&bpmp TEGRA194_CLK_SOR3_OUT>,
1133 <&bpmp TEGRA194_CLK_PLLD4>,
1134 <&bpmp TEGRA194_CLK_PLLDP>,
1135 <&bpmp TEGRA194_CLK_SOR_SAFE>,
1136 <&bpmp TEGRA194_CLK_SOR3_PAD_CLKOUT>;
1137 clock-names = "sor", "out", "parent", "dp", "safe",
1139 resets = <&bpmp TEGRA194_RESET_SOR3>;
1140 reset-names = "sor";
1141 pinctrl-0 = <&state_dpaux3_aux>;
1142 pinctrl-1 = <&state_dpaux3_i2c>;
1143 pinctrl-2 = <&state_dpaux3_off>;
1144 pinctrl-names = "aux", "i2c", "off";
1145 status = "disabled";
1147 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1148 nvidia,interface = <3>;
1154 compatible = "nvidia,tegra194-pcie", "snps,dw-pcie";
1155 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>;
1156 reg = <0x00 0x14100000 0x0 0x00020000 /* appl registers (128K) */
1157 0x00 0x30000000 0x0 0x00040000 /* configuration space (256K) */
1158 0x00 0x30040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */
1159 0x00 0x30080000 0x0 0x00040000>; /* DBI reg space (256K) */
1160 reg-names = "appl", "config", "atu_dma", "dbi";
1162 status = "disabled";
1164 #address-cells = <3>;
1166 device_type = "pci";
1169 linux,pci-domain = <1>;
1171 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_1>;
1172 clock-names = "core";
1174 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_1_APB>,
1175 <&bpmp TEGRA194_RESET_PEX0_CORE_1>;
1176 reset-names = "apb", "core";
1178 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
1179 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
1180 interrupt-names = "intr", "msi";
1182 #interrupt-cells = <1>;
1183 interrupt-map-mask = <0 0 0 0>;
1184 interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1186 nvidia,bpmp = <&bpmp 1>;
1189 nvidia,aspm-cmrt-us = <60>;
1190 nvidia,aspm-pwr-on-t-us = <20>;
1191 nvidia,aspm-l0s-entrance-latency-us = <3>;
1193 bus-range = <0x0 0xff>;
1194 ranges = <0x81000000 0x0 0x30100000 0x0 0x30100000 0x0 0x00100000 /* downstream I/O (1MB) */
1195 0xc2000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000 /* prefetchable memory (768MB) */
1196 0x82000000 0x0 0x40000000 0x12 0x30000000 0x0 0x10000000>; /* non-prefetchable memory (256MB) */
1200 compatible = "nvidia,tegra194-pcie", "snps,dw-pcie";
1201 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>;
1202 reg = <0x00 0x14120000 0x0 0x00020000 /* appl registers (128K) */
1203 0x00 0x32000000 0x0 0x00040000 /* configuration space (256K) */
1204 0x00 0x32040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */
1205 0x00 0x32080000 0x0 0x00040000>; /* DBI reg space (256K) */
1206 reg-names = "appl", "config", "atu_dma", "dbi";
1208 status = "disabled";
1210 #address-cells = <3>;
1212 device_type = "pci";
1215 linux,pci-domain = <2>;
1217 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_2>;
1218 clock-names = "core";
1220 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_2_APB>,
1221 <&bpmp TEGRA194_RESET_PEX0_CORE_2>;
1222 reset-names = "apb", "core";
1224 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
1225 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
1226 interrupt-names = "intr", "msi";
1228 #interrupt-cells = <1>;
1229 interrupt-map-mask = <0 0 0 0>;
1230 interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
1232 nvidia,bpmp = <&bpmp 2>;
1235 nvidia,aspm-cmrt-us = <60>;
1236 nvidia,aspm-pwr-on-t-us = <20>;
1237 nvidia,aspm-l0s-entrance-latency-us = <3>;
1239 bus-range = <0x0 0xff>;
1240 ranges = <0x81000000 0x0 0x32100000 0x0 0x32100000 0x0 0x00100000 /* downstream I/O (1MB) */
1241 0xc2000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000 /* prefetchable memory (768MB) */
1242 0x82000000 0x0 0x40000000 0x12 0x70000000 0x0 0x10000000>; /* non-prefetchable memory (256MB) */
1246 compatible = "nvidia,tegra194-pcie", "snps,dw-pcie";
1247 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>;
1248 reg = <0x00 0x14140000 0x0 0x00020000 /* appl registers (128K) */
1249 0x00 0x34000000 0x0 0x00040000 /* configuration space (256K) */
1250 0x00 0x34040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */
1251 0x00 0x34080000 0x0 0x00040000>; /* DBI reg space (256K) */
1252 reg-names = "appl", "config", "atu_dma", "dbi";
1254 status = "disabled";
1256 #address-cells = <3>;
1258 device_type = "pci";
1261 linux,pci-domain = <3>;
1263 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_3>;
1264 clock-names = "core";
1266 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_3_APB>,
1267 <&bpmp TEGRA194_RESET_PEX0_CORE_3>;
1268 reset-names = "apb", "core";
1270 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
1271 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
1272 interrupt-names = "intr", "msi";
1274 #interrupt-cells = <1>;
1275 interrupt-map-mask = <0 0 0 0>;
1276 interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
1278 nvidia,bpmp = <&bpmp 3>;
1281 nvidia,aspm-cmrt-us = <60>;
1282 nvidia,aspm-pwr-on-t-us = <20>;
1283 nvidia,aspm-l0s-entrance-latency-us = <3>;
1285 bus-range = <0x0 0xff>;
1286 ranges = <0x81000000 0x0 0x34100000 0x0 0x34100000 0x0 0x00100000 /* downstream I/O (1MB) */
1287 0xc2000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000 /* prefetchable memory (768MB) */
1288 0x82000000 0x0 0x40000000 0x12 0xb0000000 0x0 0x10000000>; /* non-prefetchable memory (256MB) */
1292 compatible = "nvidia,tegra194-pcie", "snps,dw-pcie";
1293 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>;
1294 reg = <0x00 0x14160000 0x0 0x00020000 /* appl registers (128K) */
1295 0x00 0x36000000 0x0 0x00040000 /* configuration space (256K) */
1296 0x00 0x36040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */
1297 0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K) */
1298 reg-names = "appl", "config", "atu_dma", "dbi";
1300 status = "disabled";
1302 #address-cells = <3>;
1304 device_type = "pci";
1307 linux,pci-domain = <4>;
1309 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>;
1310 clock-names = "core";
1312 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>,
1313 <&bpmp TEGRA194_RESET_PEX0_CORE_4>;
1314 reset-names = "apb", "core";
1316 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
1317 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
1318 interrupt-names = "intr", "msi";
1320 #interrupt-cells = <1>;
1321 interrupt-map-mask = <0 0 0 0>;
1322 interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
1324 nvidia,bpmp = <&bpmp 4>;
1327 nvidia,aspm-cmrt-us = <60>;
1328 nvidia,aspm-pwr-on-t-us = <20>;
1329 nvidia,aspm-l0s-entrance-latency-us = <3>;
1331 bus-range = <0x0 0xff>;
1332 ranges = <0x81000000 0x0 0x36100000 0x0 0x36100000 0x0 0x00100000 /* downstream I/O (1MB) */
1333 0xc2000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000 /* prefetchable memory (13GB) */
1334 0x82000000 0x0 0x40000000 0x17 0x40000000 0x0 0xc0000000>; /* non-prefetchable memory (3GB) */
1338 compatible = "nvidia,tegra194-pcie", "snps,dw-pcie";
1339 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>;
1340 reg = <0x00 0x14180000 0x0 0x00020000 /* appl registers (128K) */
1341 0x00 0x38000000 0x0 0x00040000 /* configuration space (256K) */
1342 0x00 0x38040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */
1343 0x00 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */
1344 reg-names = "appl", "config", "atu_dma", "dbi";
1346 status = "disabled";
1348 #address-cells = <3>;
1350 device_type = "pci";
1353 linux,pci-domain = <0>;
1355 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>;
1356 clock-names = "core";
1358 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>,
1359 <&bpmp TEGRA194_RESET_PEX0_CORE_0>;
1360 reset-names = "apb", "core";
1362 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
1363 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
1364 interrupt-names = "intr", "msi";
1366 #interrupt-cells = <1>;
1367 interrupt-map-mask = <0 0 0 0>;
1368 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1370 nvidia,bpmp = <&bpmp 0>;
1373 nvidia,aspm-cmrt-us = <60>;
1374 nvidia,aspm-pwr-on-t-us = <20>;
1375 nvidia,aspm-l0s-entrance-latency-us = <3>;
1377 bus-range = <0x0 0xff>;
1378 ranges = <0x81000000 0x0 0x38100000 0x0 0x38100000 0x0 0x00100000 /* downstream I/O (1MB) */
1379 0xc2000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000 /* prefetchable memory (13GB) */
1380 0x82000000 0x0 0x40000000 0x1b 0x40000000 0x0 0xc0000000>; /* non-prefetchable memory (3GB) */
1384 compatible = "nvidia,tegra194-pcie", "snps,dw-pcie";
1385 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>;
1386 reg = <0x00 0x141a0000 0x0 0x00020000 /* appl registers (128K) */
1387 0x00 0x3a000000 0x0 0x00040000 /* configuration space (256K) */
1388 0x00 0x3a040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */
1389 0x00 0x3a080000 0x0 0x00040000>; /* DBI reg space (256K) */
1390 reg-names = "appl", "config", "atu_dma", "dbi";
1392 status = "disabled";
1394 #address-cells = <3>;
1396 device_type = "pci";
1399 linux,pci-domain = <5>;
1401 pinctrl-names = "default";
1402 pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>;
1404 clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>,
1405 <&bpmp TEGRA194_CLK_PEX1_CORE_5M>;
1406 clock-names = "core", "core_m";
1408 resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>,
1409 <&bpmp TEGRA194_RESET_PEX1_CORE_5>;
1410 reset-names = "apb", "core";
1412 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
1413 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
1414 interrupt-names = "intr", "msi";
1416 nvidia,bpmp = <&bpmp 5>;
1418 #interrupt-cells = <1>;
1419 interrupt-map-mask = <0 0 0 0>;
1420 interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
1423 nvidia,aspm-cmrt-us = <60>;
1424 nvidia,aspm-pwr-on-t-us = <20>;
1425 nvidia,aspm-l0s-entrance-latency-us = <3>;
1427 bus-range = <0x0 0xff>;
1428 ranges = <0x81000000 0x0 0x3a100000 0x0 0x3a100000 0x0 0x00100000 /* downstream I/O (1MB) */
1429 0xc2000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000 /* prefetchable memory (13GB) */
1430 0x82000000 0x0 0x40000000 0x1f 0x40000000 0x0 0xc0000000>; /* non-prefetchable memory (3GB) */
1434 compatible = "nvidia,tegra194-sysram", "mmio-sram";
1435 reg = <0x0 0x40000000 0x0 0x50000>;
1436 #address-cells = <1>;
1438 ranges = <0x0 0x0 0x40000000 0x50000>;
1440 cpu_bpmp_tx: shmem@4e000 {
1441 compatible = "nvidia,tegra194-bpmp-shmem";
1442 reg = <0x4e000 0x1000>;
1443 label = "cpu-bpmp-tx";
1447 cpu_bpmp_rx: shmem@4f000 {
1448 compatible = "nvidia,tegra194-bpmp-shmem";
1449 reg = <0x4f000 0x1000>;
1450 label = "cpu-bpmp-rx";
1456 compatible = "nvidia,tegra186-bpmp";
1457 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB
1458 TEGRA_HSP_DB_MASTER_BPMP>;
1459 shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>;
1462 #power-domain-cells = <1>;
1465 compatible = "nvidia,tegra186-bpmp-i2c";
1466 nvidia,bpmp-bus-id = <5>;
1467 #address-cells = <1>;
1471 bpmp_thermal: thermal {
1472 compatible = "nvidia,tegra186-bpmp-thermal";
1473 #thermal-sensor-cells = <1>;
1478 #address-cells = <1>;
1482 compatible = "nvidia,tegra194-carmel";
1483 device_type = "cpu";
1485 enable-method = "psci";
1486 i-cache-size = <131072>;
1487 i-cache-line-size = <64>;
1488 i-cache-sets = <512>;
1489 d-cache-size = <65536>;
1490 d-cache-line-size = <64>;
1491 d-cache-sets = <256>;
1492 next-level-cache = <&l2c_0>;
1496 compatible = "nvidia,tegra194-carmel";
1497 device_type = "cpu";
1499 enable-method = "psci";
1500 i-cache-size = <131072>;
1501 i-cache-line-size = <64>;
1502 i-cache-sets = <512>;
1503 d-cache-size = <65536>;
1504 d-cache-line-size = <64>;
1505 d-cache-sets = <256>;
1506 next-level-cache = <&l2c_0>;
1510 compatible = "nvidia,tegra194-carmel";
1511 device_type = "cpu";
1513 enable-method = "psci";
1514 i-cache-size = <131072>;
1515 i-cache-line-size = <64>;
1516 i-cache-sets = <512>;
1517 d-cache-size = <65536>;
1518 d-cache-line-size = <64>;
1519 d-cache-sets = <256>;
1520 next-level-cache = <&l2c_1>;
1524 compatible = "nvidia,tegra194-carmel";
1525 device_type = "cpu";
1527 enable-method = "psci";
1528 i-cache-size = <131072>;
1529 i-cache-line-size = <64>;
1530 i-cache-sets = <512>;
1531 d-cache-size = <65536>;
1532 d-cache-line-size = <64>;
1533 d-cache-sets = <256>;
1534 next-level-cache = <&l2c_1>;
1538 compatible = "nvidia,tegra194-carmel";
1539 device_type = "cpu";
1541 enable-method = "psci";
1542 i-cache-size = <131072>;
1543 i-cache-line-size = <64>;
1544 i-cache-sets = <512>;
1545 d-cache-size = <65536>;
1546 d-cache-line-size = <64>;
1547 d-cache-sets = <256>;
1548 next-level-cache = <&l2c_2>;
1552 compatible = "nvidia,tegra194-carmel";
1553 device_type = "cpu";
1555 enable-method = "psci";
1556 i-cache-size = <131072>;
1557 i-cache-line-size = <64>;
1558 i-cache-sets = <512>;
1559 d-cache-size = <65536>;
1560 d-cache-line-size = <64>;
1561 d-cache-sets = <256>;
1562 next-level-cache = <&l2c_2>;
1566 compatible = "nvidia,tegra194-carmel";
1567 device_type = "cpu";
1569 enable-method = "psci";
1570 i-cache-size = <131072>;
1571 i-cache-line-size = <64>;
1572 i-cache-sets = <512>;
1573 d-cache-size = <65536>;
1574 d-cache-line-size = <64>;
1575 d-cache-sets = <256>;
1576 next-level-cache = <&l2c_3>;
1580 compatible = "nvidia,tegra194-carmel";
1581 device_type = "cpu";
1583 enable-method = "psci";
1584 i-cache-size = <131072>;
1585 i-cache-line-size = <64>;
1586 i-cache-sets = <512>;
1587 d-cache-size = <65536>;
1588 d-cache-line-size = <64>;
1589 d-cache-sets = <256>;
1590 next-level-cache = <&l2c_3>;
1636 cache-size = <2097152>;
1637 cache-line-size = <64>;
1638 cache-sets = <2048>;
1639 next-level-cache = <&l3c>;
1643 cache-size = <2097152>;
1644 cache-line-size = <64>;
1645 cache-sets = <2048>;
1646 next-level-cache = <&l3c>;
1650 cache-size = <2097152>;
1651 cache-line-size = <64>;
1652 cache-sets = <2048>;
1653 next-level-cache = <&l3c>;
1657 cache-size = <2097152>;
1658 cache-line-size = <64>;
1659 cache-sets = <2048>;
1660 next-level-cache = <&l3c>;
1664 cache-size = <4194304>;
1665 cache-line-size = <64>;
1666 cache-sets = <4096>;
1671 compatible = "arm,psci-1.0";
1677 compatible = "nvidia,tegra194-tcu";
1678 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>,
1679 <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>;
1680 mbox-names = "rx", "tx";
1685 thermal-sensors = <&{/bpmp/thermal}
1686 TEGRA194_BPMP_THERMAL_ZONE_CPU>;
1687 status = "disabled";
1691 thermal-sensors = <&{/bpmp/thermal}
1692 TEGRA194_BPMP_THERMAL_ZONE_GPU>;
1693 status = "disabled";
1697 thermal-sensors = <&{/bpmp/thermal}
1698 TEGRA194_BPMP_THERMAL_ZONE_AUX>;
1699 status = "disabled";
1703 thermal-sensors = <&{/bpmp/thermal}
1704 TEGRA194_BPMP_THERMAL_ZONE_PLLX>;
1705 status = "disabled";
1709 thermal-sensors = <&{/bpmp/thermal}
1710 TEGRA194_BPMP_THERMAL_ZONE_AO>;
1711 status = "disabled";
1715 thermal-sensors = <&{/bpmp/thermal}
1716 TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX>;
1717 status = "disabled";
1722 compatible = "arm,armv8-timer";
1723 interrupts = <GIC_PPI 13
1724 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1726 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1728 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1730 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
1731 interrupt-parent = <&gic>;