1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra210-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra210-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
7 #include <dt-bindings/reset/tegra210-car.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/thermal/tegra124-soctherm.h>
12 compatible = "nvidia,tegra210";
13 interrupt-parent = <&lic>;
18 compatible = "nvidia,tegra210-pcie";
20 reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */
21 0x0 0x01003800 0x0 0x00000800 /* AFI registers */
22 0x0 0x02000000 0x0 0x10000000>; /* configuration space */
23 reg-names = "pads", "afi", "cs";
24 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
25 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
26 interrupt-names = "intr", "msi";
28 #interrupt-cells = <1>;
29 interrupt-map-mask = <0 0 0 0>;
30 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
32 bus-range = <0x00 0xff>;
36 ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000 /* port 0 configuration space */
37 0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000 /* port 1 configuration space */
38 0x81000000 0 0x0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */
39 0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */
40 0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
42 clocks = <&tegra_car TEGRA210_CLK_PCIE>,
43 <&tegra_car TEGRA210_CLK_AFI>,
44 <&tegra_car TEGRA210_CLK_PLL_E>,
45 <&tegra_car TEGRA210_CLK_CML0>;
46 clock-names = "pex", "afi", "pll_e", "cml";
47 resets = <&tegra_car 70>,
50 reset-names = "pex", "afi", "pcie_x";
52 pinctrl-names = "default", "idle";
53 pinctrl-0 = <&pex_dpd_disable>;
54 pinctrl-1 = <&pex_dpd_enable>;
60 assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
61 reg = <0x000800 0 0 0 0>;
62 bus-range = <0x00 0xff>;
69 nvidia,num-lanes = <4>;
74 assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
75 reg = <0x001000 0 0 0 0>;
76 bus-range = <0x00 0xff>;
83 nvidia,num-lanes = <1>;
88 compatible = "nvidia,tegra210-host1x", "simple-bus";
89 reg = <0x0 0x50000000 0x0 0x00034000>;
90 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
91 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
92 clocks = <&tegra_car TEGRA210_CLK_HOST1X>;
93 clock-names = "host1x";
94 resets = <&tegra_car 28>;
95 reset-names = "host1x";
100 ranges = <0x0 0x54000000 0x0 0x54000000 0x0 0x01000000>;
102 iommus = <&mc TEGRA_SWGROUP_HC>;
104 dpaux1: dpaux@54040000 {
105 compatible = "nvidia,tegra210-dpaux";
106 reg = <0x0 0x54040000 0x0 0x00040000>;
107 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
108 clocks = <&tegra_car TEGRA210_CLK_DPAUX1>,
109 <&tegra_car TEGRA210_CLK_PLL_DP>;
110 clock-names = "dpaux", "parent";
111 resets = <&tegra_car 207>;
112 reset-names = "dpaux";
113 power-domains = <&pd_sor>;
116 state_dpaux1_aux: pinmux-aux {
121 state_dpaux1_i2c: pinmux-i2c {
126 state_dpaux1_off: pinmux-off {
132 #address-cells = <1>;
138 compatible = "nvidia,tegra210-vi";
139 reg = <0x0 0x54080000 0x0 0x00040000>;
140 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
145 compatible = "nvidia,tegra210-tsec";
146 reg = <0x0 0x54100000 0x0 0x00040000>;
150 compatible = "nvidia,tegra210-dc";
151 reg = <0x0 0x54200000 0x0 0x00040000>;
152 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
153 clocks = <&tegra_car TEGRA210_CLK_DISP1>,
154 <&tegra_car TEGRA210_CLK_PLL_P>;
155 clock-names = "dc", "parent";
156 resets = <&tegra_car 27>;
159 iommus = <&mc TEGRA_SWGROUP_DC>;
165 compatible = "nvidia,tegra210-dc";
166 reg = <0x0 0x54240000 0x0 0x00040000>;
167 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
168 clocks = <&tegra_car TEGRA210_CLK_DISP2>,
169 <&tegra_car TEGRA210_CLK_PLL_P>;
170 clock-names = "dc", "parent";
171 resets = <&tegra_car 26>;
174 iommus = <&mc TEGRA_SWGROUP_DCB>;
180 compatible = "nvidia,tegra210-dsi";
181 reg = <0x0 0x54300000 0x0 0x00040000>;
182 clocks = <&tegra_car TEGRA210_CLK_DSIA>,
183 <&tegra_car TEGRA210_CLK_DSIALP>,
184 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>;
185 clock-names = "dsi", "lp", "parent";
186 resets = <&tegra_car 48>;
188 power-domains = <&pd_sor>;
189 nvidia,mipi-calibrate = <&mipi 0x0c0>; /* DSIA & DSIB pads */
193 #address-cells = <1>;
198 compatible = "nvidia,tegra210-vic";
199 reg = <0x0 0x54340000 0x0 0x00040000>;
200 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
201 clocks = <&tegra_car TEGRA210_CLK_VIC03>;
203 resets = <&tegra_car 178>;
206 iommus = <&mc TEGRA_SWGROUP_VIC>;
207 power-domains = <&pd_vic>;
211 compatible = "nvidia,tegra210-nvjpg";
212 reg = <0x0 0x54380000 0x0 0x00040000>;
217 compatible = "nvidia,tegra210-dsi";
218 reg = <0x0 0x54400000 0x0 0x00040000>;
219 clocks = <&tegra_car TEGRA210_CLK_DSIB>,
220 <&tegra_car TEGRA210_CLK_DSIBLP>,
221 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>;
222 clock-names = "dsi", "lp", "parent";
223 resets = <&tegra_car 82>;
225 power-domains = <&pd_sor>;
226 nvidia,mipi-calibrate = <&mipi 0x300>; /* DSIC & DSID pads */
230 #address-cells = <1>;
235 compatible = "nvidia,tegra210-nvdec";
236 reg = <0x0 0x54480000 0x0 0x00040000>;
241 compatible = "nvidia,tegra210-nvenc";
242 reg = <0x0 0x544c0000 0x0 0x00040000>;
247 compatible = "nvidia,tegra210-tsec";
248 reg = <0x0 0x54500000 0x0 0x00040000>;
253 compatible = "nvidia,tegra210-sor";
254 reg = <0x0 0x54540000 0x0 0x00040000>;
255 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
256 clocks = <&tegra_car TEGRA210_CLK_SOR0>,
257 <&tegra_car TEGRA210_CLK_SOR0_OUT>,
258 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>,
259 <&tegra_car TEGRA210_CLK_PLL_DP>,
260 <&tegra_car TEGRA210_CLK_SOR_SAFE>;
261 clock-names = "sor", "out", "parent", "dp", "safe";
262 resets = <&tegra_car 182>;
264 pinctrl-0 = <&state_dpaux_aux>;
265 pinctrl-1 = <&state_dpaux_i2c>;
266 pinctrl-2 = <&state_dpaux_off>;
267 pinctrl-names = "aux", "i2c", "off";
268 power-domains = <&pd_sor>;
273 compatible = "nvidia,tegra210-sor1";
274 reg = <0x0 0x54580000 0x0 0x00040000>;
275 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
276 clocks = <&tegra_car TEGRA210_CLK_SOR1>,
277 <&tegra_car TEGRA210_CLK_SOR1_OUT>,
278 <&tegra_car TEGRA210_CLK_PLL_D2_OUT0>,
279 <&tegra_car TEGRA210_CLK_PLL_DP>,
280 <&tegra_car TEGRA210_CLK_SOR_SAFE>;
281 clock-names = "sor", "out", "parent", "dp", "safe";
282 resets = <&tegra_car 183>;
284 pinctrl-0 = <&state_dpaux1_aux>;
285 pinctrl-1 = <&state_dpaux1_i2c>;
286 pinctrl-2 = <&state_dpaux1_off>;
287 pinctrl-names = "aux", "i2c", "off";
288 power-domains = <&pd_sor>;
292 dpaux: dpaux@545c0000 {
293 compatible = "nvidia,tegra124-dpaux";
294 reg = <0x0 0x545c0000 0x0 0x00040000>;
295 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
296 clocks = <&tegra_car TEGRA210_CLK_DPAUX>,
297 <&tegra_car TEGRA210_CLK_PLL_DP>;
298 clock-names = "dpaux", "parent";
299 resets = <&tegra_car 181>;
300 reset-names = "dpaux";
301 power-domains = <&pd_sor>;
304 state_dpaux_aux: pinmux-aux {
309 state_dpaux_i2c: pinmux-i2c {
314 state_dpaux_off: pinmux-off {
320 #address-cells = <1>;
326 compatible = "nvidia,tegra210-isp";
327 reg = <0x0 0x54600000 0x0 0x00040000>;
328 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
333 compatible = "nvidia,tegra210-isp";
334 reg = <0x0 0x54680000 0x0 0x00040000>;
335 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
340 compatible = "nvidia,tegra210-i2c-vi";
341 reg = <0x0 0x546c0000 0x0 0x00040000>;
342 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
347 gic: interrupt-controller@50041000 {
348 compatible = "arm,gic-400";
349 #interrupt-cells = <3>;
350 interrupt-controller;
351 reg = <0x0 0x50041000 0x0 0x1000>,
352 <0x0 0x50042000 0x0 0x2000>,
353 <0x0 0x50044000 0x0 0x2000>,
354 <0x0 0x50046000 0x0 0x2000>;
355 interrupts = <GIC_PPI 9
356 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
357 interrupt-parent = <&gic>;
361 compatible = "nvidia,gm20b";
362 reg = <0x0 0x57000000 0x0 0x01000000>,
363 <0x0 0x58000000 0x0 0x01000000>;
364 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
365 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
366 interrupt-names = "stall", "nonstall";
367 clocks = <&tegra_car TEGRA210_CLK_GPU>,
368 <&tegra_car TEGRA210_CLK_PLL_P_OUT5>,
369 <&tegra_car TEGRA210_CLK_PLL_G_REF>;
370 clock-names = "gpu", "pwr", "ref";
371 resets = <&tegra_car 184>;
374 iommus = <&mc TEGRA_SWGROUP_GPU>;
379 lic: interrupt-controller@60004000 {
380 compatible = "nvidia,tegra210-ictlr";
381 reg = <0x0 0x60004000 0x0 0x40>, /* primary controller */
382 <0x0 0x60004100 0x0 0x40>, /* secondary controller */
383 <0x0 0x60004200 0x0 0x40>, /* tertiary controller */
384 <0x0 0x60004300 0x0 0x40>, /* quaternary controller */
385 <0x0 0x60004400 0x0 0x40>, /* quinary controller */
386 <0x0 0x60004500 0x0 0x40>; /* senary controller */
387 interrupt-controller;
388 #interrupt-cells = <3>;
389 interrupt-parent = <&gic>;
393 compatible = "nvidia,tegra210-timer";
394 reg = <0x0 0x60005000 0x0 0x400>;
395 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
396 <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
397 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
398 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
399 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
400 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
401 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
402 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
403 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
404 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
405 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
406 <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
407 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
408 <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
409 clocks = <&tegra_car TEGRA210_CLK_TIMER>;
410 clock-names = "timer";
413 tegra_car: clock@60006000 {
414 compatible = "nvidia,tegra210-car";
415 reg = <0x0 0x60006000 0x0 0x1000>;
420 flow-controller@60007000 {
421 compatible = "nvidia,tegra210-flowctrl";
422 reg = <0x0 0x60007000 0x0 0x1000>;
425 gpio: gpio@6000d000 {
426 compatible = "nvidia,tegra210-gpio", "nvidia,tegra30-gpio";
427 reg = <0x0 0x6000d000 0x0 0x1000>;
428 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
429 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
430 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
431 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
432 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
433 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
434 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
435 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
438 #interrupt-cells = <2>;
439 interrupt-controller;
442 apbdma: dma@60020000 {
443 compatible = "nvidia,tegra210-apbdma", "nvidia,tegra148-apbdma";
444 reg = <0x0 0x60020000 0x0 0x1400>;
445 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
446 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
447 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
448 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
449 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
450 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
451 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
452 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
453 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
454 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
455 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
456 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
457 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
458 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
459 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
460 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
461 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
462 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
463 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
464 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
465 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
466 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
467 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
468 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
469 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
470 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
471 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
472 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
473 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
474 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
475 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
476 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
477 clocks = <&tegra_car TEGRA210_CLK_APBDMA>;
479 resets = <&tegra_car 34>;
485 compatible = "nvidia,tegra210-apbmisc", "nvidia,tegra20-apbmisc";
486 reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */
487 <0x0 0x70000008 0x0 0x04>; /* Strapping options */
490 pinmux: pinmux@700008d4 {
491 compatible = "nvidia,tegra210-pinmux";
492 reg = <0x0 0x700008d4 0x0 0x29c>, /* Pad control registers */
493 <0x0 0x70003000 0x0 0x294>; /* Mux registers */
494 sdmmc1_3v3_drv: sdmmc1-3v3-drv {
496 nvidia,pins = "drive_sdmmc1";
497 nvidia,pull-down-strength = <0x8>;
498 nvidia,pull-up-strength = <0x8>;
501 sdmmc1_1v8_drv: sdmmc1-1v8-drv {
503 nvidia,pins = "drive_sdmmc1";
504 nvidia,pull-down-strength = <0x4>;
505 nvidia,pull-up-strength = <0x3>;
508 sdmmc2_1v8_drv: sdmmc2-1v8-drv {
510 nvidia,pins = "drive_sdmmc2";
511 nvidia,pull-down-strength = <0x10>;
512 nvidia,pull-up-strength = <0x10>;
515 sdmmc3_3v3_drv: sdmmc3-3v3-drv {
517 nvidia,pins = "drive_sdmmc3";
518 nvidia,pull-down-strength = <0x8>;
519 nvidia,pull-up-strength = <0x8>;
522 sdmmc3_1v8_drv: sdmmc3-1v8-drv {
524 nvidia,pins = "drive_sdmmc3";
525 nvidia,pull-down-strength = <0x4>;
526 nvidia,pull-up-strength = <0x3>;
529 sdmmc4_1v8_drv: sdmmc4-1v8-drv {
531 nvidia,pins = "drive_sdmmc4";
532 nvidia,pull-down-strength = <0x10>;
533 nvidia,pull-up-strength = <0x10>;
539 * There are two serial driver i.e. 8250 based simple serial
540 * driver and APB DMA based serial driver for higher baudrate
541 * and performance. To enable the 8250 based driver, the compatible
542 * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable
543 * the APB DMA based serial driver, the compatible is
544 * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart".
546 uarta: serial@70006000 {
547 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
548 reg = <0x0 0x70006000 0x0 0x40>;
550 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
551 clocks = <&tegra_car TEGRA210_CLK_UARTA>;
552 clock-names = "serial";
553 resets = <&tegra_car 6>;
554 reset-names = "serial";
555 dmas = <&apbdma 8>, <&apbdma 8>;
556 dma-names = "rx", "tx";
560 uartb: serial@70006040 {
561 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
562 reg = <0x0 0x70006040 0x0 0x40>;
564 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
565 clocks = <&tegra_car TEGRA210_CLK_UARTB>;
566 clock-names = "serial";
567 resets = <&tegra_car 7>;
568 reset-names = "serial";
569 dmas = <&apbdma 9>, <&apbdma 9>;
570 dma-names = "rx", "tx";
574 uartc: serial@70006200 {
575 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
576 reg = <0x0 0x70006200 0x0 0x40>;
578 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
579 clocks = <&tegra_car TEGRA210_CLK_UARTC>;
580 clock-names = "serial";
581 resets = <&tegra_car 55>;
582 reset-names = "serial";
583 dmas = <&apbdma 10>, <&apbdma 10>;
584 dma-names = "rx", "tx";
588 uartd: serial@70006300 {
589 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
590 reg = <0x0 0x70006300 0x0 0x40>;
592 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
593 clocks = <&tegra_car TEGRA210_CLK_UARTD>;
594 clock-names = "serial";
595 resets = <&tegra_car 65>;
596 reset-names = "serial";
597 dmas = <&apbdma 19>, <&apbdma 19>;
598 dma-names = "rx", "tx";
603 compatible = "nvidia,tegra210-pwm", "nvidia,tegra20-pwm";
604 reg = <0x0 0x7000a000 0x0 0x100>;
606 clocks = <&tegra_car TEGRA210_CLK_PWM>;
608 resets = <&tegra_car 17>;
614 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c";
615 reg = <0x0 0x7000c000 0x0 0x100>;
616 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
617 #address-cells = <1>;
619 clocks = <&tegra_car TEGRA210_CLK_I2C1>;
620 clock-names = "div-clk";
621 resets = <&tegra_car 12>;
623 dmas = <&apbdma 21>, <&apbdma 21>;
624 dma-names = "rx", "tx";
629 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c";
630 reg = <0x0 0x7000c400 0x0 0x100>;
631 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
632 #address-cells = <1>;
634 clocks = <&tegra_car TEGRA210_CLK_I2C2>;
635 clock-names = "div-clk";
636 resets = <&tegra_car 54>;
638 dmas = <&apbdma 22>, <&apbdma 22>;
639 dma-names = "rx", "tx";
644 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c";
645 reg = <0x0 0x7000c500 0x0 0x100>;
646 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
647 #address-cells = <1>;
649 clocks = <&tegra_car TEGRA210_CLK_I2C3>;
650 clock-names = "div-clk";
651 resets = <&tegra_car 67>;
653 dmas = <&apbdma 23>, <&apbdma 23>;
654 dma-names = "rx", "tx";
659 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c";
660 reg = <0x0 0x7000c700 0x0 0x100>;
661 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
662 #address-cells = <1>;
664 clocks = <&tegra_car TEGRA210_CLK_I2C4>;
665 clock-names = "div-clk";
666 resets = <&tegra_car 103>;
668 dmas = <&apbdma 26>, <&apbdma 26>;
669 dma-names = "rx", "tx";
670 pinctrl-0 = <&state_dpaux1_i2c>;
671 pinctrl-1 = <&state_dpaux1_off>;
672 pinctrl-names = "default", "idle";
677 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c";
678 reg = <0x0 0x7000d000 0x0 0x100>;
679 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
680 #address-cells = <1>;
682 clocks = <&tegra_car TEGRA210_CLK_I2C5>;
683 clock-names = "div-clk";
684 resets = <&tegra_car 47>;
686 dmas = <&apbdma 24>, <&apbdma 24>;
687 dma-names = "rx", "tx";
692 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c";
693 reg = <0x0 0x7000d100 0x0 0x100>;
694 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
695 #address-cells = <1>;
697 clocks = <&tegra_car TEGRA210_CLK_I2C6>;
698 clock-names = "div-clk";
699 resets = <&tegra_car 166>;
701 dmas = <&apbdma 30>, <&apbdma 30>;
702 dma-names = "rx", "tx";
703 pinctrl-0 = <&state_dpaux_i2c>;
704 pinctrl-1 = <&state_dpaux_off>;
705 pinctrl-names = "default", "idle";
710 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
711 reg = <0x0 0x7000d400 0x0 0x200>;
712 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
713 #address-cells = <1>;
715 clocks = <&tegra_car TEGRA210_CLK_SBC1>;
717 resets = <&tegra_car 41>;
719 dmas = <&apbdma 15>, <&apbdma 15>;
720 dma-names = "rx", "tx";
725 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
726 reg = <0x0 0x7000d600 0x0 0x200>;
727 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
728 #address-cells = <1>;
730 clocks = <&tegra_car TEGRA210_CLK_SBC2>;
732 resets = <&tegra_car 44>;
734 dmas = <&apbdma 16>, <&apbdma 16>;
735 dma-names = "rx", "tx";
740 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
741 reg = <0x0 0x7000d800 0x0 0x200>;
742 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
743 #address-cells = <1>;
745 clocks = <&tegra_car TEGRA210_CLK_SBC3>;
747 resets = <&tegra_car 46>;
749 dmas = <&apbdma 17>, <&apbdma 17>;
750 dma-names = "rx", "tx";
755 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
756 reg = <0x0 0x7000da00 0x0 0x200>;
757 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
758 #address-cells = <1>;
760 clocks = <&tegra_car TEGRA210_CLK_SBC4>;
762 resets = <&tegra_car 68>;
764 dmas = <&apbdma 18>, <&apbdma 18>;
765 dma-names = "rx", "tx";
770 compatible = "nvidia,tegra210-rtc", "nvidia,tegra20-rtc";
771 reg = <0x0 0x7000e000 0x0 0x100>;
772 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
773 clocks = <&tegra_car TEGRA210_CLK_RTC>;
778 compatible = "nvidia,tegra210-pmc";
779 reg = <0x0 0x7000e400 0x0 0x400>;
780 clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>;
781 clock-names = "pclk", "clk32k_in";
785 clocks = <&tegra_car TEGRA210_CLK_APE>,
786 <&tegra_car TEGRA210_CLK_APB2APE>;
787 resets = <&tegra_car 198>;
788 #power-domain-cells = <0>;
792 clocks = <&tegra_car TEGRA210_CLK_SOR0>,
793 <&tegra_car TEGRA210_CLK_SOR1>,
794 <&tegra_car TEGRA210_CLK_CSI>,
795 <&tegra_car TEGRA210_CLK_DSIA>,
796 <&tegra_car TEGRA210_CLK_DSIB>,
797 <&tegra_car TEGRA210_CLK_DPAUX>,
798 <&tegra_car TEGRA210_CLK_DPAUX1>,
799 <&tegra_car TEGRA210_CLK_MIPI_CAL>;
800 resets = <&tegra_car TEGRA210_CLK_SOR0>,
801 <&tegra_car TEGRA210_CLK_SOR1>,
802 <&tegra_car TEGRA210_CLK_CSI>,
803 <&tegra_car TEGRA210_CLK_DSIA>,
804 <&tegra_car TEGRA210_CLK_DSIB>,
805 <&tegra_car TEGRA210_CLK_DPAUX>,
806 <&tegra_car TEGRA210_CLK_DPAUX1>,
807 <&tegra_car TEGRA210_CLK_MIPI_CAL>;
808 #power-domain-cells = <0>;
812 clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>;
813 resets = <&tegra_car TEGRA210_CLK_XUSB_SS>;
814 #power-domain-cells = <0>;
818 clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>;
819 resets = <&tegra_car 95>;
820 #power-domain-cells = <0>;
824 clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>;
825 resets = <&tegra_car TEGRA210_CLK_XUSB_HOST>;
826 #power-domain-cells = <0>;
830 clocks = <&tegra_car TEGRA210_CLK_VIC03>;
832 resets = <&tegra_car 178>;
834 #power-domain-cells = <0>;
838 sdmmc1_3v3: sdmmc1-3v3 {
840 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
843 sdmmc1_1v8: sdmmc1-1v8 {
845 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
848 sdmmc3_3v3: sdmmc3-3v3 {
850 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
853 sdmmc3_1v8: sdmmc3-1v8 {
855 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
858 pex_dpd_disable: pex_en {
860 pins = "pex-bias", "pex-clk1", "pex-clk2";
865 pex_dpd_enable: pex_dis {
867 pins = "pex-bias", "pex-clk1", "pex-clk2";
874 compatible = "nvidia,tegra210-efuse";
875 reg = <0x0 0x7000f800 0x0 0x400>;
876 clocks = <&tegra_car TEGRA210_CLK_FUSE>;
877 clock-names = "fuse";
878 resets = <&tegra_car 39>;
879 reset-names = "fuse";
882 mc: memory-controller@70019000 {
883 compatible = "nvidia,tegra210-mc";
884 reg = <0x0 0x70019000 0x0 0x1000>;
885 clocks = <&tegra_car TEGRA210_CLK_MC>;
888 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
894 compatible = "nvidia,tegra210-ahci";
895 reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */
896 <0x0 0x70020000 0x0 0x7000>, /* SATA */
897 <0x0 0x70001100 0x0 0x1000>; /* SATA AUX */
898 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
899 clocks = <&tegra_car TEGRA210_CLK_SATA>,
900 <&tegra_car TEGRA210_CLK_SATA_OOB>;
901 clock-names = "sata", "sata-oob";
902 resets = <&tegra_car 124>,
905 reset-names = "sata", "sata-oob", "sata-cold";
910 compatible = "nvidia,tegra210-hda", "nvidia,tegra30-hda";
911 reg = <0x0 0x70030000 0x0 0x10000>;
912 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
913 clocks = <&tegra_car TEGRA210_CLK_HDA>,
914 <&tegra_car TEGRA210_CLK_HDA2HDMI>,
915 <&tegra_car TEGRA210_CLK_HDA2CODEC_2X>;
916 clock-names = "hda", "hda2hdmi", "hda2codec_2x";
917 resets = <&tegra_car 125>, /* hda */
918 <&tegra_car 128>, /* hda2hdmi */
919 <&tegra_car 111>; /* hda2codec_2x */
920 reset-names = "hda", "hda2hdmi", "hda2codec_2x";
925 compatible = "nvidia,tegra210-xusb";
926 reg = <0x0 0x70090000 0x0 0x8000>,
927 <0x0 0x70098000 0x0 0x1000>,
928 <0x0 0x70099000 0x0 0x1000>;
929 reg-names = "hcd", "fpci", "ipfs";
931 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
932 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
934 clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>,
935 <&tegra_car TEGRA210_CLK_XUSB_HOST_SRC>,
936 <&tegra_car TEGRA210_CLK_XUSB_FALCON_SRC>,
937 <&tegra_car TEGRA210_CLK_XUSB_SS>,
938 <&tegra_car TEGRA210_CLK_XUSB_SS_DIV2>,
939 <&tegra_car TEGRA210_CLK_XUSB_SS_SRC>,
940 <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>,
941 <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>,
942 <&tegra_car TEGRA210_CLK_PLL_U_480M>,
943 <&tegra_car TEGRA210_CLK_CLK_M>,
944 <&tegra_car TEGRA210_CLK_PLL_E>;
945 clock-names = "xusb_host", "xusb_host_src",
946 "xusb_falcon_src", "xusb_ss",
947 "xusb_ss_div2", "xusb_ss_src",
948 "xusb_hs_src", "xusb_fs_src",
949 "pll_u_480m", "clk_m", "pll_e";
950 resets = <&tegra_car 89>, <&tegra_car 156>,
952 reset-names = "xusb_host", "xusb_ss", "xusb_src";
953 power-domains = <&pd_xusbhost>, <&pd_xusbss>;
954 power-domain-names = "xusb_host", "xusb_ss";
956 nvidia,xusb-padctl = <&padctl>;
961 padctl: padctl@7009f000 {
962 compatible = "nvidia,tegra210-xusb-padctl";
963 reg = <0x0 0x7009f000 0x0 0x1000>;
964 resets = <&tegra_car 142>;
965 reset-names = "padctl";
971 clocks = <&tegra_car TEGRA210_CLK_USB2_TRK>;
999 clocks = <&tegra_car TEGRA210_CLK_HSIC_TRK>;
1000 clock-names = "trk";
1001 status = "disabled";
1005 status = "disabled";
1010 status = "disabled";
1017 clocks = <&tegra_car TEGRA210_CLK_PLL_E>;
1018 clock-names = "pll";
1019 resets = <&tegra_car 205>;
1020 reset-names = "phy";
1021 status = "disabled";
1025 status = "disabled";
1030 status = "disabled";
1035 status = "disabled";
1040 status = "disabled";
1045 status = "disabled";
1050 status = "disabled";
1055 status = "disabled";
1062 clocks = <&tegra_car TEGRA210_CLK_PLL_E>;
1063 clock-names = "pll";
1064 resets = <&tegra_car 204>;
1065 reset-names = "phy";
1066 status = "disabled";
1070 status = "disabled";
1079 status = "disabled";
1083 status = "disabled";
1087 status = "disabled";
1091 status = "disabled";
1095 status = "disabled";
1099 status = "disabled";
1103 status = "disabled";
1107 status = "disabled";
1111 status = "disabled";
1117 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";
1118 reg = <0x0 0x700b0000 0x0 0x200>;
1119 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1120 clocks = <&tegra_car TEGRA210_CLK_SDMMC1>;
1121 clock-names = "sdhci";
1122 resets = <&tegra_car 14>;
1123 reset-names = "sdhci";
1124 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8",
1125 "sdmmc-3v3-drv", "sdmmc-1v8-drv";
1126 pinctrl-0 = <&sdmmc1_3v3>;
1127 pinctrl-1 = <&sdmmc1_1v8>;
1128 pinctrl-2 = <&sdmmc1_3v3_drv>;
1129 pinctrl-3 = <&sdmmc1_1v8_drv>;
1130 nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>;
1131 nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>;
1132 nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>;
1133 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>;
1134 nvidia,default-tap = <0x2>;
1135 nvidia,default-trim = <0x4>;
1136 assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>,
1137 <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>,
1138 <&tegra_car TEGRA210_CLK_PLL_C4>;
1139 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
1140 assigned-clock-rates = <200000000>, <1000000000>, <1000000000>;
1141 status = "disabled";
1145 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";
1146 reg = <0x0 0x700b0200 0x0 0x200>;
1147 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1148 clocks = <&tegra_car TEGRA210_CLK_SDMMC2>;
1149 clock-names = "sdhci";
1150 resets = <&tegra_car 9>;
1151 reset-names = "sdhci";
1152 pinctrl-names = "sdmmc-1v8-drv";
1153 pinctrl-0 = <&sdmmc2_1v8_drv>;
1154 nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>;
1155 nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>;
1156 nvidia,default-tap = <0x8>;
1157 nvidia,default-trim = <0x0>;
1158 status = "disabled";
1162 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";
1163 reg = <0x0 0x700b0400 0x0 0x200>;
1164 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1165 clocks = <&tegra_car TEGRA210_CLK_SDMMC3>;
1166 clock-names = "sdhci";
1167 resets = <&tegra_car 69>;
1168 reset-names = "sdhci";
1169 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8",
1170 "sdmmc-3v3-drv", "sdmmc-1v8-drv";
1171 pinctrl-0 = <&sdmmc3_3v3>;
1172 pinctrl-1 = <&sdmmc3_1v8>;
1173 pinctrl-2 = <&sdmmc3_3v3_drv>;
1174 pinctrl-3 = <&sdmmc3_1v8_drv>;
1175 nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>;
1176 nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>;
1177 nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>;
1178 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>;
1179 nvidia,default-tap = <0x3>;
1180 nvidia,default-trim = <0x3>;
1181 status = "disabled";
1185 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";
1186 reg = <0x0 0x700b0600 0x0 0x200>;
1187 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
1188 clocks = <&tegra_car TEGRA210_CLK_SDMMC4>;
1189 clock-names = "sdhci";
1190 resets = <&tegra_car 15>;
1191 reset-names = "sdhci";
1192 pinctrl-names = "sdmmc-3v3-drv", "sdmmc-1v8-drv";
1193 pinctrl-0 = <&sdmmc4_1v8_drv>;
1194 pinctrl-1 = <&sdmmc4_1v8_drv>;
1195 nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>;
1196 nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>;
1197 nvidia,default-tap = <0x8>;
1198 nvidia,default-trim = <0x0>;
1199 assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>,
1200 <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
1201 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
1202 nvidia,dqs-trim = <40>;
1204 status = "disabled";
1207 mipi: mipi@700e3000 {
1208 compatible = "nvidia,tegra210-mipi";
1209 reg = <0x0 0x700e3000 0x0 0x100>;
1210 clocks = <&tegra_car TEGRA210_CLK_MIPI_CAL>;
1211 clock-names = "mipi-cal";
1212 power-domains = <&pd_sor>;
1213 #nvidia,mipi-calibrate-cells = <1>;
1216 dfll: clock@70110000 {
1217 compatible = "nvidia,tegra210-dfll";
1218 reg = <0 0x70110000 0 0x100>, /* DFLL control */
1219 <0 0x70110000 0 0x100>, /* I2C output control */
1220 <0 0x70110100 0 0x100>, /* Integrated I2C controller */
1221 <0 0x70110200 0 0x100>; /* Look-up table RAM */
1222 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
1223 clocks = <&tegra_car TEGRA210_CLK_DFLL_SOC>,
1224 <&tegra_car TEGRA210_CLK_DFLL_REF>,
1225 <&tegra_car TEGRA210_CLK_I2C5>;
1226 clock-names = "soc", "ref", "i2c";
1227 resets = <&tegra_car TEGRA210_RST_DFLL_DVCO>;
1228 reset-names = "dvco";
1230 clock-output-names = "dfllCPU_out";
1231 status = "disabled";
1235 compatible = "nvidia,tegra210-aconnect";
1236 clocks = <&tegra_car TEGRA210_CLK_APE>,
1237 <&tegra_car TEGRA210_CLK_APB2APE>;
1238 clock-names = "ape", "apb2ape";
1239 power-domains = <&pd_audio>;
1240 #address-cells = <1>;
1242 ranges = <0x702c0000 0x0 0x702c0000 0x00040000>;
1243 status = "disabled";
1245 adma: dma@702e2000 {
1246 compatible = "nvidia,tegra210-adma";
1247 reg = <0x702e2000 0x2000>;
1248 interrupt-parent = <&agic>;
1249 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
1250 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
1251 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
1252 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
1253 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
1254 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
1255 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
1256 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
1257 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
1258 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
1259 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
1260 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
1261 <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
1262 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
1263 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
1264 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
1265 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
1266 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
1267 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
1268 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
1269 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
1270 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1272 clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>;
1273 clock-names = "d_audio";
1274 status = "disabled";
1277 agic: agic@702f9000 {
1278 compatible = "nvidia,tegra210-agic";
1279 #interrupt-cells = <3>;
1280 interrupt-controller;
1281 reg = <0x702f9000 0x1000>,
1282 <0x702fa000 0x2000>;
1283 interrupts = <GIC_SPI 102 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1284 clocks = <&tegra_car TEGRA210_CLK_APE>;
1285 clock-names = "clk";
1286 status = "disabled";
1291 compatible = "nvidia,tegra210-qspi";
1292 reg = <0x0 0x70410000 0x0 0x1000>;
1293 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1294 #address-cells = <1>;
1296 clocks = <&tegra_car TEGRA210_CLK_QSPI>;
1297 clock-names = "qspi";
1298 resets = <&tegra_car 211>;
1299 reset-names = "qspi";
1300 dmas = <&apbdma 5>, <&apbdma 5>;
1301 dma-names = "rx", "tx";
1302 status = "disabled";
1306 compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci";
1307 reg = <0x0 0x7d000000 0x0 0x4000>;
1308 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1310 clocks = <&tegra_car TEGRA210_CLK_USBD>;
1311 clock-names = "usb";
1312 resets = <&tegra_car 22>;
1313 reset-names = "usb";
1314 nvidia,phy = <&phy1>;
1315 status = "disabled";
1318 phy1: usb-phy@7d000000 {
1319 compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy";
1320 reg = <0x0 0x7d000000 0x0 0x4000>,
1321 <0x0 0x7d000000 0x0 0x4000>;
1323 clocks = <&tegra_car TEGRA210_CLK_USBD>,
1324 <&tegra_car TEGRA210_CLK_PLL_U>,
1325 <&tegra_car TEGRA210_CLK_USBD>;
1326 clock-names = "reg", "pll_u", "utmi-pads";
1327 resets = <&tegra_car 22>, <&tegra_car 22>;
1328 reset-names = "usb", "utmi-pads";
1329 nvidia,hssync-start-delay = <0>;
1330 nvidia,idle-wait-delay = <17>;
1331 nvidia,elastic-limit = <16>;
1332 nvidia,term-range-adj = <6>;
1333 nvidia,xcvr-setup = <9>;
1334 nvidia,xcvr-lsfslew = <0>;
1335 nvidia,xcvr-lsrslew = <3>;
1336 nvidia,hssquelch-level = <2>;
1337 nvidia,hsdiscon-level = <5>;
1338 nvidia,xcvr-hsslew = <12>;
1339 nvidia,has-utmi-pad-registers;
1340 status = "disabled";
1344 compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci";
1345 reg = <0x0 0x7d004000 0x0 0x4000>;
1346 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
1348 clocks = <&tegra_car TEGRA210_CLK_USB2>;
1349 clock-names = "usb";
1350 resets = <&tegra_car 58>;
1351 reset-names = "usb";
1352 nvidia,phy = <&phy2>;
1353 status = "disabled";
1356 phy2: usb-phy@7d004000 {
1357 compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy";
1358 reg = <0x0 0x7d004000 0x0 0x4000>,
1359 <0x0 0x7d000000 0x0 0x4000>;
1361 clocks = <&tegra_car TEGRA210_CLK_USB2>,
1362 <&tegra_car TEGRA210_CLK_PLL_U>,
1363 <&tegra_car TEGRA210_CLK_USBD>;
1364 clock-names = "reg", "pll_u", "utmi-pads";
1365 resets = <&tegra_car 58>, <&tegra_car 22>;
1366 reset-names = "usb", "utmi-pads";
1367 nvidia,hssync-start-delay = <0>;
1368 nvidia,idle-wait-delay = <17>;
1369 nvidia,elastic-limit = <16>;
1370 nvidia,term-range-adj = <6>;
1371 nvidia,xcvr-setup = <9>;
1372 nvidia,xcvr-lsfslew = <0>;
1373 nvidia,xcvr-lsrslew = <3>;
1374 nvidia,hssquelch-level = <2>;
1375 nvidia,hsdiscon-level = <5>;
1376 nvidia,xcvr-hsslew = <12>;
1377 status = "disabled";
1381 #address-cells = <1>;
1385 device_type = "cpu";
1386 compatible = "arm,cortex-a57";
1388 clocks = <&tegra_car TEGRA210_CLK_CCLK_G>,
1389 <&tegra_car TEGRA210_CLK_PLL_X>,
1390 <&tegra_car TEGRA210_CLK_PLL_P_OUT4>,
1392 clock-names = "cpu_g", "pll_x", "pll_p", "dfll";
1393 clock-latency = <300000>;
1394 cpu-idle-states = <&CPU_SLEEP>;
1395 next-level-cache = <&L2>;
1399 device_type = "cpu";
1400 compatible = "arm,cortex-a57";
1402 cpu-idle-states = <&CPU_SLEEP>;
1403 next-level-cache = <&L2>;
1407 device_type = "cpu";
1408 compatible = "arm,cortex-a57";
1410 cpu-idle-states = <&CPU_SLEEP>;
1411 next-level-cache = <&L2>;
1415 device_type = "cpu";
1416 compatible = "arm,cortex-a57";
1418 cpu-idle-states = <&CPU_SLEEP>;
1419 next-level-cache = <&L2>;
1423 entry-method = "psci";
1425 CPU_SLEEP: cpu-sleep {
1426 compatible = "arm,idle-state";
1427 arm,psci-suspend-param = <0x40000007>;
1428 entry-latency-us = <100>;
1429 exit-latency-us = <30>;
1430 min-residency-us = <1000>;
1431 wakeup-latency-us = <130>;
1432 idle-state-name = "cpu-sleep";
1433 status = "disabled";
1438 compatible = "cache";
1443 compatible = "arm,armv8-pmuv3";
1444 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
1445 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
1446 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
1447 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
1448 interrupt-affinity = <&{/cpus/cpu@0} &{/cpus/cpu@1}
1449 &{/cpus/cpu@2} &{/cpus/cpu@3}>;
1453 compatible = "arm,armv8-timer";
1454 interrupts = <GIC_PPI 13
1455 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1457 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1459 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1461 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
1462 interrupt-parent = <&gic>;
1463 arm,no-tick-in-suspend;
1466 soctherm: thermal-sensor@700e2000 {
1467 compatible = "nvidia,tegra210-soctherm";
1468 reg = <0x0 0x700e2000 0x0 0x600 /* SOC_THERM reg_base */
1469 0x0 0x60006000 0x0 0x400>; /* CAR reg_base */
1470 reg-names = "soctherm-reg", "car-reg";
1471 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
1472 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
1473 interrupt-names = "thermal", "edp";
1474 clocks = <&tegra_car TEGRA210_CLK_TSENSOR>,
1475 <&tegra_car TEGRA210_CLK_SOC_THERM>;
1476 clock-names = "tsensor", "soctherm";
1477 resets = <&tegra_car 78>;
1478 reset-names = "soctherm";
1479 #thermal-sensor-cells = <1>;
1482 throttle_heavy: heavy {
1483 nvidia,priority = <100>;
1484 nvidia,cpu-throt-percent = <85>;
1486 #cooling-cells = <2>;
1493 polling-delay-passive = <1000>;
1494 polling-delay = <0>;
1497 <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>;
1501 temperature = <102500>;
1506 cpu_throttle_trip: throttle-trip {
1507 temperature = <98500>;
1508 hysteresis = <1000>;
1515 trip = <&cpu_throttle_trip>;
1516 cooling-device = <&throttle_heavy 1 1>;
1522 polling-delay-passive = <0>;
1523 polling-delay = <0>;
1526 <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>;
1530 temperature = <103000>;
1538 * There are currently no cooling maps,
1539 * because there are no cooling devices.
1545 polling-delay-passive = <1000>;
1546 polling-delay = <0>;
1549 <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>;
1553 temperature = <103000>;
1558 gpu_throttle_trip: throttle-trip {
1559 temperature = <100000>;
1560 hysteresis = <1000>;
1567 trip = <&gpu_throttle_trip>;
1568 cooling-device = <&throttle_heavy 1 1>;
1574 polling-delay-passive = <0>;
1575 polling-delay = <0>;
1578 <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>;
1581 pllx-shutdown-trip {
1582 temperature = <103000>;
1590 * There are currently no cooling maps,
1591 * because there are no cooling devices.