2 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 #include <dt-bindings/clock/qcom,gcc-msm8916.h>
16 #include <dt-bindings/reset/qcom,gcc-msm8916.h>
17 #include <dt-bindings/clock/qcom,rpmcc.h>
18 #include <dt-bindings/thermal/thermal.h>
21 interrupt-parent = <&intc>;
27 sdhc1 = &sdhc_1; /* SDC1 eMMC slot */
28 sdhc2 = &sdhc_2; /* SDC2 SD card slot */
34 device_type = "memory";
35 /* We expect the bootloader to fill in the reg */
45 reg = <0x0 0x86000000 0x0 0x300000>;
49 smem_mem: smem_region@86300000 {
50 reg = <0x0 0x86300000 0x0 0x100000>;
55 reg = <0x0 0x86400000 0x0 0x100000>;
60 reg = <0x0 0x86500000 0x0 0x180000>;
65 reg = <0x0 0x86680000 0x0 0x80000>;
70 compatible = "qcom,rmtfs-mem";
71 reg = <0x0 0x86700000 0x0 0xe0000>;
78 reg = <0x0 0x867e0000 0x0 0x20000>;
82 mpss_mem: mpss@86800000 {
83 reg = <0x0 0x86800000 0x0 0x2b00000>;
87 wcnss_mem: wcnss@89300000 {
88 reg = <0x0 0x89300000 0x0 0x600000>;
92 venus_mem: venus@89900000 {
93 reg = <0x0 0x89900000 0x0 0x600000>;
97 mba_mem: mba@8ea00000 {
99 reg = <0 0x8ea00000 0 0x100000>;
104 #address-cells = <1>;
109 compatible = "arm,cortex-a53", "arm,armv8";
111 next-level-cache = <&L2_0>;
112 enable-method = "psci";
113 cpu-idle-states = <&CPU_SPC>;
115 operating-points-v2 = <&cpu_opp_table>;
116 #cooling-cells = <2>;
121 compatible = "arm,cortex-a53", "arm,armv8";
123 next-level-cache = <&L2_0>;
124 enable-method = "psci";
125 cpu-idle-states = <&CPU_SPC>;
127 operating-points-v2 = <&cpu_opp_table>;
128 #cooling-cells = <2>;
133 compatible = "arm,cortex-a53", "arm,armv8";
135 next-level-cache = <&L2_0>;
136 enable-method = "psci";
137 cpu-idle-states = <&CPU_SPC>;
139 operating-points-v2 = <&cpu_opp_table>;
140 #cooling-cells = <2>;
145 compatible = "arm,cortex-a53", "arm,armv8";
147 next-level-cache = <&L2_0>;
148 enable-method = "psci";
149 cpu-idle-states = <&CPU_SPC>;
151 operating-points-v2 = <&cpu_opp_table>;
152 #cooling-cells = <2>;
156 compatible = "cache";
162 compatible = "arm,idle-state";
163 arm,psci-suspend-param = <0x40000002>;
164 entry-latency-us = <130>;
165 exit-latency-us = <150>;
166 min-residency-us = <2000>;
173 compatible = "arm,psci-1.0";
178 compatible = "arm,cortex-a53-pmu";
179 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4)| IRQ_TYPE_LEVEL_HIGH)>;
184 polling-delay-passive = <250>;
185 polling-delay = <1000>;
187 thermal-sensors = <&tsens 4>;
191 temperature = <75000>;
196 temperature = <110000>;
204 trip = <&cpu_alert0>;
205 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
206 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
207 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
208 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
214 polling-delay-passive = <250>;
215 polling-delay = <1000>;
217 thermal-sensors = <&tsens 3>;
221 temperature = <75000>;
226 temperature = <110000>;
234 trip = <&cpu_alert1>;
235 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
236 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
237 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
238 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
244 polling-delay-passive = <250>;
245 polling-delay = <1000>;
247 thermal-sensors = <&tsens 2>;
251 temperature = <75000>;
256 temperature = <95000>;
264 polling-delay-passive = <250>;
265 polling-delay = <1000>;
267 thermal-sensors = <&tsens 1>;
271 temperature = <75000>;
276 temperature = <95000>;
286 cpu_opp_table: cpu_opp_table {
287 compatible = "operating-points-v2";
291 opp-hz = /bits/ 64 <200000000>;
294 opp-hz = /bits/ 64 <400000000>;
297 opp-hz = /bits/ 64 <800000000>;
300 opp-hz = /bits/ 64 <998400000>;
304 gpu_opp_table: opp_table {
305 compatible = "operating-points-v2";
308 opp-hz = /bits/ 64 <400000000>;
311 opp-hz = /bits/ 64 <19200000>;
316 compatible = "arm,armv8-timer";
317 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
318 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
319 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
320 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
325 compatible = "fixed-clock";
327 clock-frequency = <19200000>;
330 sleep_clk: sleep_clk {
331 compatible = "fixed-clock";
333 clock-frequency = <32768>;
338 compatible = "qcom,smem";
340 memory-region = <&smem_mem>;
341 qcom,rpm-msg-ram = <&rpm_msg_ram>;
343 hwlocks = <&tcsr_mutex 3>;
348 compatible = "qcom,scm";
349 clocks = <&gcc GCC_CRYPTO_CLK>, <&gcc GCC_CRYPTO_AXI_CLK>, <&gcc GCC_CRYPTO_AHB_CLK>;
350 clock-names = "core", "bus", "iface";
353 qcom,dload-mode = <&tcsr 0x6100>;
358 #address-cells = <1>;
360 ranges = <0 0 0 0xffffffff>;
361 compatible = "simple-bus";
364 compatible = "qcom,pshold";
365 reg = <0x4ab000 0x4>;
368 msmgpio: pinctrl@1000000 {
369 compatible = "qcom,msm8916-pinctrl";
370 reg = <0x1000000 0x300000>;
371 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
374 interrupt-controller;
375 #interrupt-cells = <2>;
378 gcc: clock-controller@1800000 {
379 compatible = "qcom,gcc-msm8916";
382 #power-domain-cells = <1>;
383 reg = <0x1800000 0x80000>;
386 tcsr_mutex_regs: syscon@1905000 {
387 compatible = "syscon";
388 reg = <0x1905000 0x20000>;
391 tcsr: syscon@1937000 {
392 compatible = "qcom,tcsr-msm8916", "syscon";
393 reg = <0x1937000 0x30000>;
397 compatible = "qcom,tcsr-mutex";
398 syscon = <&tcsr_mutex_regs 0 0x1000>;
402 rpm_msg_ram: memory@60000 {
403 compatible = "qcom,rpm-msg-ram";
404 reg = <0x60000 0x8000>;
407 blsp1_uart1: serial@78af000 {
408 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
409 reg = <0x78af000 0x200>;
410 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
411 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
412 clock-names = "core", "iface";
413 dmas = <&blsp_dma 1>, <&blsp_dma 0>;
414 dma-names = "rx", "tx";
418 a53pll: clock@b016000 {
419 compatible = "qcom,msm8916-a53pll";
420 reg = <0xb016000 0x40>;
424 apcs: mailbox@b011000 {
425 compatible = "qcom,msm8916-apcs-kpss-global", "syscon";
426 reg = <0xb011000 0x1000>;
432 blsp1_uart2: serial@78b0000 {
433 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
434 reg = <0x78b0000 0x200>;
435 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
436 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
437 clock-names = "core", "iface";
438 dmas = <&blsp_dma 3>, <&blsp_dma 2>;
439 dma-names = "rx", "tx";
443 blsp_dma: dma@7884000 {
444 compatible = "qcom,bam-v1.7.0";
445 reg = <0x07884000 0x23000>;
446 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
447 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
448 clock-names = "bam_clk";
454 blsp_spi1: spi@78b5000 {
455 compatible = "qcom,spi-qup-v2.2.1";
456 reg = <0x078b5000 0x500>;
457 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
458 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
459 <&gcc GCC_BLSP1_AHB_CLK>;
460 clock-names = "core", "iface";
461 dmas = <&blsp_dma 5>, <&blsp_dma 4>;
462 dma-names = "rx", "tx";
463 pinctrl-names = "default", "sleep";
464 pinctrl-0 = <&spi1_default>;
465 pinctrl-1 = <&spi1_sleep>;
466 #address-cells = <1>;
471 blsp_spi2: spi@78b6000 {
472 compatible = "qcom,spi-qup-v2.2.1";
473 reg = <0x078b6000 0x500>;
474 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
475 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
476 <&gcc GCC_BLSP1_AHB_CLK>;
477 clock-names = "core", "iface";
478 dmas = <&blsp_dma 7>, <&blsp_dma 6>;
479 dma-names = "rx", "tx";
480 pinctrl-names = "default", "sleep";
481 pinctrl-0 = <&spi2_default>;
482 pinctrl-1 = <&spi2_sleep>;
483 #address-cells = <1>;
488 blsp_spi3: spi@78b7000 {
489 compatible = "qcom,spi-qup-v2.2.1";
490 reg = <0x078b7000 0x500>;
491 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
492 clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
493 <&gcc GCC_BLSP1_AHB_CLK>;
494 clock-names = "core", "iface";
495 dmas = <&blsp_dma 9>, <&blsp_dma 8>;
496 dma-names = "rx", "tx";
497 pinctrl-names = "default", "sleep";
498 pinctrl-0 = <&spi3_default>;
499 pinctrl-1 = <&spi3_sleep>;
500 #address-cells = <1>;
505 blsp_spi4: spi@78b8000 {
506 compatible = "qcom,spi-qup-v2.2.1";
507 reg = <0x078b8000 0x500>;
508 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
509 clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
510 <&gcc GCC_BLSP1_AHB_CLK>;
511 clock-names = "core", "iface";
512 dmas = <&blsp_dma 11>, <&blsp_dma 10>;
513 dma-names = "rx", "tx";
514 pinctrl-names = "default", "sleep";
515 pinctrl-0 = <&spi4_default>;
516 pinctrl-1 = <&spi4_sleep>;
517 #address-cells = <1>;
522 blsp_spi5: spi@78b9000 {
523 compatible = "qcom,spi-qup-v2.2.1";
524 reg = <0x078b9000 0x500>;
525 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
526 clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
527 <&gcc GCC_BLSP1_AHB_CLK>;
528 clock-names = "core", "iface";
529 dmas = <&blsp_dma 13>, <&blsp_dma 12>;
530 dma-names = "rx", "tx";
531 pinctrl-names = "default", "sleep";
532 pinctrl-0 = <&spi5_default>;
533 pinctrl-1 = <&spi5_sleep>;
534 #address-cells = <1>;
539 blsp_spi6: spi@78ba000 {
540 compatible = "qcom,spi-qup-v2.2.1";
541 reg = <0x078ba000 0x500>;
542 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
543 clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>,
544 <&gcc GCC_BLSP1_AHB_CLK>;
545 clock-names = "core", "iface";
546 dmas = <&blsp_dma 15>, <&blsp_dma 14>;
547 dma-names = "rx", "tx";
548 pinctrl-names = "default", "sleep";
549 pinctrl-0 = <&spi6_default>;
550 pinctrl-1 = <&spi6_sleep>;
551 #address-cells = <1>;
556 blsp_i2c2: i2c@78b6000 {
557 compatible = "qcom,i2c-qup-v2.2.1";
558 reg = <0x078b6000 0x500>;
559 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
560 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
561 <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
562 clock-names = "iface", "core";
563 pinctrl-names = "default", "sleep";
564 pinctrl-0 = <&i2c2_default>;
565 pinctrl-1 = <&i2c2_sleep>;
566 #address-cells = <1>;
571 blsp_i2c4: i2c@78b8000 {
572 compatible = "qcom,i2c-qup-v2.2.1";
573 reg = <0x078b8000 0x500>;
574 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
575 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
576 <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
577 clock-names = "iface", "core";
578 pinctrl-names = "default", "sleep";
579 pinctrl-0 = <&i2c4_default>;
580 pinctrl-1 = <&i2c4_sleep>;
581 #address-cells = <1>;
586 blsp_i2c6: i2c@78ba000 {
587 compatible = "qcom,i2c-qup-v2.2.1";
588 reg = <0x078ba000 0x500>;
589 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
590 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
591 <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>;
592 clock-names = "iface", "core";
593 pinctrl-names = "default", "sleep";
594 pinctrl-0 = <&i2c6_default>;
595 pinctrl-1 = <&i2c6_sleep>;
596 #address-cells = <1>;
601 lpass: lpass@7708000 {
603 compatible = "qcom,lpass-cpu-apq8016";
604 clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
605 <&gcc GCC_ULTAUDIO_PCNOC_MPORT_CLK>,
606 <&gcc GCC_ULTAUDIO_PCNOC_SWAY_CLK>,
607 <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>,
608 <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>,
609 <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>,
610 <&gcc GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK>;
612 clock-names = "ahbix-clk",
619 #sound-dai-cells = <1>;
621 interrupts = <0 160 IRQ_TYPE_LEVEL_HIGH>;
622 interrupt-names = "lpass-irq-lpaif";
623 reg = <0x07708000 0x10000>;
624 reg-names = "lpass-lpaif";
628 compatible = "qcom,msm8916-wcd-digital-codec";
629 reg = <0x0771c000 0x400>;
630 clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
631 <&gcc GCC_CODEC_DIGCODEC_CLK>;
632 clock-names = "ahbix-clk", "mclk";
633 #sound-dai-cells = <1>;
636 sdhc_1: sdhci@7824000 {
637 compatible = "qcom,sdhci-msm-v4";
638 reg = <0x07824900 0x11c>, <0x07824000 0x800>;
639 reg-names = "hc_mem", "core_mem";
641 interrupts = <0 123 IRQ_TYPE_LEVEL_HIGH>, <0 138 IRQ_TYPE_LEVEL_HIGH>;
642 interrupt-names = "hc_irq", "pwr_irq";
643 clocks = <&gcc GCC_SDCC1_APPS_CLK>,
644 <&gcc GCC_SDCC1_AHB_CLK>,
646 clock-names = "core", "iface", "xo";
653 sdhc_2: sdhci@7864000 {
654 compatible = "qcom,sdhci-msm-v4";
655 reg = <0x07864900 0x11c>, <0x07864000 0x800>;
656 reg-names = "hc_mem", "core_mem";
658 interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>, <0 221 IRQ_TYPE_LEVEL_HIGH>;
659 interrupt-names = "hc_irq", "pwr_irq";
660 clocks = <&gcc GCC_SDCC2_APPS_CLK>,
661 <&gcc GCC_SDCC2_AHB_CLK>,
663 clock-names = "core", "iface", "xo";
669 compatible = "qcom,ci-hdrc";
670 reg = <0x78d9000 0x200>,
672 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
673 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
674 clocks = <&gcc GCC_USB_HS_AHB_CLK>,
675 <&gcc GCC_USB_HS_SYSTEM_CLK>;
676 clock-names = "iface", "core";
677 assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>;
678 assigned-clock-rates = <80000000>;
679 resets = <&gcc GCC_USB_HS_BCR>;
680 reset-names = "core";
683 ahb-burst-config = <0>;
684 phy-names = "usb-phy";
685 phys = <&usb_hs_phy>;
691 compatible = "qcom,usb-hs-phy-msm8916",
694 clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
695 clock-names = "ref", "sleep";
696 resets = <&gcc GCC_USB2A_PHY_BCR>, <&otg 0>;
697 reset-names = "phy", "por";
698 qcom,init-seq = /bits/ 8 <0x0 0x44
699 0x1 0x6b 0x2 0x24 0x3 0x13>;
704 intc: interrupt-controller@b000000 {
705 compatible = "qcom,msm-qgic2";
706 interrupt-controller;
707 #interrupt-cells = <3>;
708 reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
712 #address-cells = <1>;
715 compatible = "arm,armv7-timer-mem";
716 reg = <0xb020000 0x1000>;
717 clock-frequency = <19200000>;
721 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
722 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
723 reg = <0xb021000 0x1000>,
729 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
730 reg = <0xb023000 0x1000>;
736 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
737 reg = <0xb024000 0x1000>;
743 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
744 reg = <0xb025000 0x1000>;
750 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
751 reg = <0xb026000 0x1000>;
757 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
758 reg = <0xb027000 0x1000>;
764 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
765 reg = <0xb028000 0x1000>;
770 spmi_bus: spmi@200f000 {
771 compatible = "qcom,spmi-pmic-arb";
772 reg = <0x200f000 0x001000>,
773 <0x2400000 0x400000>,
774 <0x2c00000 0x400000>,
775 <0x3800000 0x200000>,
776 <0x200a000 0x002100>;
777 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
778 interrupt-names = "periph_irq";
779 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
782 #address-cells = <2>;
784 interrupt-controller;
785 #interrupt-cells = <4>;
789 compatible = "qcom,prng";
790 reg = <0x00022000 0x200>;
791 clocks = <&gcc GCC_PRNG_AHB_CLK>;
792 clock-names = "core";
795 qfprom: qfprom@5c000 {
796 compatible = "qcom,qfprom";
797 reg = <0x5c000 0x1000>;
798 #address-cells = <1>;
800 tsens_caldata: caldata@d0 {
803 tsens_calsel: calsel@ec {
808 tsens: thermal-sensor@4a9000 {
809 compatible = "qcom,msm8916-tsens";
810 reg = <0x4a9000 0x1000>, /* TM */
811 <0x4a8000 0x1000>; /* SROT */
812 nvmem-cells = <&tsens_caldata>, <&tsens_calsel>;
813 nvmem-cell-names = "calib", "calib_sel";
815 #thermal-sensor-cells = <1>;
818 apps_iommu: iommu@1ef0000 {
819 #address-cells = <1>;
822 compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
823 ranges = <0 0x1e20000 0x40000>;
824 reg = <0x1ef0000 0x3000>;
825 clocks = <&gcc GCC_SMMU_CFG_CLK>,
826 <&gcc GCC_APSS_TCU_CLK>;
827 clock-names = "iface", "bus";
828 qcom,iommu-secure-id = <17>;
832 compatible = "qcom,msm-iommu-v1-ns";
833 reg = <0x4000 0x1000>;
834 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
839 compatible = "qcom,msm-iommu-v1-sec";
840 reg = <0x5000 0x1000>;
841 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
845 gpu_iommu: iommu@1f08000 {
846 #address-cells = <1>;
849 compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
850 ranges = <0 0x1f08000 0x10000>;
851 clocks = <&gcc GCC_SMMU_CFG_CLK>,
852 <&gcc GCC_GFX_TCU_CLK>;
853 clock-names = "iface", "bus";
854 qcom,iommu-secure-id = <18>;
858 compatible = "qcom,msm-iommu-v1-ns";
859 reg = <0x1000 0x1000>;
860 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
865 compatible = "qcom,msm-iommu-v1-ns";
866 reg = <0x2000 0x1000>;
867 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
872 compatible = "qcom,adreno-306.0", "qcom,adreno";
873 reg = <0x01c00000 0x20000>;
874 reg-names = "kgsl_3d0_reg_memory";
875 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
876 interrupt-names = "kgsl_3d0_irq";
885 <&gcc GCC_OXILI_GFX3D_CLK>,
886 <&gcc GCC_OXILI_AHB_CLK>,
887 <&gcc GCC_OXILI_GMEM_CLK>,
888 <&gcc GCC_BIMC_GFX_CLK>,
889 <&gcc GCC_BIMC_GPU_CLK>,
890 <&gcc GFX3D_CLK_SRC>;
891 power-domains = <&gcc OXILI_GDSC>;
892 operating-points-v2 = <&gpu_opp_table>;
893 iommus = <&gpu_iommu 1>, <&gpu_iommu 2>;
897 compatible = "qcom,mdss";
898 reg = <0x1a00000 0x1000>,
900 reg-names = "mdss_phys", "vbif_phys";
902 power-domains = <&gcc MDSS_GDSC>;
904 clocks = <&gcc GCC_MDSS_AHB_CLK>,
905 <&gcc GCC_MDSS_AXI_CLK>,
906 <&gcc GCC_MDSS_VSYNC_CLK>;
907 clock-names = "iface",
911 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>;
913 interrupt-controller;
914 #interrupt-cells = <1>;
916 #address-cells = <1>;
921 compatible = "qcom,mdp5";
922 reg = <0x1a01000 0x89000>;
923 reg-names = "mdp_phys";
925 interrupt-parent = <&mdss>;
928 clocks = <&gcc GCC_MDSS_AHB_CLK>,
929 <&gcc GCC_MDSS_AXI_CLK>,
930 <&gcc GCC_MDSS_MDP_CLK>,
931 <&gcc GCC_MDSS_VSYNC_CLK>;
932 clock-names = "iface",
937 iommus = <&apps_iommu 4>;
940 #address-cells = <1>;
945 mdp5_intf1_out: endpoint {
946 remote-endpoint = <&dsi0_in>;
953 compatible = "qcom,mdss-dsi-ctrl";
954 reg = <0x1a98000 0x25c>;
955 reg-names = "dsi_ctrl";
957 interrupt-parent = <&mdss>;
960 assigned-clocks = <&gcc BYTE0_CLK_SRC>,
961 <&gcc PCLK0_CLK_SRC>;
962 assigned-clock-parents = <&dsi_phy0 0>,
965 clocks = <&gcc GCC_MDSS_MDP_CLK>,
966 <&gcc GCC_MDSS_AHB_CLK>,
967 <&gcc GCC_MDSS_AXI_CLK>,
968 <&gcc GCC_MDSS_BYTE0_CLK>,
969 <&gcc GCC_MDSS_PCLK0_CLK>,
970 <&gcc GCC_MDSS_ESC0_CLK>;
971 clock-names = "mdp_core",
978 phy-names = "dsi-phy";
981 #address-cells = <1>;
987 remote-endpoint = <&mdp5_intf1_out>;
999 dsi_phy0: dsi-phy@1a98300 {
1000 compatible = "qcom,dsi-phy-28nm-lp";
1001 reg = <0x1a98300 0xd4>,
1004 reg-names = "dsi_pll",
1006 "dsi_phy_regulator";
1011 clocks = <&gcc GCC_MDSS_AHB_CLK>;
1012 clock-names = "iface";
1018 compatible = "qcom,q6v5-pil";
1019 reg = <0x04080000 0x100>,
1022 reg-names = "qdsp6", "rmb";
1024 interrupts-extended = <&intc 0 24 1>,
1025 <&hexagon_smp2p_in 0 0>,
1026 <&hexagon_smp2p_in 1 0>,
1027 <&hexagon_smp2p_in 2 0>,
1028 <&hexagon_smp2p_in 3 0>;
1029 interrupt-names = "wdog", "fatal", "ready",
1030 "handover", "stop-ack";
1032 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
1033 <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>,
1034 <&gcc GCC_BOOT_ROM_AHB_CLK>,
1036 clock-names = "iface", "bus", "mem", "xo";
1038 qcom,smem-states = <&hexagon_smp2p_out 0>;
1039 qcom,smem-state-names = "stop";
1042 reset-names = "mss_restart";
1044 cx-supply = <&pm8916_s1>;
1045 mx-supply = <&pm8916_l3>;
1046 pll-supply = <&pm8916_l7>;
1048 qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>;
1050 status = "disabled";
1053 memory-region = <&mba_mem>;
1057 memory-region = <&mpss_mem>;
1061 interrupts = <0 25 IRQ_TYPE_EDGE_RISING>;
1063 qcom,smd-edge = <0>;
1064 qcom,ipc = <&apcs 8 12>;
1065 qcom,remote-pid = <1>;
1071 pronto: wcnss@a21b000 {
1072 compatible = "qcom,pronto-v2-pil", "qcom,pronto";
1073 reg = <0x0a204000 0x2000>, <0x0a202000 0x1000>, <0x0a21b000 0x3000>;
1074 reg-names = "ccu", "dxe", "pmu";
1076 memory-region = <&wcnss_mem>;
1078 interrupts-extended = <&intc 0 149 IRQ_TYPE_EDGE_RISING>,
1079 <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1080 <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1081 <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1082 <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1083 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
1085 vddmx-supply = <&pm8916_l3>;
1086 vddpx-supply = <&pm8916_l7>;
1088 qcom,state = <&wcnss_smp2p_out 0>;
1089 qcom,state-names = "stop";
1091 pinctrl-names = "default";
1092 pinctrl-0 = <&wcnss_pin_a>;
1094 status = "disabled";
1097 compatible = "qcom,wcn3620";
1099 clocks = <&rpmcc RPM_SMD_RF_CLK2>;
1102 vddxo-supply = <&pm8916_l7>;
1103 vddrfa-supply = <&pm8916_s3>;
1104 vddpa-supply = <&pm8916_l9>;
1105 vdddig-supply = <&pm8916_l5>;
1109 interrupts = <0 142 1>;
1111 qcom,ipc = <&apcs 8 17>;
1112 qcom,smd-edge = <6>;
1113 qcom,remote-pid = <4>;
1118 compatible = "qcom,wcnss";
1119 qcom,smd-channels = "WCNSS_CTRL";
1121 qcom,mmio = <&pronto>;
1124 compatible = "qcom,wcnss-bt";
1128 compatible = "qcom,wcnss-wlan";
1130 interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>,
1131 <0 146 IRQ_TYPE_LEVEL_HIGH>;
1132 interrupt-names = "tx", "rx";
1134 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>;
1135 qcom,smem-state-names = "tx-enable", "tx-rings-empty";
1142 compatible = "arm,coresight-tpiu", "arm,primecell";
1143 reg = <0x820000 0x1000>;
1145 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1146 clock-names = "apb_pclk", "atclk";
1151 remote-endpoint = <&replicator_out1>;
1158 compatible = "arm,coresight-funnel", "arm,primecell";
1159 reg = <0x821000 0x1000>;
1161 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1162 clock-names = "apb_pclk", "atclk";
1165 #address-cells = <1>;
1169 * Not described input ports:
1170 * 0 - connected to Resource and Power Manger CPU ETM
1172 * 2 - connected to Modem CPU ETM
1175 * 6 - connected trought funnel to Wireless CPU ETM
1176 * 7 - connected to STM component
1181 funnel0_in4: endpoint {
1182 remote-endpoint = <&funnel1_out>;
1189 funnel0_out: endpoint {
1190 remote-endpoint = <&etf_in>;
1197 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
1198 reg = <0x824000 0x1000>;
1200 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1201 clock-names = "apb_pclk", "atclk";
1204 #address-cells = <1>;
1209 replicator_out0: endpoint {
1210 remote-endpoint = <&etr_in>;
1215 replicator_out1: endpoint {
1216 remote-endpoint = <&tpiu_in>;
1223 replicator_in: endpoint {
1224 remote-endpoint = <&etf_out>;
1231 compatible = "arm,coresight-tmc", "arm,primecell";
1232 reg = <0x825000 0x1000>;
1234 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1235 clock-names = "apb_pclk", "atclk";
1240 remote-endpoint = <&funnel0_out>;
1248 remote-endpoint = <&replicator_in>;
1255 compatible = "arm,coresight-tmc", "arm,primecell";
1256 reg = <0x826000 0x1000>;
1258 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1259 clock-names = "apb_pclk", "atclk";
1264 remote-endpoint = <&replicator_out0>;
1270 funnel@841000 { /* APSS funnel only 4 inputs are used */
1271 compatible = "arm,coresight-funnel", "arm,primecell";
1272 reg = <0x841000 0x1000>;
1274 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1275 clock-names = "apb_pclk", "atclk";
1278 #address-cells = <1>;
1283 funnel1_in0: endpoint {
1284 remote-endpoint = <&etm0_out>;
1289 funnel1_in1: endpoint {
1290 remote-endpoint = <&etm1_out>;
1295 funnel1_in2: endpoint {
1296 remote-endpoint = <&etm2_out>;
1301 funnel1_in3: endpoint {
1302 remote-endpoint = <&etm3_out>;
1309 funnel1_out: endpoint {
1310 remote-endpoint = <&funnel0_in4>;
1317 compatible = "arm,coresight-cpu-debug","arm,primecell";
1318 reg = <0x850000 0x1000>;
1319 clocks = <&rpmcc RPM_QDSS_CLK>;
1320 clock-names = "apb_pclk";
1325 compatible = "arm,coresight-cpu-debug","arm,primecell";
1326 reg = <0x852000 0x1000>;
1327 clocks = <&rpmcc RPM_QDSS_CLK>;
1328 clock-names = "apb_pclk";
1333 compatible = "arm,coresight-cpu-debug","arm,primecell";
1334 reg = <0x854000 0x1000>;
1335 clocks = <&rpmcc RPM_QDSS_CLK>;
1336 clock-names = "apb_pclk";
1341 compatible = "arm,coresight-cpu-debug","arm,primecell";
1342 reg = <0x856000 0x1000>;
1343 clocks = <&rpmcc RPM_QDSS_CLK>;
1344 clock-names = "apb_pclk";
1349 compatible = "arm,coresight-etm4x", "arm,primecell";
1350 reg = <0x85c000 0x1000>;
1352 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1353 clock-names = "apb_pclk", "atclk";
1359 etm0_out: endpoint {
1360 remote-endpoint = <&funnel1_in0>;
1367 compatible = "arm,coresight-etm4x", "arm,primecell";
1368 reg = <0x85d000 0x1000>;
1370 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1371 clock-names = "apb_pclk", "atclk";
1377 etm1_out: endpoint {
1378 remote-endpoint = <&funnel1_in1>;
1385 compatible = "arm,coresight-etm4x", "arm,primecell";
1386 reg = <0x85e000 0x1000>;
1388 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1389 clock-names = "apb_pclk", "atclk";
1395 etm2_out: endpoint {
1396 remote-endpoint = <&funnel1_in2>;
1403 compatible = "arm,coresight-etm4x", "arm,primecell";
1404 reg = <0x85f000 0x1000>;
1406 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1407 clock-names = "apb_pclk", "atclk";
1413 etm3_out: endpoint {
1414 remote-endpoint = <&funnel1_in3>;
1420 venus: video-codec@1d00000 {
1421 compatible = "qcom,msm8916-venus";
1422 reg = <0x01d00000 0xff000>;
1423 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
1424 power-domains = <&gcc VENUS_GDSC>;
1425 clocks = <&gcc GCC_VENUS0_VCODEC0_CLK>,
1426 <&gcc GCC_VENUS0_AHB_CLK>,
1427 <&gcc GCC_VENUS0_AXI_CLK>;
1428 clock-names = "core", "iface", "bus";
1429 iommus = <&apps_iommu 5>;
1430 memory-region = <&venus_mem>;
1434 compatible = "venus-decoder";
1438 compatible = "venus-encoder";
1444 compatible = "qcom,smd";
1447 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
1448 qcom,ipc = <&apcs 8 0>;
1449 qcom,smd-edge = <15>;
1452 compatible = "qcom,rpm-msm8916";
1453 qcom,smd-channels = "rpm_requests";
1456 compatible = "qcom,rpmcc-msm8916";
1460 smd_rpm_regulators: pm8916-regulators {
1461 compatible = "qcom,rpm-pm8916-regulators";
1491 compatible = "qcom,smp2p";
1492 qcom,smem = <435>, <428>;
1494 interrupts = <0 27 IRQ_TYPE_EDGE_RISING>;
1496 qcom,ipc = <&apcs 8 14>;
1498 qcom,local-pid = <0>;
1499 qcom,remote-pid = <1>;
1501 hexagon_smp2p_out: master-kernel {
1502 qcom,entry-name = "master-kernel";
1504 #qcom,smem-state-cells = <1>;
1507 hexagon_smp2p_in: slave-kernel {
1508 qcom,entry-name = "slave-kernel";
1510 interrupt-controller;
1511 #interrupt-cells = <2>;
1516 compatible = "qcom,smp2p";
1517 qcom,smem = <451>, <431>;
1519 interrupts = <0 143 IRQ_TYPE_EDGE_RISING>;
1521 qcom,ipc = <&apcs 8 18>;
1523 qcom,local-pid = <0>;
1524 qcom,remote-pid = <4>;
1526 wcnss_smp2p_out: master-kernel {
1527 qcom,entry-name = "master-kernel";
1529 #qcom,smem-state-cells = <1>;
1532 wcnss_smp2p_in: slave-kernel {
1533 qcom,entry-name = "slave-kernel";
1535 interrupt-controller;
1536 #interrupt-cells = <2>;
1541 compatible = "qcom,smsm";
1543 #address-cells = <1>;
1546 qcom,ipc-1 = <&apcs 8 13>;
1547 qcom,ipc-3 = <&apcs 8 19>;
1552 #qcom,smem-state-cells = <1>;
1555 hexagon_smsm: hexagon@1 {
1557 interrupts = <0 26 IRQ_TYPE_EDGE_RISING>;
1559 interrupt-controller;
1560 #interrupt-cells = <2>;
1563 wcnss_smsm: wcnss@6 {
1565 interrupts = <0 144 IRQ_TYPE_EDGE_RISING>;
1567 interrupt-controller;
1568 #interrupt-cells = <2>;
1573 #include "msm8916-pins.dtsi"