2 * Copyright (C) 2014 ARM Limited
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
10 #include <linux/init.h>
11 #include <linux/list.h>
12 #include <linux/perf_event.h>
13 #include <linux/sched.h>
14 #include <linux/slab.h>
15 #include <linux/sysctl.h>
17 #include <asm/cpufeature.h>
19 #include <asm/sysreg.h>
20 #include <asm/system_misc.h>
21 #include <asm/traps.h>
22 #include <linux/uaccess.h>
23 #include <asm/cpufeature.h>
25 #define CREATE_TRACE_POINTS
26 #include "trace-events-emulation.h"
29 * The runtime support for deprecated instruction support can be in one of
30 * following three states -
33 * 1 = emulate (software emulation)
34 * 2 = hw (supported in hardware)
36 enum insn_emulation_mode {
42 enum legacy_insn_status {
47 struct insn_emulation_ops {
49 enum legacy_insn_status status;
50 struct undef_hook *hooks;
51 int (*set_hw_mode)(bool enable);
54 struct insn_emulation {
55 struct list_head node;
56 struct insn_emulation_ops *ops;
62 static LIST_HEAD(insn_emulation);
63 static int nr_insn_emulated __initdata;
64 static DEFINE_RAW_SPINLOCK(insn_emulation_lock);
66 static void register_emulation_hooks(struct insn_emulation_ops *ops)
68 struct undef_hook *hook;
72 for (hook = ops->hooks; hook->instr_mask; hook++)
73 register_undef_hook(hook);
75 pr_notice("Registered %s emulation handler\n", ops->name);
78 static void remove_emulation_hooks(struct insn_emulation_ops *ops)
80 struct undef_hook *hook;
84 for (hook = ops->hooks; hook->instr_mask; hook++)
85 unregister_undef_hook(hook);
87 pr_notice("Removed %s emulation handler\n", ops->name);
90 static void enable_insn_hw_mode(void *data)
92 struct insn_emulation *insn = (struct insn_emulation *)data;
93 if (insn->ops->set_hw_mode)
94 insn->ops->set_hw_mode(true);
97 static void disable_insn_hw_mode(void *data)
99 struct insn_emulation *insn = (struct insn_emulation *)data;
100 if (insn->ops->set_hw_mode)
101 insn->ops->set_hw_mode(false);
104 /* Run set_hw_mode(mode) on all active CPUs */
105 static int run_all_cpu_set_hw_mode(struct insn_emulation *insn, bool enable)
107 if (!insn->ops->set_hw_mode)
110 on_each_cpu(enable_insn_hw_mode, (void *)insn, true);
112 on_each_cpu(disable_insn_hw_mode, (void *)insn, true);
117 * Run set_hw_mode for all insns on a starting CPU.
119 * 0 - If all the hooks ran successfully.
120 * -EINVAL - At least one hook is not supported by the CPU.
122 static int run_all_insn_set_hw_mode(unsigned int cpu)
126 struct insn_emulation *insn;
128 raw_spin_lock_irqsave(&insn_emulation_lock, flags);
129 list_for_each_entry(insn, &insn_emulation, node) {
130 bool enable = (insn->current_mode == INSN_HW);
131 if (insn->ops->set_hw_mode && insn->ops->set_hw_mode(enable)) {
132 pr_warn("CPU[%u] cannot support the emulation of %s",
133 cpu, insn->ops->name);
137 raw_spin_unlock_irqrestore(&insn_emulation_lock, flags);
141 static int update_insn_emulation_mode(struct insn_emulation *insn,
142 enum insn_emulation_mode prev)
147 case INSN_UNDEF: /* Nothing to be done */
150 remove_emulation_hooks(insn->ops);
153 if (!run_all_cpu_set_hw_mode(insn, false))
154 pr_notice("Disabled %s support\n", insn->ops->name);
158 switch (insn->current_mode) {
162 register_emulation_hooks(insn->ops);
165 ret = run_all_cpu_set_hw_mode(insn, true);
167 pr_notice("Enabled %s support\n", insn->ops->name);
174 static void __init register_insn_emulation(struct insn_emulation_ops *ops)
177 struct insn_emulation *insn;
179 insn = kzalloc(sizeof(*insn), GFP_KERNEL);
181 insn->min = INSN_UNDEF;
183 switch (ops->status) {
184 case INSN_DEPRECATED:
185 insn->current_mode = INSN_EMULATE;
186 /* Disable the HW mode if it was turned on at early boot time */
187 run_all_cpu_set_hw_mode(insn, false);
191 insn->current_mode = INSN_UNDEF;
192 insn->max = INSN_EMULATE;
196 raw_spin_lock_irqsave(&insn_emulation_lock, flags);
197 list_add(&insn->node, &insn_emulation);
199 raw_spin_unlock_irqrestore(&insn_emulation_lock, flags);
201 /* Register any handlers if required */
202 update_insn_emulation_mode(insn, INSN_UNDEF);
205 static int emulation_proc_handler(struct ctl_table *table, int write,
206 void __user *buffer, size_t *lenp,
210 struct insn_emulation *insn = (struct insn_emulation *) table->data;
211 enum insn_emulation_mode prev_mode = insn->current_mode;
213 table->data = &insn->current_mode;
214 ret = proc_dointvec_minmax(table, write, buffer, lenp, ppos);
216 if (ret || !write || prev_mode == insn->current_mode)
219 ret = update_insn_emulation_mode(insn, prev_mode);
221 /* Mode change failed, revert to previous mode. */
222 insn->current_mode = prev_mode;
223 update_insn_emulation_mode(insn, INSN_UNDEF);
230 static struct ctl_table ctl_abi[] = {
238 static void __init register_insn_emulation_sysctl(struct ctl_table *table)
242 struct insn_emulation *insn;
243 struct ctl_table *insns_sysctl, *sysctl;
245 insns_sysctl = kzalloc(sizeof(*sysctl) * (nr_insn_emulated + 1),
248 raw_spin_lock_irqsave(&insn_emulation_lock, flags);
249 list_for_each_entry(insn, &insn_emulation, node) {
250 sysctl = &insns_sysctl[i];
253 sysctl->maxlen = sizeof(int);
255 sysctl->procname = insn->ops->name;
257 sysctl->extra1 = &insn->min;
258 sysctl->extra2 = &insn->max;
259 sysctl->proc_handler = emulation_proc_handler;
262 raw_spin_unlock_irqrestore(&insn_emulation_lock, flags);
264 table->child = insns_sysctl;
265 register_sysctl_table(table);
269 * Implement emulation of the SWP/SWPB instructions using load-exclusive and
272 * Syntax of SWP{B} instruction: SWP{B}<c> <Rt>, <Rt2>, [<Rn>]
273 * Where: Rt = destination
279 * Error-checking SWP macros implemented using ldxr{b}/stxr{b}
282 /* Arbitrary constant to ensure forward-progress of the LL/SC loop */
283 #define __SWP_LL_SC_LOOPS 4
285 #define __user_swpX_asm(data, addr, res, temp, temp2, B) \
288 __asm__ __volatile__( \
290 "0: ldxr"B" %w2, [%4]\n" \
291 "1: stxr"B" %w0, %w1, [%4]\n" \
293 " sub %w3, %w3, #1\n" \
300 " .pushsection .fixup,\"ax\"\n" \
302 "4: mov %w0, %w6\n" \
305 _ASM_EXTABLE(0b, 4b) \
306 _ASM_EXTABLE(1b, 4b) \
307 : "=&r" (res), "+r" (data), "=&r" (temp), "=&r" (temp2) \
308 : "r" (addr), "i" (-EAGAIN), "i" (-EFAULT), \
309 "i" (__SWP_LL_SC_LOOPS) \
314 #define __user_swp_asm(data, addr, res, temp, temp2) \
315 __user_swpX_asm(data, addr, res, temp, temp2, "")
316 #define __user_swpb_asm(data, addr, res, temp, temp2) \
317 __user_swpX_asm(data, addr, res, temp, temp2, "b")
320 * Bit 22 of the instruction encoding distinguishes between
321 * the SWP and SWPB variants (bit set means SWPB).
323 #define TYPE_SWPB (1 << 22)
325 static int emulate_swpX(unsigned int address, unsigned int *data,
328 unsigned int res = 0;
330 if ((type != TYPE_SWPB) && (address & 0x3)) {
331 /* SWP to unaligned address not permitted */
332 pr_debug("SWP instruction on unaligned pointer!\n");
337 unsigned long temp, temp2;
339 if (type == TYPE_SWPB)
340 __user_swpb_asm(*data, address, res, temp, temp2);
342 __user_swp_asm(*data, address, res, temp, temp2);
344 if (likely(res != -EAGAIN) || signal_pending(current))
353 #define ARM_OPCODE_CONDTEST_FAIL 0
354 #define ARM_OPCODE_CONDTEST_PASS 1
355 #define ARM_OPCODE_CONDTEST_UNCOND 2
357 #define ARM_OPCODE_CONDITION_UNCOND 0xf
359 static unsigned int __kprobes aarch32_check_condition(u32 opcode, u32 psr)
361 u32 cc_bits = opcode >> 28;
363 if (cc_bits != ARM_OPCODE_CONDITION_UNCOND) {
364 if ((*aarch32_opcode_cond_checks[cc_bits])(psr))
365 return ARM_OPCODE_CONDTEST_PASS;
367 return ARM_OPCODE_CONDTEST_FAIL;
369 return ARM_OPCODE_CONDTEST_UNCOND;
373 * swp_handler logs the id of calling process, dissects the instruction, sanity
374 * checks the memory location, calls emulate_swpX for the actual operation and
375 * deals with fixup/error handling before returning
377 static int swp_handler(struct pt_regs *regs, u32 instr)
379 u32 destreg, data, type, address = 0;
380 int rn, rt2, res = 0;
382 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, regs->pc);
384 type = instr & TYPE_SWPB;
386 switch (aarch32_check_condition(instr, regs->pstate)) {
387 case ARM_OPCODE_CONDTEST_PASS:
389 case ARM_OPCODE_CONDTEST_FAIL:
390 /* Condition failed - return to next instruction */
392 case ARM_OPCODE_CONDTEST_UNCOND:
393 /* If unconditional encoding - not a SWP, undef */
399 rn = aarch32_insn_extract_reg_num(instr, A32_RN_OFFSET);
400 rt2 = aarch32_insn_extract_reg_num(instr, A32_RT2_OFFSET);
402 address = (u32)regs->user_regs.regs[rn];
403 data = (u32)regs->user_regs.regs[rt2];
404 destreg = aarch32_insn_extract_reg_num(instr, A32_RT_OFFSET);
406 pr_debug("addr in r%d->0x%08x, dest is r%d, source in r%d->0x%08x)\n",
407 rn, address, destreg,
408 aarch32_insn_extract_reg_num(instr, A32_RT2_OFFSET), data);
410 /* Check access in reasonable access range for both SWP and SWPB */
411 if (!access_ok(VERIFY_WRITE, (address & ~3), 4)) {
412 pr_debug("SWP{B} emulation: access to 0x%08x not allowed!\n",
417 res = emulate_swpX(address, &data, type);
421 regs->user_regs.regs[destreg] = data;
424 if (type == TYPE_SWPB)
425 trace_instruction_emulation("swpb", regs->pc);
427 trace_instruction_emulation("swp", regs->pc);
429 pr_warn_ratelimited("\"%s\" (%ld) uses obsolete SWP{B} instruction at 0x%llx\n",
430 current->comm, (unsigned long)current->pid, regs->pc);
436 pr_debug("SWP{B} emulation: access caused memory abort!\n");
437 arm64_notify_segfault(regs, address);
443 * Only emulate SWP/SWPB executed in ARM state/User mode.
444 * The kernel must be SWP free and SWP{B} does not exist in Thumb.
446 static struct undef_hook swp_hooks[] = {
448 .instr_mask = 0x0fb00ff0,
449 .instr_val = 0x01000090,
450 .pstate_mask = COMPAT_PSR_MODE_MASK,
451 .pstate_val = COMPAT_PSR_MODE_USR,
457 static struct insn_emulation_ops swp_ops = {
459 .status = INSN_OBSOLETE,
464 static int cp15barrier_handler(struct pt_regs *regs, u32 instr)
466 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, regs->pc);
468 switch (aarch32_check_condition(instr, regs->pstate)) {
469 case ARM_OPCODE_CONDTEST_PASS:
471 case ARM_OPCODE_CONDTEST_FAIL:
472 /* Condition failed - return to next instruction */
474 case ARM_OPCODE_CONDTEST_UNCOND:
475 /* If unconditional encoding - not a barrier instruction */
481 switch (aarch32_insn_mcr_extract_crm(instr)) {
484 * dmb - mcr p15, 0, Rt, c7, c10, 5
485 * dsb - mcr p15, 0, Rt, c7, c10, 4
487 if (aarch32_insn_mcr_extract_opc2(instr) == 5) {
489 trace_instruction_emulation(
490 "mcr p15, 0, Rt, c7, c10, 5 ; dmb", regs->pc);
493 trace_instruction_emulation(
494 "mcr p15, 0, Rt, c7, c10, 4 ; dsb", regs->pc);
499 * isb - mcr p15, 0, Rt, c7, c5, 4
501 * Taking an exception or returning from one acts as an
502 * instruction barrier. So no explicit barrier needed here.
504 trace_instruction_emulation(
505 "mcr p15, 0, Rt, c7, c5, 4 ; isb", regs->pc);
510 pr_warn_ratelimited("\"%s\" (%ld) uses deprecated CP15 Barrier instruction at 0x%llx\n",
511 current->comm, (unsigned long)current->pid, regs->pc);
517 static int cp15_barrier_set_hw_mode(bool enable)
520 config_sctlr_el1(0, SCTLR_EL1_CP15BEN);
522 config_sctlr_el1(SCTLR_EL1_CP15BEN, 0);
526 static struct undef_hook cp15_barrier_hooks[] = {
528 .instr_mask = 0x0fff0fdf,
529 .instr_val = 0x0e070f9a,
530 .pstate_mask = COMPAT_PSR_MODE_MASK,
531 .pstate_val = COMPAT_PSR_MODE_USR,
532 .fn = cp15barrier_handler,
535 .instr_mask = 0x0fff0fff,
536 .instr_val = 0x0e070f95,
537 .pstate_mask = COMPAT_PSR_MODE_MASK,
538 .pstate_val = COMPAT_PSR_MODE_USR,
539 .fn = cp15barrier_handler,
544 static struct insn_emulation_ops cp15_barrier_ops = {
545 .name = "cp15_barrier",
546 .status = INSN_DEPRECATED,
547 .hooks = cp15_barrier_hooks,
548 .set_hw_mode = cp15_barrier_set_hw_mode,
551 static int setend_set_hw_mode(bool enable)
553 if (!cpu_supports_mixed_endian_el0())
557 config_sctlr_el1(SCTLR_EL1_SED, 0);
559 config_sctlr_el1(0, SCTLR_EL1_SED);
563 static int compat_setend_handler(struct pt_regs *regs, u32 big_endian)
567 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, regs->pc);
571 regs->pstate |= COMPAT_PSR_E_BIT;
574 regs->pstate &= ~COMPAT_PSR_E_BIT;
577 trace_instruction_emulation(insn, regs->pc);
578 pr_warn_ratelimited("\"%s\" (%ld) uses deprecated setend instruction at 0x%llx\n",
579 current->comm, (unsigned long)current->pid, regs->pc);
584 static int a32_setend_handler(struct pt_regs *regs, u32 instr)
586 int rc = compat_setend_handler(regs, (instr >> 9) & 1);
591 static int t16_setend_handler(struct pt_regs *regs, u32 instr)
593 int rc = compat_setend_handler(regs, (instr >> 3) & 1);
598 static struct undef_hook setend_hooks[] = {
600 .instr_mask = 0xfffffdff,
601 .instr_val = 0xf1010000,
602 .pstate_mask = COMPAT_PSR_MODE_MASK,
603 .pstate_val = COMPAT_PSR_MODE_USR,
604 .fn = a32_setend_handler,
608 .instr_mask = 0x0000fff7,
609 .instr_val = 0x0000b650,
610 .pstate_mask = (COMPAT_PSR_T_BIT | COMPAT_PSR_MODE_MASK),
611 .pstate_val = (COMPAT_PSR_T_BIT | COMPAT_PSR_MODE_USR),
612 .fn = t16_setend_handler,
617 static struct insn_emulation_ops setend_ops = {
619 .status = INSN_DEPRECATED,
620 .hooks = setend_hooks,
621 .set_hw_mode = setend_set_hw_mode,
625 * Invoked as late_initcall, since not needed before init spawned.
627 static int __init armv8_deprecated_init(void)
629 if (IS_ENABLED(CONFIG_SWP_EMULATION))
630 register_insn_emulation(&swp_ops);
632 if (IS_ENABLED(CONFIG_CP15_BARRIER_EMULATION))
633 register_insn_emulation(&cp15_barrier_ops);
635 if (IS_ENABLED(CONFIG_SETEND_EMULATION)) {
636 if(system_supports_mixed_endian_el0())
637 register_insn_emulation(&setend_ops);
639 pr_info("setend instruction emulation is not supported on the system");
642 cpuhp_setup_state_nocalls(CPUHP_AP_ARM64_ISNDEP_STARTING,
643 "arm64/isndep:starting",
644 run_all_insn_set_hw_mode, NULL);
645 register_insn_emulation_sysctl(ctl_abi);
650 late_initcall(armv8_deprecated_init);