2 * Contains CPU specific errata definitions
4 * Copyright (C) 2014 ARM Ltd.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
19 #include <linux/arm-smccc.h>
20 #include <linux/psci.h>
21 #include <linux/types.h>
23 #include <asm/cputype.h>
24 #include <asm/cpufeature.h>
26 static bool __maybe_unused
27 is_affected_midr_range(const struct arm64_cpu_capabilities *entry, int scope)
29 const struct arm64_midr_revidr *fix;
30 u32 midr = read_cpuid_id(), revidr;
32 WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
33 if (!is_midr_in_range(midr, &entry->midr_range))
36 midr &= MIDR_REVISION_MASK | MIDR_VARIANT_MASK;
37 revidr = read_cpuid(REVIDR_EL1);
38 for (fix = entry->fixed_revs; fix && fix->revidr_mask; fix++)
39 if (midr == fix->midr_rv && (revidr & fix->revidr_mask))
45 static bool __maybe_unused
46 is_affected_midr_range_list(const struct arm64_cpu_capabilities *entry,
49 WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
50 return is_midr_in_range_list(read_cpuid_id(), entry->midr_range_list);
53 static bool __maybe_unused
54 is_kryo_midr(const struct arm64_cpu_capabilities *entry, int scope)
58 WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
60 model = read_cpuid_id();
61 model &= MIDR_IMPLEMENTOR_MASK | (0xf00 << MIDR_PARTNUM_SHIFT) |
62 MIDR_ARCHITECTURE_MASK;
64 return model == entry->midr_range.model;
68 has_mismatched_cache_type(const struct arm64_cpu_capabilities *entry,
71 u64 mask = CTR_CACHE_MINLINE_MASK;
73 /* Skip matching the min line sizes for cache type check */
74 if (entry->capability == ARM64_MISMATCHED_CACHE_TYPE)
75 mask ^= arm64_ftr_reg_ctrel0.strict_mask;
77 WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
78 return (read_cpuid_cachetype() & mask) !=
79 (arm64_ftr_reg_ctrel0.sys_val & mask);
83 cpu_enable_trap_ctr_access(const struct arm64_cpu_capabilities *__unused)
85 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0);
88 atomic_t arm64_el2_vector_last_slot = ATOMIC_INIT(-1);
90 #ifdef CONFIG_HARDEN_BRANCH_PREDICTOR
91 #include <asm/mmu_context.h>
92 #include <asm/cacheflush.h>
94 DEFINE_PER_CPU_READ_MOSTLY(struct bp_hardening_data, bp_hardening_data);
96 #ifdef CONFIG_KVM_INDIRECT_VECTORS
97 extern char __smccc_workaround_1_smc_start[];
98 extern char __smccc_workaround_1_smc_end[];
100 static void __copy_hyp_vect_bpi(int slot, const char *hyp_vecs_start,
101 const char *hyp_vecs_end)
103 void *dst = lm_alias(__bp_harden_hyp_vecs_start + slot * SZ_2K);
106 for (i = 0; i < SZ_2K; i += 0x80)
107 memcpy(dst + i, hyp_vecs_start, hyp_vecs_end - hyp_vecs_start);
109 __flush_icache_range((uintptr_t)dst, (uintptr_t)dst + SZ_2K);
112 static void __install_bp_hardening_cb(bp_hardening_cb_t fn,
113 const char *hyp_vecs_start,
114 const char *hyp_vecs_end)
116 static DEFINE_SPINLOCK(bp_lock);
120 for_each_possible_cpu(cpu) {
121 if (per_cpu(bp_hardening_data.fn, cpu) == fn) {
122 slot = per_cpu(bp_hardening_data.hyp_vectors_slot, cpu);
128 slot = atomic_inc_return(&arm64_el2_vector_last_slot);
129 BUG_ON(slot >= BP_HARDEN_EL2_SLOTS);
130 __copy_hyp_vect_bpi(slot, hyp_vecs_start, hyp_vecs_end);
133 __this_cpu_write(bp_hardening_data.hyp_vectors_slot, slot);
134 __this_cpu_write(bp_hardening_data.fn, fn);
135 spin_unlock(&bp_lock);
138 #define __smccc_workaround_1_smc_start NULL
139 #define __smccc_workaround_1_smc_end NULL
141 static void __install_bp_hardening_cb(bp_hardening_cb_t fn,
142 const char *hyp_vecs_start,
143 const char *hyp_vecs_end)
145 __this_cpu_write(bp_hardening_data.fn, fn);
147 #endif /* CONFIG_KVM_INDIRECT_VECTORS */
149 static void install_bp_hardening_cb(const struct arm64_cpu_capabilities *entry,
150 bp_hardening_cb_t fn,
151 const char *hyp_vecs_start,
152 const char *hyp_vecs_end)
156 if (!entry->matches(entry, SCOPE_LOCAL_CPU))
159 pfr0 = read_cpuid(ID_AA64PFR0_EL1);
160 if (cpuid_feature_extract_unsigned_field(pfr0, ID_AA64PFR0_CSV2_SHIFT))
163 __install_bp_hardening_cb(fn, hyp_vecs_start, hyp_vecs_end);
166 #include <uapi/linux/psci.h>
167 #include <linux/arm-smccc.h>
168 #include <linux/psci.h>
170 static void call_smc_arch_workaround_1(void)
172 arm_smccc_1_1_smc(ARM_SMCCC_ARCH_WORKAROUND_1, NULL);
175 static void call_hvc_arch_workaround_1(void)
177 arm_smccc_1_1_hvc(ARM_SMCCC_ARCH_WORKAROUND_1, NULL);
180 static void qcom_link_stack_sanitization(void)
184 asm volatile("mov %0, x30 \n"
193 enable_smccc_arch_workaround_1(const struct arm64_cpu_capabilities *entry)
195 bp_hardening_cb_t cb;
196 void *smccc_start, *smccc_end;
197 struct arm_smccc_res res;
198 u32 midr = read_cpuid_id();
200 if (!entry->matches(entry, SCOPE_LOCAL_CPU))
203 if (psci_ops.smccc_version == SMCCC_VERSION_1_0)
206 switch (psci_ops.conduit) {
207 case PSCI_CONDUIT_HVC:
208 arm_smccc_1_1_hvc(ARM_SMCCC_ARCH_FEATURES_FUNC_ID,
209 ARM_SMCCC_ARCH_WORKAROUND_1, &res);
212 cb = call_hvc_arch_workaround_1;
213 /* This is a guest, no need to patch KVM vectors */
218 case PSCI_CONDUIT_SMC:
219 arm_smccc_1_1_smc(ARM_SMCCC_ARCH_FEATURES_FUNC_ID,
220 ARM_SMCCC_ARCH_WORKAROUND_1, &res);
223 cb = call_smc_arch_workaround_1;
224 smccc_start = __smccc_workaround_1_smc_start;
225 smccc_end = __smccc_workaround_1_smc_end;
232 if (((midr & MIDR_CPU_MODEL_MASK) == MIDR_QCOM_FALKOR) ||
233 ((midr & MIDR_CPU_MODEL_MASK) == MIDR_QCOM_FALKOR_V1))
234 cb = qcom_link_stack_sanitization;
236 install_bp_hardening_cb(entry, cb, smccc_start, smccc_end);
240 #endif /* CONFIG_HARDEN_BRANCH_PREDICTOR */
242 #ifdef CONFIG_ARM64_SSBD
243 DEFINE_PER_CPU_READ_MOSTLY(u64, arm64_ssbd_callback_required);
245 int ssbd_state __read_mostly = ARM64_SSBD_KERNEL;
247 static const struct ssbd_options {
251 { "force-on", ARM64_SSBD_FORCE_ENABLE, },
252 { "force-off", ARM64_SSBD_FORCE_DISABLE, },
253 { "kernel", ARM64_SSBD_KERNEL, },
256 static int __init ssbd_cfg(char *buf)
263 for (i = 0; i < ARRAY_SIZE(ssbd_options); i++) {
264 int len = strlen(ssbd_options[i].str);
266 if (strncmp(buf, ssbd_options[i].str, len))
269 ssbd_state = ssbd_options[i].state;
275 early_param("ssbd", ssbd_cfg);
277 void __init arm64_update_smccc_conduit(struct alt_instr *alt,
278 __le32 *origptr, __le32 *updptr,
283 BUG_ON(nr_inst != 1);
285 switch (psci_ops.conduit) {
286 case PSCI_CONDUIT_HVC:
287 insn = aarch64_insn_get_hvc_value();
289 case PSCI_CONDUIT_SMC:
290 insn = aarch64_insn_get_smc_value();
296 *updptr = cpu_to_le32(insn);
299 void __init arm64_enable_wa2_handling(struct alt_instr *alt,
300 __le32 *origptr, __le32 *updptr,
303 BUG_ON(nr_inst != 1);
305 * Only allow mitigation on EL1 entry/exit and guest
306 * ARCH_WORKAROUND_2 handling if the SSBD state allows it to
309 if (arm64_get_ssbd_state() == ARM64_SSBD_KERNEL)
310 *updptr = cpu_to_le32(aarch64_insn_gen_nop());
313 void arm64_set_ssbd_mitigation(bool state)
315 if (this_cpu_has_cap(ARM64_SSBS)) {
317 asm volatile(SET_PSTATE_SSBS(0));
319 asm volatile(SET_PSTATE_SSBS(1));
323 switch (psci_ops.conduit) {
324 case PSCI_CONDUIT_HVC:
325 arm_smccc_1_1_hvc(ARM_SMCCC_ARCH_WORKAROUND_2, state, NULL);
328 case PSCI_CONDUIT_SMC:
329 arm_smccc_1_1_smc(ARM_SMCCC_ARCH_WORKAROUND_2, state, NULL);
338 static bool has_ssbd_mitigation(const struct arm64_cpu_capabilities *entry,
341 struct arm_smccc_res res;
342 bool required = true;
345 WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
347 if (this_cpu_has_cap(ARM64_SSBS)) {
352 if (psci_ops.smccc_version == SMCCC_VERSION_1_0) {
353 ssbd_state = ARM64_SSBD_UNKNOWN;
357 switch (psci_ops.conduit) {
358 case PSCI_CONDUIT_HVC:
359 arm_smccc_1_1_hvc(ARM_SMCCC_ARCH_FEATURES_FUNC_ID,
360 ARM_SMCCC_ARCH_WORKAROUND_2, &res);
363 case PSCI_CONDUIT_SMC:
364 arm_smccc_1_1_smc(ARM_SMCCC_ARCH_FEATURES_FUNC_ID,
365 ARM_SMCCC_ARCH_WORKAROUND_2, &res);
369 ssbd_state = ARM64_SSBD_UNKNOWN;
376 case SMCCC_RET_NOT_SUPPORTED:
377 ssbd_state = ARM64_SSBD_UNKNOWN;
380 case SMCCC_RET_NOT_REQUIRED:
381 pr_info_once("%s mitigation not required\n", entry->desc);
382 ssbd_state = ARM64_SSBD_MITIGATED;
385 case SMCCC_RET_SUCCESS:
389 case 1: /* Mitigation not required on this CPU */
398 switch (ssbd_state) {
399 case ARM64_SSBD_FORCE_DISABLE:
400 arm64_set_ssbd_mitigation(false);
404 case ARM64_SSBD_KERNEL:
406 __this_cpu_write(arm64_ssbd_callback_required, 1);
407 arm64_set_ssbd_mitigation(true);
411 case ARM64_SSBD_FORCE_ENABLE:
412 arm64_set_ssbd_mitigation(true);
422 switch (ssbd_state) {
423 case ARM64_SSBD_FORCE_DISABLE:
424 pr_info_once("%s disabled from command-line\n", entry->desc);
427 case ARM64_SSBD_FORCE_ENABLE:
428 pr_info_once("%s forced from command-line\n", entry->desc);
434 #endif /* CONFIG_ARM64_SSBD */
436 #define CAP_MIDR_RANGE(model, v_min, r_min, v_max, r_max) \
437 .matches = is_affected_midr_range, \
438 .midr_range = MIDR_RANGE(model, v_min, r_min, v_max, r_max)
440 #define CAP_MIDR_ALL_VERSIONS(model) \
441 .matches = is_affected_midr_range, \
442 .midr_range = MIDR_ALL_VERSIONS(model)
444 #define MIDR_FIXED(rev, revidr_mask) \
445 .fixed_revs = (struct arm64_midr_revidr[]){{ (rev), (revidr_mask) }, {}}
447 #define ERRATA_MIDR_RANGE(model, v_min, r_min, v_max, r_max) \
448 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, \
449 CAP_MIDR_RANGE(model, v_min, r_min, v_max, r_max)
451 #define CAP_MIDR_RANGE_LIST(list) \
452 .matches = is_affected_midr_range_list, \
453 .midr_range_list = list
455 /* Errata affecting a range of revisions of given model variant */
456 #define ERRATA_MIDR_REV_RANGE(m, var, r_min, r_max) \
457 ERRATA_MIDR_RANGE(m, var, r_min, var, r_max)
459 /* Errata affecting a single variant/revision of a model */
460 #define ERRATA_MIDR_REV(model, var, rev) \
461 ERRATA_MIDR_RANGE(model, var, rev, var, rev)
463 /* Errata affecting all variants/revisions of a given a model */
464 #define ERRATA_MIDR_ALL_VERSIONS(model) \
465 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, \
466 CAP_MIDR_ALL_VERSIONS(model)
468 /* Errata affecting a list of midr ranges, with same work around */
469 #define ERRATA_MIDR_RANGE_LIST(midr_list) \
470 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, \
471 CAP_MIDR_RANGE_LIST(midr_list)
474 * Generic helper for handling capabilties with multiple (match,enable) pairs
475 * of call backs, sharing the same capability bit.
476 * Iterate over each entry to see if at least one matches.
478 static bool __maybe_unused
479 multi_entry_cap_matches(const struct arm64_cpu_capabilities *entry, int scope)
481 const struct arm64_cpu_capabilities *caps;
483 for (caps = entry->match_list; caps->matches; caps++)
484 if (caps->matches(caps, scope))
491 * Take appropriate action for all matching entries in the shared capability
494 static void __maybe_unused
495 multi_entry_cap_cpu_enable(const struct arm64_cpu_capabilities *entry)
497 const struct arm64_cpu_capabilities *caps;
499 for (caps = entry->match_list; caps->matches; caps++)
500 if (caps->matches(caps, SCOPE_LOCAL_CPU) &&
502 caps->cpu_enable(caps);
505 #ifdef CONFIG_HARDEN_BRANCH_PREDICTOR
508 * List of CPUs where we need to issue a psci call to
509 * harden the branch predictor.
511 static const struct midr_range arm64_bp_harden_smccc_cpus[] = {
512 MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
513 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
514 MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),
515 MIDR_ALL_VERSIONS(MIDR_CORTEX_A75),
516 MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN),
517 MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2),
518 MIDR_ALL_VERSIONS(MIDR_QCOM_FALKOR_V1),
519 MIDR_ALL_VERSIONS(MIDR_QCOM_FALKOR),
520 MIDR_ALL_VERSIONS(MIDR_NVIDIA_DENVER),
526 #ifdef CONFIG_HARDEN_EL2_VECTORS
528 static const struct midr_range arm64_harden_el2_vectors[] = {
529 MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
530 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
536 const struct arm64_cpu_capabilities arm64_errata[] = {
537 #if defined(CONFIG_ARM64_ERRATUM_826319) || \
538 defined(CONFIG_ARM64_ERRATUM_827319) || \
539 defined(CONFIG_ARM64_ERRATUM_824069)
541 /* Cortex-A53 r0p[012] */
542 .desc = "ARM errata 826319, 827319, 824069",
543 .capability = ARM64_WORKAROUND_CLEAN_CACHE,
544 ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 2),
545 .cpu_enable = cpu_enable_cache_maint_trap,
548 #ifdef CONFIG_ARM64_ERRATUM_819472
550 /* Cortex-A53 r0p[01] */
551 .desc = "ARM errata 819472",
552 .capability = ARM64_WORKAROUND_CLEAN_CACHE,
553 ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 1),
554 .cpu_enable = cpu_enable_cache_maint_trap,
557 #ifdef CONFIG_ARM64_ERRATUM_832075
559 /* Cortex-A57 r0p0 - r1p2 */
560 .desc = "ARM erratum 832075",
561 .capability = ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE,
562 ERRATA_MIDR_RANGE(MIDR_CORTEX_A57,
567 #ifdef CONFIG_ARM64_ERRATUM_834220
569 /* Cortex-A57 r0p0 - r1p2 */
570 .desc = "ARM erratum 834220",
571 .capability = ARM64_WORKAROUND_834220,
572 ERRATA_MIDR_RANGE(MIDR_CORTEX_A57,
577 #ifdef CONFIG_ARM64_ERRATUM_843419
579 /* Cortex-A53 r0p[01234] */
580 .desc = "ARM erratum 843419",
581 .capability = ARM64_WORKAROUND_843419,
582 ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 4),
583 MIDR_FIXED(0x4, BIT(8)),
586 #ifdef CONFIG_ARM64_ERRATUM_845719
588 /* Cortex-A53 r0p[01234] */
589 .desc = "ARM erratum 845719",
590 .capability = ARM64_WORKAROUND_845719,
591 ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 4),
594 #ifdef CONFIG_CAVIUM_ERRATUM_23154
596 /* Cavium ThunderX, pass 1.x */
597 .desc = "Cavium erratum 23154",
598 .capability = ARM64_WORKAROUND_CAVIUM_23154,
599 ERRATA_MIDR_REV_RANGE(MIDR_THUNDERX, 0, 0, 1),
602 #ifdef CONFIG_CAVIUM_ERRATUM_27456
604 /* Cavium ThunderX, T88 pass 1.x - 2.1 */
605 .desc = "Cavium erratum 27456",
606 .capability = ARM64_WORKAROUND_CAVIUM_27456,
607 ERRATA_MIDR_RANGE(MIDR_THUNDERX,
612 /* Cavium ThunderX, T81 pass 1.0 */
613 .desc = "Cavium erratum 27456",
614 .capability = ARM64_WORKAROUND_CAVIUM_27456,
615 ERRATA_MIDR_REV(MIDR_THUNDERX_81XX, 0, 0),
618 #ifdef CONFIG_CAVIUM_ERRATUM_30115
620 /* Cavium ThunderX, T88 pass 1.x - 2.2 */
621 .desc = "Cavium erratum 30115",
622 .capability = ARM64_WORKAROUND_CAVIUM_30115,
623 ERRATA_MIDR_RANGE(MIDR_THUNDERX,
628 /* Cavium ThunderX, T81 pass 1.0 - 1.2 */
629 .desc = "Cavium erratum 30115",
630 .capability = ARM64_WORKAROUND_CAVIUM_30115,
631 ERRATA_MIDR_REV_RANGE(MIDR_THUNDERX_81XX, 0, 0, 2),
634 /* Cavium ThunderX, T83 pass 1.0 */
635 .desc = "Cavium erratum 30115",
636 .capability = ARM64_WORKAROUND_CAVIUM_30115,
637 ERRATA_MIDR_REV(MIDR_THUNDERX_83XX, 0, 0),
641 .desc = "Mismatched cache line size",
642 .capability = ARM64_MISMATCHED_CACHE_LINE_SIZE,
643 .matches = has_mismatched_cache_type,
644 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
645 .cpu_enable = cpu_enable_trap_ctr_access,
648 .desc = "Mismatched cache type",
649 .capability = ARM64_MISMATCHED_CACHE_TYPE,
650 .matches = has_mismatched_cache_type,
651 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
652 .cpu_enable = cpu_enable_trap_ctr_access,
654 #ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003
656 .desc = "Qualcomm Technologies Falkor erratum 1003",
657 .capability = ARM64_WORKAROUND_QCOM_FALKOR_E1003,
658 ERRATA_MIDR_REV(MIDR_QCOM_FALKOR_V1, 0, 0),
661 .desc = "Qualcomm Technologies Kryo erratum 1003",
662 .capability = ARM64_WORKAROUND_QCOM_FALKOR_E1003,
663 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
664 .midr_range.model = MIDR_QCOM_KRYO,
665 .matches = is_kryo_midr,
668 #ifdef CONFIG_QCOM_FALKOR_ERRATUM_1009
670 .desc = "Qualcomm Technologies Falkor erratum 1009",
671 .capability = ARM64_WORKAROUND_REPEAT_TLBI,
672 ERRATA_MIDR_REV(MIDR_QCOM_FALKOR_V1, 0, 0),
675 #ifdef CONFIG_ARM64_ERRATUM_858921
677 /* Cortex-A73 all versions */
678 .desc = "ARM erratum 858921",
679 .capability = ARM64_WORKAROUND_858921,
680 ERRATA_MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),
683 #ifdef CONFIG_HARDEN_BRANCH_PREDICTOR
685 .capability = ARM64_HARDEN_BRANCH_PREDICTOR,
686 .cpu_enable = enable_smccc_arch_workaround_1,
687 ERRATA_MIDR_RANGE_LIST(arm64_bp_harden_smccc_cpus),
690 #ifdef CONFIG_HARDEN_EL2_VECTORS
692 .desc = "EL2 vector hardening",
693 .capability = ARM64_HARDEN_EL2_VECTORS,
694 ERRATA_MIDR_RANGE_LIST(arm64_harden_el2_vectors),
697 #ifdef CONFIG_ARM64_SSBD
699 .desc = "Speculative Store Bypass Disable",
700 .capability = ARM64_SSBD,
701 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
702 .matches = has_ssbd_mitigation,