arch/arm64/kernel/cpufeature.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Contains CPU feature definitions
   4  *
   5  * Copyright (C) 2015 ARM Ltd.
   6  */
   7
   8 #define pr_fmt(fmt) "CPU features: " fmt
   9
  10 #include <linux/bsearch.h>
  11 #include <linux/cpumask.h>
  12 #include <linux/crash_dump.h>
  13 #include <linux/sort.h>
  14 #include <linux/stop_machine.h>
  15 #include <linux/types.h>
  16 #include <linux/mm.h>
  17 #include <linux/cpu.h>
  18 #include <asm/cpu.h>
  19 #include <asm/cpufeature.h>
  20 #include <asm/cpu_ops.h>
  21 #include <asm/fpsimd.h>
  22 #include <asm/mmu_context.h>
  23 #include <asm/processor.h>
  24 #include <asm/sysreg.h>
  25 #include <asm/traps.h>
  26 #include <asm/virt.h>
  27
  28 /* Kernel representation of AT_HWCAP and AT_HWCAP2 */
  29 static unsigned long elf_hwcap __read_mostly;
  30
  31 #ifdef CONFIG_COMPAT
  32 #define COMPAT_ELF_HWCAP_DEFAULT        \
  33                                 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\
  34                                  COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\
  35                                  COMPAT_HWCAP_TLS|COMPAT_HWCAP_VFP|\
  36                                  COMPAT_HWCAP_VFPv3|COMPAT_HWCAP_VFPv4|\
  37                                  COMPAT_HWCAP_NEON|COMPAT_HWCAP_IDIV|\
  38                                  COMPAT_HWCAP_LPAE)
  39 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT;
  40 unsigned int compat_elf_hwcap2 __read_mostly;
  41 #endif
  42
  43 DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS);
  44 EXPORT_SYMBOL(cpu_hwcaps);
  45 static struct arm64_cpu_capabilities const __ro_after_init *cpu_hwcaps_ptrs[ARM64_NCAPS];
  46
  47 /* Need also bit for ARM64_CB_PATCH */
  48 DECLARE_BITMAP(boot_capabilities, ARM64_NPATCHABLE);
  49
  50 /*
  51  * Flag to indicate if we have computed the system wide
  52  * capabilities based on the boot time active CPUs. This
  53  * will be used to determine if a new booting CPU should
  54  * go through the verification process to make sure that it
  55  * supports the system capabilities, without using a hotplug
  56  * notifier.
  57  */
  58 static bool sys_caps_initialised;
  59
  60 static inline void set_sys_caps_initialised(void)
  61 {
  62         sys_caps_initialised = true;
  63 }
  64
  65 static int dump_cpu_hwcaps(struct notifier_block *self, unsigned long v, void *p)
  66 {
  67         /* file-wide pr_fmt adds "CPU features: " prefix */
  68         pr_emerg("0x%*pb\n", ARM64_NCAPS, &cpu_hwcaps);
  69         return 0;
  70 }
  71
  72 static struct notifier_block cpu_hwcaps_notifier = {
  73         .notifier_call = dump_cpu_hwcaps
  74 };
  75
  76 static int __init register_cpu_hwcaps_dumper(void)
  77 {
  78         atomic_notifier_chain_register(&panic_notifier_list,
  79                                        &cpu_hwcaps_notifier);
  80         return 0;
  81 }
  82 __initcall(register_cpu_hwcaps_dumper);
  83
  84 DEFINE_STATIC_KEY_ARRAY_FALSE(cpu_hwcap_keys, ARM64_NCAPS);
  85 EXPORT_SYMBOL(cpu_hwcap_keys);
  86
  87 #define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
  88         {                                               \
  89                 .sign = SIGNED,                         \
  90                 .visible = VISIBLE,                     \
  91                 .strict = STRICT,                       \
  92                 .type = TYPE,                           \
  93                 .shift = SHIFT,                         \
  94                 .width = WIDTH,                         \
  95                 .safe_val = SAFE_VAL,                   \
  96         }
  97
  98 /* Define a feature with unsigned values */
  99 #define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
 100         __ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
 101
 102 /* Define a feature with a signed value */
 103 #define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
 104         __ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
 105
 106 #define ARM64_FTR_END                                   \
 107         {                                               \
 108                 .width = 0,                             \
 109         }
 110
 111 /* meta feature for alternatives */
 112 static bool __maybe_unused
 113 cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused);
 114
 115 static void cpu_enable_cnp(struct arm64_cpu_capabilities const *cap);
 116
 117 /*
 118  * NOTE: Any changes to the visibility of features should be kept in
 119  * sync with the documentation of the CPU feature register ABI.
 120  */
 121 static const struct arm64_ftr_bits ftr_id_aa64isar0[] = {
 122         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_RNDR_SHIFT, 4, 0),
 123         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_TS_SHIFT, 4, 0),
 124         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_FHM_SHIFT, 4, 0),
 125         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_DP_SHIFT, 4, 0),
 126         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM4_SHIFT, 4, 0),
 127         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM3_SHIFT, 4, 0),
 128         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA3_SHIFT, 4, 0),
 129         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_RDM_SHIFT, 4, 0),
 130         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_ATOMICS_SHIFT, 4, 0),
 131         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_CRC32_SHIFT, 4, 0),
 132         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA2_SHIFT, 4, 0),
 133         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA1_SHIFT, 4, 0),
 134         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_AES_SHIFT, 4, 0),
 135         ARM64_FTR_END,
 136 };
 137
 138 static const struct arm64_ftr_bits ftr_id_aa64isar1[] = {
 139         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_SB_SHIFT, 4, 0),
 140         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FRINTTS_SHIFT, 4, 0),
 141         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
 142                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_GPI_SHIFT, 4, 0),
 143         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
 144                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_GPA_SHIFT, 4, 0),
 145         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_LRCPC_SHIFT, 4, 0),
 146         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FCMA_SHIFT, 4, 0),
 147         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_JSCVT_SHIFT, 4, 0),
 148         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
 149                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_API_SHIFT, 4, 0),
 150         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
 151                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_APA_SHIFT, 4, 0),
 152         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_DPB_SHIFT, 4, 0),
 153         ARM64_FTR_END,
 154 };
 155
 156 static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = {
 157         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV3_SHIFT, 4, 0),
 158         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV2_SHIFT, 4, 0),
 159         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_DIT_SHIFT, 4, 0),
 160         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
 161                                    FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_SVE_SHIFT, 4, 0),
 162         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_RAS_SHIFT, 4, 0),
 163         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_GIC_SHIFT, 4, 0),
 164         S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_ASIMD_SHIFT, 4, ID_AA64PFR0_ASIMD_NI),
 165         S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI),
 166         /* Linux doesn't care about the EL3 */
 167         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL3_SHIFT, 4, 0),
 168         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL2_SHIFT, 4, 0),
 169         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SHIFT, 4, ID_AA64PFR0_EL1_64BIT_ONLY),
 170         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL0_SHIFT, 4, ID_AA64PFR0_EL0_64BIT_ONLY),
 171         ARM64_FTR_END,
 172 };
 173
 174 static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = {
 175         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_SSBS_SHIFT, 4, ID_AA64PFR1_SSBS_PSTATE_NI),
 176         ARM64_FTR_END,
 177 };
 178
 179 static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = {
 180         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
 181                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SM4_SHIFT, 4, 0),
 182         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
 183                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SHA3_SHIFT, 4, 0),
 184         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
 185                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_BITPERM_SHIFT, 4, 0),
 186         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
 187                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_AES_SHIFT, 4, 0),
 188         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
 189                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SVEVER_SHIFT, 4, 0),
 190         ARM64_FTR_END,
 191 };
 192
 193 static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = {
 194         /*
 195          * We already refuse to boot CPUs that don't support our configured
 196          * page size, so we can only detect mismatches for a page size other
 197          * than the one we're currently using. Unfortunately, SoCs like this
 198          * exist in the wild so, even though we don't like it, we'll have to go
 199          * along with it and treat them as non-strict.
 200          */
 201         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN4_SHIFT, 4, ID_AA64MMFR0_TGRAN4_NI),
 202         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN64_SHIFT, 4, ID_AA64MMFR0_TGRAN64_NI),
 203         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN16_SHIFT, 4, ID_AA64MMFR0_TGRAN16_NI),
 204
 205         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL0_SHIFT, 4, 0),
 206         /* Linux shouldn't care about secure memory */
 207         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_SNSMEM_SHIFT, 4, 0),
 208         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL_SHIFT, 4, 0),
 209         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_ASID_SHIFT, 4, 0),
 210         /*
 211          * Differing PARange is fine as long as all peripherals and memory are mapped
 212          * within the minimum PARange of all CPUs
 213          */
 214         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_PARANGE_SHIFT, 4, 0),
 215         ARM64_FTR_END,
 216 };
 217
 218 static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = {
 219         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_PAN_SHIFT, 4, 0),
 220         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_LOR_SHIFT, 4, 0),
 221         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HPD_SHIFT, 4, 0),
 222         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VHE_SHIFT, 4, 0),
 223         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VMIDBITS_SHIFT, 4, 0),
 224         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HADBS_SHIFT, 4, 0),
 225         ARM64_FTR_END,
 226 };
 227
 228 static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = {
 229         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_FWB_SHIFT, 4, 0),
 230         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_AT_SHIFT, 4, 0),
 231         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LVA_SHIFT, 4, 0),
 232         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_IESB_SHIFT, 4, 0),
 233         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LSM_SHIFT, 4, 0),
 234         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_UAO_SHIFT, 4, 0),
 235         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_CNP_SHIFT, 4, 0),
 236         ARM64_FTR_END,
 237 };
 238
 239 static const struct arm64_ftr_bits ftr_ctr[] = {
 240         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RES1 */
 241         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DIC_SHIFT, 1, 1),
 242         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IDC_SHIFT, 1, 1),
 243         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_CWG_SHIFT, 4, 0),
 244         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_ERG_SHIFT, 4, 0),
 245         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DMINLINE_SHIFT, 4, 1),
 246         /*
 247          * Linux can handle differing I-cache policies. Userspace JITs will
 248          * make use of *minLine.
 249          * If we have differing I-cache policies, report it as the weakest - VIPT.
 250          */
 251         ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, 14, 2, ICACHE_POLICY_VIPT),       /* L1Ip */
 252         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IMINLINE_SHIFT, 4, 0),
 253         ARM64_FTR_END,
 254 };
 255
 256 struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = {
 257         .name           = "SYS_CTR_EL0",
 258         .ftr_bits       = ftr_ctr
 259 };
 260
 261 static const struct arm64_ftr_bits ftr_id_mmfr0[] = {
 262         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0xf),   /* InnerShr */
 263         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0),       /* FCSE */
 264         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, 20, 4, 0),    /* AuxReg */
 265         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),       /* TCM */
 266         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),       /* ShareLvl */
 267         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0xf),    /* OuterShr */
 268         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),        /* PMSA */
 269         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),        /* VMSA */
 270         ARM64_FTR_END,
 271 };
 272
 273 static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = {
 274         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 36, 28, 0),
 275         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_PMSVER_SHIFT, 4, 0),
 276         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_CTX_CMPS_SHIFT, 4, 0),
 277         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_WRPS_SHIFT, 4, 0),
 278         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_BRPS_SHIFT, 4, 0),
 279         /*
 280          * We can instantiate multiple PMU instances with different levels
 281          * of support.
 282          */
 283         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_PMUVER_SHIFT, 4, 0),
 284         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_TRACEVER_SHIFT, 4, 0),
 285         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_DEBUGVER_SHIFT, 4, 0x6),
 286         ARM64_FTR_END,
 287 };
 288
 289 static const struct arm64_ftr_bits ftr_mvfr2[] = {
 290         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),                /* FPMisc */
 291         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),                /* SIMDMisc */
 292         ARM64_FTR_END,
 293 };
 294
 295 static const struct arm64_ftr_bits ftr_dczid[] = {
 296         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 4, 1, 1),            /* DZP */
 297         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),       /* BS */
 298         ARM64_FTR_END,
 299 };
 300
 301
 302 static const struct arm64_ftr_bits ftr_id_isar5[] = {
 303         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_RDM_SHIFT, 4, 0),
 304         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_CRC32_SHIFT, 4, 0),
 305         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA2_SHIFT, 4, 0),
 306         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA1_SHIFT, 4, 0),
 307         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_AES_SHIFT, 4, 0),
 308         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SEVL_SHIFT, 4, 0),
 309         ARM64_FTR_END,
 310 };
 311
 312 static const struct arm64_ftr_bits ftr_id_mmfr4[] = {
 313         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),        /* ac2 */
 314         ARM64_FTR_END,
 315 };
 316
 317 static const struct arm64_ftr_bits ftr_id_pfr0[] = {
 318         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),               /* State3 */
 319         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),                /* State2 */
 320         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),                /* State1 */
 321         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),                /* State0 */
 322         ARM64_FTR_END,
 323 };
 324
 325 static const struct arm64_ftr_bits ftr_id_dfr0[] = {
 326         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
 327         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0xf),   /* PerfMon */
 328         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
 329         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
 330         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
 331         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
 332         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
 333         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
 334         ARM64_FTR_END,
 335 };
 336
 337 static const struct arm64_ftr_bits ftr_zcr[] = {
 338         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE,
 339                 ZCR_ELx_LEN_SHIFT, ZCR_ELx_LEN_SIZE, 0),        /* LEN */
 340         ARM64_FTR_END,
 341 };
 342
 343 /*
 344  * Common ftr bits for a 32bit register with all hidden, strict
 345  * attributes, with 4bit feature fields and a default safe value of
 346  * 0. Covers the following 32bit registers:
 347  * id_isar[0-4], id_mmfr[1-3], id_pfr1, mvfr[0-1]
 348  */
 349 static const struct arm64_ftr_bits ftr_generic_32bits[] = {
 350         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
 351         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0),
 352         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
 353         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
 354         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
 355         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
 356         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
 357         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
 358         ARM64_FTR_END,
 359 };
 360
 361 /* Table for a single 32bit feature value */
 362 static const struct arm64_ftr_bits ftr_single32[] = {
 363         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 32, 0),
 364         ARM64_FTR_END,
 365 };
 366
 367 static const struct arm64_ftr_bits ftr_raz[] = {
 368         ARM64_FTR_END,
 369 };
 370
 371 #define ARM64_FTR_REG(id, table) {              \
 372         .sys_id = id,                           \
 373         .reg =  &(struct arm64_ftr_reg){        \
 374                 .name = #id,                    \
 375                 .ftr_bits = &((table)[0]),      \
 376         }}
 377
 378 static const struct __ftr_reg_entry {
 379         u32                     sys_id;
 380         struct arm64_ftr_reg    *reg;
 381 } arm64_ftr_regs[] = {
 382
 383         /* Op1 = 0, CRn = 0, CRm = 1 */
 384         ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0),
 385         ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_generic_32bits),
 386         ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0),
 387         ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0),
 388         ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits),
 389         ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits),
 390         ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits),
 391
 392         /* Op1 = 0, CRn = 0, CRm = 2 */
 393         ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_generic_32bits),
 394         ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits),
 395         ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits),
 396         ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits),
 397         ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_generic_32bits),
 398         ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5),
 399         ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4),
 400
 401         /* Op1 = 0, CRn = 0, CRm = 3 */
 402         ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_generic_32bits),
 403         ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_generic_32bits),
 404         ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2),
 405
 406         /* Op1 = 0, CRn = 0, CRm = 4 */
 407         ARM64_FTR_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0),
 408         ARM64_FTR_REG(SYS_ID_AA64PFR1_EL1, ftr_id_aa64pfr1),
 409         ARM64_FTR_REG(SYS_ID_AA64ZFR0_EL1, ftr_id_aa64zfr0),
 410
 411         /* Op1 = 0, CRn = 0, CRm = 5 */
 412         ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0),
 413         ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz),
 414
 415         /* Op1 = 0, CRn = 0, CRm = 6 */
 416         ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0),
 417         ARM64_FTR_REG(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1),
 418
 419         /* Op1 = 0, CRn = 0, CRm = 7 */
 420         ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0),
 421         ARM64_FTR_REG(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1),
 422         ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2),
 423
 424         /* Op1 = 0, CRn = 1, CRm = 2 */
 425         ARM64_FTR_REG(SYS_ZCR_EL1, ftr_zcr),
 426
 427         /* Op1 = 3, CRn = 0, CRm = 0 */
 428         { SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 },
 429         ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid),
 430
 431         /* Op1 = 3, CRn = 14, CRm = 0 */
 432         ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_single32),
 433 };
 434
 435 static int search_cmp_ftr_reg(const void *id, const void *regp)
 436 {
 437         return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id;
 438 }
 439
 440 /*
 441  * get_arm64_ftr_reg - Lookup a feature register entry using its
 442  * sys_reg() encoding. With the array arm64_ftr_regs sorted in the
 443  * ascending order of sys_id , we use binary search to find a matching
 444  * entry.
 445  *
 446  * returns - Upon success,  matching ftr_reg entry for id.
 447  *         - NULL on failure. It is upto the caller to decide
 448  *           the impact of a failure.
 449  */
 450 static struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id)
 451 {
 452         const struct __ftr_reg_entry *ret;
 453
 454         ret = bsearch((const void *)(unsigned long)sys_id,
 455                         arm64_ftr_regs,
 456                         ARRAY_SIZE(arm64_ftr_regs),
 457                         sizeof(arm64_ftr_regs[0]),
 458                         search_cmp_ftr_reg);
 459         if (ret)
 460                 return ret->reg;
 461         return NULL;
 462 }
 463
 464 static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg,
 465                                s64 ftr_val)
 466 {
 467         u64 mask = arm64_ftr_mask(ftrp);
 468
 469         reg &= ~mask;
 470         reg |= (ftr_val << ftrp->shift) & mask;
 471         return reg;
 472 }
 473
 474 static s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new,
 475                                 s64 cur)
 476 {
 477         s64 ret = 0;
 478
 479         switch (ftrp->type) {
 480         case FTR_EXACT:
 481                 ret = ftrp->safe_val;
 482                 break;
 483         case FTR_LOWER_SAFE:
 484                 ret = new < cur ? new : cur;
 485                 break;
 486         case FTR_HIGHER_OR_ZERO_SAFE:
 487                 if (!cur || !new)
 488                         break;
 489                 /* Fallthrough */
 490         case FTR_HIGHER_SAFE:
 491                 ret = new > cur ? new : cur;
 492                 break;
 493         default:
 494                 BUG();
 495         }
 496
 497         return ret;
 498 }
 499
 500 static void __init sort_ftr_regs(void)
 501 {
 502         int i;
 503
 504         /* Check that the array is sorted so that we can do the binary search */
 505         for (i = 1; i < ARRAY_SIZE(arm64_ftr_regs); i++)
 506                 BUG_ON(arm64_ftr_regs[i].sys_id < arm64_ftr_regs[i - 1].sys_id);
 507 }
 508
 509 /*
 510  * Initialise the CPU feature register from Boot CPU values.
 511  * Also initiliases the strict_mask for the register.
 512  * Any bits that are not covered by an arm64_ftr_bits entry are considered
 513  * RES0 for the system-wide value, and must strictly match.
 514  */
 515 static void __init init_cpu_ftr_reg(u32 sys_reg, u64 new)
 516 {
 517         u64 val = 0;
 518         u64 strict_mask = ~0x0ULL;
 519         u64 user_mask = 0;
 520         u64 valid_mask = 0;
 521
 522         const struct arm64_ftr_bits *ftrp;
 523         struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg);
 524
 525         BUG_ON(!reg);
 526
 527         for (ftrp  = reg->ftr_bits; ftrp->width; ftrp++) {
 528                 u64 ftr_mask = arm64_ftr_mask(ftrp);
 529                 s64 ftr_new = arm64_ftr_value(ftrp, new);
 530
 531                 val = arm64_ftr_set_value(ftrp, val, ftr_new);
 532
 533                 valid_mask |= ftr_mask;
 534                 if (!ftrp->strict)
 535                         strict_mask &= ~ftr_mask;
 536                 if (ftrp->visible)
 537                         user_mask |= ftr_mask;
 538                 else
 539                         reg->user_val = arm64_ftr_set_value(ftrp,
 540                                                             reg->user_val,
 541                                                             ftrp->safe_val);
 542         }
 543
 544         val &= valid_mask;
 545
 546         reg->sys_val = val;
 547         reg->strict_mask = strict_mask;
 548         reg->user_mask = user_mask;
 549 }
 550
 551 extern const struct arm64_cpu_capabilities arm64_errata[];
 552 static const struct arm64_cpu_capabilities arm64_features[];
 553
 554 static void __init
 555 init_cpu_hwcaps_indirect_list_from_array(const struct arm64_cpu_capabilities *caps)
 556 {
 557         for (; caps->matches; caps++) {
 558                 if (WARN(caps->capability >= ARM64_NCAPS,
 559                         "Invalid capability %d\n", caps->capability))
 560                         continue;
 561                 if (WARN(cpu_hwcaps_ptrs[caps->capability],
 562                         "Duplicate entry for capability %d\n",
 563                         caps->capability))
 564                         continue;
 565                 cpu_hwcaps_ptrs[caps->capability] = caps;
 566         }
 567 }
 568
 569 static void __init init_cpu_hwcaps_indirect_list(void)
 570 {
 571         init_cpu_hwcaps_indirect_list_from_array(arm64_features);
 572         init_cpu_hwcaps_indirect_list_from_array(arm64_errata);
 573 }
 574
 575 static void __init setup_boot_cpu_capabilities(void);
 576
 577 void __init init_cpu_features(struct cpuinfo_arm64 *info)
 578 {
 579         /* Before we start using the tables, make sure it is sorted */
 580         sort_ftr_regs();
 581
 582         init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr);
 583         init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid);
 584         init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq);
 585         init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0);
 586         init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1);
 587         init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0);
 588         init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1);
 589         init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0);
 590         init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1);
 591         init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2);
 592         init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0);
 593         init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1);
 594         init_cpu_ftr_reg(SYS_ID_AA64ZFR0_EL1, info->reg_id_aa64zfr0);
 595
 596         if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
 597                 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0);
 598                 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0);
 599                 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1);
 600                 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2);
 601                 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3);
 602                 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4);
 603                 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5);
 604                 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0);
 605                 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1);
 606                 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2);
 607                 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3);
 608                 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0);
 609                 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1);
 610                 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0);
 611                 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1);
 612                 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2);
 613         }
 614
 615         if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) {
 616                 init_cpu_ftr_reg(SYS_ZCR_EL1, info->reg_zcr);
 617                 sve_init_vq_map();
 618         }
 619
 620         /*
 621          * Initialize the indirect array of CPU hwcaps capabilities pointers
 622          * before we handle the boot CPU below.
 623          */
 624         init_cpu_hwcaps_indirect_list();
 625
 626         /*
 627          * Detect and enable early CPU capabilities based on the boot CPU,
 628          * after we have initialised the CPU feature infrastructure.
 629          */
 630         setup_boot_cpu_capabilities();
 631 }
 632
 633 static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new)
 634 {
 635         const struct arm64_ftr_bits *ftrp;
 636
 637         for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
 638                 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val);
 639                 s64 ftr_new = arm64_ftr_value(ftrp, new);
 640
 641                 if (ftr_cur == ftr_new)
 642                         continue;
 643                 /* Find a safe value */
 644                 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur);
 645                 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new);
 646         }
 647
 648 }
 649
 650 static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot)
 651 {
 652         struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id);
 653
 654         BUG_ON(!regp);
 655         update_cpu_ftr_reg(regp, val);
 656         if ((boot & regp->strict_mask) == (val & regp->strict_mask))
 657                 return 0;
 658         pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n",
 659                         regp->name, boot, cpu, val);
 660         return 1;
 661 }
 662
 663 /*
 664  * Update system wide CPU feature registers with the values from a
 665  * non-boot CPU. Also performs SANITY checks to make sure that there
 666  * aren't any insane variations from that of the boot CPU.
 667  */
 668 void update_cpu_features(int cpu,
 669                          struct cpuinfo_arm64 *info,
 670                          struct cpuinfo_arm64 *boot)
 671 {
 672         int taint = 0;
 673
 674         /*
 675          * The kernel can handle differing I-cache policies, but otherwise
 676          * caches should look identical. Userspace JITs will make use of
 677          * *minLine.
 678          */
 679         taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu,
 680                                       info->reg_ctr, boot->reg_ctr);
 681
 682         /*
 683          * Userspace may perform DC ZVA instructions. Mismatched block sizes
 684          * could result in too much or too little memory being zeroed if a
 685          * process is preempted and migrated between CPUs.
 686          */
 687         taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu,
 688                                       info->reg_dczid, boot->reg_dczid);
 689
 690         /* If different, timekeeping will be broken (especially with KVM) */
 691         taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu,
 692                                       info->reg_cntfrq, boot->reg_cntfrq);
 693
 694         /*
 695          * The kernel uses self-hosted debug features and expects CPUs to
 696          * support identical debug features. We presently need CTX_CMPs, WRPs,
 697          * and BRPs to be identical.
 698          * ID_AA64DFR1 is currently RES0.
 699          */
 700         taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu,
 701                                       info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0);
 702         taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu,
 703                                       info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1);
 704         /*
 705          * Even in big.LITTLE, processors should be identical instruction-set
 706          * wise.
 707          */
 708         taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu,
 709                                       info->reg_id_aa64isar0, boot->reg_id_aa64isar0);
 710         taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu,
 711                                       info->reg_id_aa64isar1, boot->reg_id_aa64isar1);
 712
 713         /*
 714          * Differing PARange support is fine as long as all peripherals and
 715          * memory are mapped within the minimum PARange of all CPUs.
 716          * Linux should not care about secure memory.
 717          */
 718         taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu,
 719                                       info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0);
 720         taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu,
 721                                       info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1);
 722         taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu,
 723                                       info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2);
 724
 725         /*
 726          * EL3 is not our concern.
 727          */
 728         taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu,
 729                                       info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0);
 730         taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu,
 731                                       info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1);
 732
 733         taint |= check_update_ftr_reg(SYS_ID_AA64ZFR0_EL1, cpu,
 734                                       info->reg_id_aa64zfr0, boot->reg_id_aa64zfr0);
 735
 736         /*
 737          * If we have AArch32, we care about 32-bit features for compat.
 738          * If the system doesn't support AArch32, don't update them.
 739          */
 740         if (id_aa64pfr0_32bit_el0(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1)) &&
 741                 id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
 742
 743                 taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu,
 744                                         info->reg_id_dfr0, boot->reg_id_dfr0);
 745                 taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu,
 746                                         info->reg_id_isar0, boot->reg_id_isar0);
 747                 taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu,
 748                                         info->reg_id_isar1, boot->reg_id_isar1);
 749                 taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu,
 750                                         info->reg_id_isar2, boot->reg_id_isar2);
 751                 taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu,
 752                                         info->reg_id_isar3, boot->reg_id_isar3);
 753                 taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu,
 754                                         info->reg_id_isar4, boot->reg_id_isar4);
 755                 taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu,
 756                                         info->reg_id_isar5, boot->reg_id_isar5);
 757
 758                 /*
 759                  * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and
 760                  * ACTLR formats could differ across CPUs and therefore would have to
 761                  * be trapped for virtualization anyway.
 762                  */
 763                 taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu,
 764                                         info->reg_id_mmfr0, boot->reg_id_mmfr0);
 765                 taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu,
 766                                         info->reg_id_mmfr1, boot->reg_id_mmfr1);
 767                 taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu,
 768                                         info->reg_id_mmfr2, boot->reg_id_mmfr2);
 769                 taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu,
 770                                         info->reg_id_mmfr3, boot->reg_id_mmfr3);
 771                 taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu,
 772                                         info->reg_id_pfr0, boot->reg_id_pfr0);
 773                 taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu,
 774                                         info->reg_id_pfr1, boot->reg_id_pfr1);
 775                 taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu,
 776                                         info->reg_mvfr0, boot->reg_mvfr0);
 777                 taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu,
 778                                         info->reg_mvfr1, boot->reg_mvfr1);
 779                 taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu,
 780                                         info->reg_mvfr2, boot->reg_mvfr2);
 781         }
 782
 783         if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) {
 784                 taint |= check_update_ftr_reg(SYS_ZCR_EL1, cpu,
 785                                         info->reg_zcr, boot->reg_zcr);
 786
 787                 /* Probe vector lengths, unless we already gave up on SVE */
 788                 if (id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1)) &&
 789                     !sys_caps_initialised)
 790                         sve_update_vq_map();
 791         }
 792
 793         /*
 794          * Mismatched CPU features are a recipe for disaster. Don't even
 795          * pretend to support them.
 796          */
 797         if (taint) {
 798                 pr_warn_once("Unsupported CPU feature variation detected.\n");
 799                 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK);
 800         }
 801 }
 802
 803 u64 read_sanitised_ftr_reg(u32 id)
 804 {
 805         struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id);
 806
 807         /* We shouldn't get a request for an unsupported register */
 808         BUG_ON(!regp);
 809         return regp->sys_val;
 810 }
 811
 812 #define read_sysreg_case(r)     \
 813         case r:         return read_sysreg_s(r)
 814
 815 /*
 816  * __read_sysreg_by_encoding() - Used by a STARTING cpu before cpuinfo is populated.
 817  * Read the system register on the current CPU
 818  */
 819 static u64 __read_sysreg_by_encoding(u32 sys_id)
 820 {
 821         switch (sys_id) {
 822         read_sysreg_case(SYS_ID_PFR0_EL1);
 823         read_sysreg_case(SYS_ID_PFR1_EL1);
 824         read_sysreg_case(SYS_ID_DFR0_EL1);
 825         read_sysreg_case(SYS_ID_MMFR0_EL1);
 826         read_sysreg_case(SYS_ID_MMFR1_EL1);
 827         read_sysreg_case(SYS_ID_MMFR2_EL1);
 828         read_sysreg_case(SYS_ID_MMFR3_EL1);
 829         read_sysreg_case(SYS_ID_ISAR0_EL1);
 830         read_sysreg_case(SYS_ID_ISAR1_EL1);
 831         read_sysreg_case(SYS_ID_ISAR2_EL1);
 832         read_sysreg_case(SYS_ID_ISAR3_EL1);
 833         read_sysreg_case(SYS_ID_ISAR4_EL1);
 834         read_sysreg_case(SYS_ID_ISAR5_EL1);
 835         read_sysreg_case(SYS_MVFR0_EL1);
 836         read_sysreg_case(SYS_MVFR1_EL1);
 837         read_sysreg_case(SYS_MVFR2_EL1);
 838
 839         read_sysreg_case(SYS_ID_AA64PFR0_EL1);
 840         read_sysreg_case(SYS_ID_AA64PFR1_EL1);
 841         read_sysreg_case(SYS_ID_AA64ZFR0_EL1);
 842         read_sysreg_case(SYS_ID_AA64DFR0_EL1);
 843         read_sysreg_case(SYS_ID_AA64DFR1_EL1);
 844         read_sysreg_case(SYS_ID_AA64MMFR0_EL1);
 845         read_sysreg_case(SYS_ID_AA64MMFR1_EL1);
 846         read_sysreg_case(SYS_ID_AA64MMFR2_EL1);
 847         read_sysreg_case(SYS_ID_AA64ISAR0_EL1);
 848         read_sysreg_case(SYS_ID_AA64ISAR1_EL1);
 849
 850         read_sysreg_case(SYS_CNTFRQ_EL0);
 851         read_sysreg_case(SYS_CTR_EL0);
 852         read_sysreg_case(SYS_DCZID_EL0);
 853
 854         default:
 855                 BUG();
 856                 return 0;
 857         }
 858 }
 859
 860 #include <linux/irqchip/arm-gic-v3.h>
 861
 862 static bool
 863 feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry)
 864 {
 865         int val = cpuid_feature_extract_field(reg, entry->field_pos, entry->sign);
 866
 867         return val >= entry->min_field_value;
 868 }
 869
 870 static bool
 871 has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope)
 872 {
 873         u64 val;
 874
 875         WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible());
 876         if (scope == SCOPE_SYSTEM)
 877                 val = read_sanitised_ftr_reg(entry->sys_reg);
 878         else
 879                 val = __read_sysreg_by_encoding(entry->sys_reg);
 880
 881         return feature_matches(val, entry);
 882 }
 883
 884 static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope)
 885 {
 886         bool has_sre;
 887
 888         if (!has_cpuid_feature(entry, scope))
 889                 return false;
 890
 891         has_sre = gic_enable_sre();
 892         if (!has_sre)
 893                 pr_warn_once("%s present but disabled by higher exception level\n",
 894                              entry->desc);
 895
 896         return has_sre;
 897 }
 898
 899 static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities *entry, int __unused)
 900 {
 901         u32 midr = read_cpuid_id();
 902
 903         /* Cavium ThunderX pass 1.x and 2.x */
 904         return midr_is_cpu_model_range(midr, MIDR_THUNDERX,
 905                 MIDR_CPU_VAR_REV(0, 0),
 906                 MIDR_CPU_VAR_REV(1, MIDR_REVISION_MASK));
 907 }
 908
 909 static bool has_no_fpsimd(const struct arm64_cpu_capabilities *entry, int __unused)
 910 {
 911         u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
 912
 913         return cpuid_feature_extract_signed_field(pfr0,
 914                                         ID_AA64PFR0_FP_SHIFT) < 0;
 915 }
 916
 917 static bool has_cache_idc(const struct arm64_cpu_capabilities *entry,
 918                           int scope)
 919 {
 920         u64 ctr;
 921
 922         if (scope == SCOPE_SYSTEM)
 923                 ctr = arm64_ftr_reg_ctrel0.sys_val;
 924         else
 925                 ctr = read_cpuid_effective_cachetype();
 926
 927         return ctr & BIT(CTR_IDC_SHIFT);
 928 }
 929
 930 static void cpu_emulate_effective_ctr(const struct arm64_cpu_capabilities *__unused)
 931 {
 932         /*
 933          * If the CPU exposes raw CTR_EL0.IDC = 0, while effectively
 934          * CTR_EL0.IDC = 1 (from CLIDR values), we need to trap accesses
 935          * to the CTR_EL0 on this CPU and emulate it with the real/safe
 936          * value.
 937          */
 938         if (!(read_cpuid_cachetype() & BIT(CTR_IDC_SHIFT)))
 939                 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0);
 940 }
 941
 942 static bool has_cache_dic(const struct arm64_cpu_capabilities *entry,
 943                           int scope)
 944 {
 945         u64 ctr;
 946
 947         if (scope == SCOPE_SYSTEM)
 948                 ctr = arm64_ftr_reg_ctrel0.sys_val;
 949         else
 950                 ctr = read_cpuid_cachetype();
 951
 952         return ctr & BIT(CTR_DIC_SHIFT);
 953 }
 954
 955 static bool __maybe_unused
 956 has_useable_cnp(const struct arm64_cpu_capabilities *entry, int scope)
 957 {
 958         /*
 959          * Kdump isn't guaranteed to power-off all secondary CPUs, CNP
 960          * may share TLB entries with a CPU stuck in the crashed
 961          * kernel.
 962          */
 963          if (is_kdump_kernel())
 964                 return false;
 965
 966         return has_cpuid_feature(entry, scope);
 967 }
 968
 969 static bool __meltdown_safe = true;
 970 static int __kpti_forced; /* 0: not forced, >0: forced on, <0: forced off */
 971
 972 static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry,
 973                                 int scope)
 974 {
 975         /* List of CPUs that are not vulnerable and don't need KPTI */
 976         static const struct midr_range kpti_safe_list[] = {
 977                 MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2),
 978                 MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN),
 979                 MIDR_ALL_VERSIONS(MIDR_CORTEX_A35),
 980                 MIDR_ALL_VERSIONS(MIDR_CORTEX_A53),
 981                 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
 982                 MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
 983                 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
 984                 MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),
 985                 MIDR_ALL_VERSIONS(MIDR_HISI_TSV110),
 986                 MIDR_ALL_VERSIONS(MIDR_NVIDIA_CARMEL),
 987                 { /* sentinel */ }
 988         };
 989         char const *str = "kpti command line option";
 990         bool meltdown_safe;
 991
 992         meltdown_safe = is_midr_in_range_list(read_cpuid_id(), kpti_safe_list);
 993
 994         /* Defer to CPU feature registers */
 995         if (has_cpuid_feature(entry, scope))
 996                 meltdown_safe = true;
 997
 998         if (!meltdown_safe)
 999                 __meltdown_safe = false;
1000
1001         /*
1002          * For reasons that aren't entirely clear, enabling KPTI on Cavium
1003          * ThunderX leads to apparent I-cache corruption of kernel text, which
1004          * ends as well as you might imagine. Don't even try.
1005          */
1006         if (cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_27456)) {
1007                 str = "ARM64_WORKAROUND_CAVIUM_27456";
1008                 __kpti_forced = -1;
1009         }
1010
1011         /* Useful for KASLR robustness */
1012         if (IS_ENABLED(CONFIG_RANDOMIZE_BASE) && kaslr_offset() > 0) {
1013                 if (!__kpti_forced) {
1014                         str = "KASLR";
1015                         __kpti_forced = 1;
1016                 }
1017         }
1018
1019         if (cpu_mitigations_off() && !__kpti_forced) {
1020                 str = "mitigations=off";
1021                 __kpti_forced = -1;
1022         }
1023
1024         if (!IS_ENABLED(CONFIG_UNMAP_KERNEL_AT_EL0)) {
1025                 pr_info_once("kernel page table isolation disabled by kernel configuration\n");
1026                 return false;
1027         }
1028
1029         /* Forced? */
1030         if (__kpti_forced) {
1031                 pr_info_once("kernel page table isolation forced %s by %s\n",
1032                              __kpti_forced > 0 ? "ON" : "OFF", str);
1033                 return __kpti_forced > 0;
1034         }
1035
1036         return !meltdown_safe;
1037 }
1038
1039 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
1040 static void
1041 kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused)
1042 {
1043         typedef void (kpti_remap_fn)(int, int, phys_addr_t);
1044         extern kpti_remap_fn idmap_kpti_install_ng_mappings;
1045         kpti_remap_fn *remap_fn;
1046
1047         static bool kpti_applied = false;
1048         int cpu = smp_processor_id();
1049
1050         /*
1051          * We don't need to rewrite the page-tables if either we've done
1052          * it already or we have KASLR enabled and therefore have not
1053          * created any global mappings at all.
1054          */
1055         if (kpti_applied || kaslr_offset() > 0)
1056                 return;
1057
1058         remap_fn = (void *)__pa_symbol(idmap_kpti_install_ng_mappings);
1059
1060         cpu_install_idmap();
1061         remap_fn(cpu, num_online_cpus(), __pa_symbol(swapper_pg_dir));
1062         cpu_uninstall_idmap();
1063
1064         if (!cpu)
1065                 kpti_applied = true;
1066
1067         return;
1068 }
1069 #else
1070 static void
1071 kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused)
1072 {
1073 }
1074 #endif  /* CONFIG_UNMAP_KERNEL_AT_EL0 */
1075
1076 static int __init parse_kpti(char *str)
1077 {
1078         bool enabled;
1079         int ret = strtobool(str, &enabled);
1080
1081         if (ret)
1082                 return ret;
1083
1084         __kpti_forced = enabled ? 1 : -1;
1085         return 0;
1086 }
1087 early_param("kpti", parse_kpti);
1088
1089 #ifdef CONFIG_ARM64_HW_AFDBM
1090 static inline void __cpu_enable_hw_dbm(void)
1091 {
1092         u64 tcr = read_sysreg(tcr_el1) | TCR_HD;
1093
1094         write_sysreg(tcr, tcr_el1);
1095         isb();
1096 }
1097
1098 static bool cpu_has_broken_dbm(void)
1099 {
1100         /* List of CPUs which have broken DBM support. */
1101         static const struct midr_range cpus[] = {
1102 #ifdef CONFIG_ARM64_ERRATUM_1024718
1103                 MIDR_RANGE(MIDR_CORTEX_A55, 0, 0, 1, 0),  // A55 r0p0 -r1p0
1104 #endif
1105                 {},
1106         };
1107
1108         return is_midr_in_range_list(read_cpuid_id(), cpus);
1109 }
1110
1111 static bool cpu_can_use_dbm(const struct arm64_cpu_capabilities *cap)
1112 {
1113         return has_cpuid_feature(cap, SCOPE_LOCAL_CPU) &&
1114                !cpu_has_broken_dbm();
1115 }
1116
1117 static void cpu_enable_hw_dbm(struct arm64_cpu_capabilities const *cap)
1118 {
1119         if (cpu_can_use_dbm(cap))
1120                 __cpu_enable_hw_dbm();
1121 }
1122
1123 static bool has_hw_dbm(const struct arm64_cpu_capabilities *cap,
1124                        int __unused)
1125 {
1126         static bool detected = false;
1127         /*
1128          * DBM is a non-conflicting feature. i.e, the kernel can safely
1129          * run a mix of CPUs with and without the feature. So, we
1130          * unconditionally enable the capability to allow any late CPU
1131          * to use the feature. We only enable the control bits on the
1132          * CPU, if it actually supports.
1133          *
1134          * We have to make sure we print the "feature" detection only
1135          * when at least one CPU actually uses it. So check if this CPU
1136          * can actually use it and print the message exactly once.
1137          *
1138          * This is safe as all CPUs (including secondary CPUs - due to the
1139          * LOCAL_CPU scope - and the hotplugged CPUs - via verification)
1140          * goes through the "matches" check exactly once. Also if a CPU
1141          * matches the criteria, it is guaranteed that the CPU will turn
1142          * the DBM on, as the capability is unconditionally enabled.
1143          */
1144         if (!detected && cpu_can_use_dbm(cap)) {
1145                 detected = true;
1146                 pr_info("detected: Hardware dirty bit management\n");
1147         }
1148
1149         return true;
1150 }
1151
1152 #endif
1153
1154 #ifdef CONFIG_ARM64_VHE
1155 static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused)
1156 {
1157         return is_kernel_in_hyp_mode();
1158 }
1159
1160 static void cpu_copy_el2regs(const struct arm64_cpu_capabilities *__unused)
1161 {
1162         /*
1163          * Copy register values that aren't redirected by hardware.
1164          *
1165          * Before code patching, we only set tpidr_el1, all CPUs need to copy
1166          * this value to tpidr_el2 before we patch the code. Once we've done
1167          * that, freshly-onlined CPUs will set tpidr_el2, so we don't need to
1168          * do anything here.
1169          */
1170         if (!alternative_is_applied(ARM64_HAS_VIRT_HOST_EXTN))
1171                 write_sysreg(read_sysreg(tpidr_el1), tpidr_el2);
1172 }
1173 #endif
1174
1175 static void cpu_has_fwb(const struct arm64_cpu_capabilities *__unused)
1176 {
1177         u64 val = read_sysreg_s(SYS_CLIDR_EL1);
1178
1179         /* Check that CLIDR_EL1.LOU{U,IS} are both 0 */
1180         WARN_ON(val & (7 << 27 | 7 << 21));
1181 }
1182
1183 #ifdef CONFIG_ARM64_SSBD
1184 static int ssbs_emulation_handler(struct pt_regs *regs, u32 instr)
1185 {
1186         if (user_mode(regs))
1187                 return 1;
1188
1189         if (instr & BIT(PSTATE_Imm_shift))
1190                 regs->pstate |= PSR_SSBS_BIT;
1191         else
1192                 regs->pstate &= ~PSR_SSBS_BIT;
1193
1194         arm64_skip_faulting_instruction(regs, 4);
1195         return 0;
1196 }
1197
1198 static struct undef_hook ssbs_emulation_hook = {
1199         .instr_mask     = ~(1U << PSTATE_Imm_shift),
1200         .instr_val      = 0xd500401f | PSTATE_SSBS,
1201         .fn             = ssbs_emulation_handler,
1202 };
1203
1204 static void cpu_enable_ssbs(const struct arm64_cpu_capabilities *__unused)
1205 {
1206         static bool undef_hook_registered = false;
1207         static DEFINE_RAW_SPINLOCK(hook_lock);
1208
1209         raw_spin_lock(&hook_lock);
1210         if (!undef_hook_registered) {
1211                 register_undef_hook(&ssbs_emulation_hook);
1212                 undef_hook_registered = true;
1213         }
1214         raw_spin_unlock(&hook_lock);
1215
1216         if (arm64_get_ssbd_state() == ARM64_SSBD_FORCE_DISABLE) {
1217                 sysreg_clear_set(sctlr_el1, 0, SCTLR_ELx_DSSBS);
1218                 arm64_set_ssbd_mitigation(false);
1219         } else {
1220                 arm64_set_ssbd_mitigation(true);
1221         }
1222 }
1223 #endif /* CONFIG_ARM64_SSBD */
1224
1225 #ifdef CONFIG_ARM64_PAN
1226 static void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused)
1227 {
1228         /*
1229          * We modify PSTATE. This won't work from irq context as the PSTATE
1230          * is discarded once we return from the exception.
1231          */
1232         WARN_ON_ONCE(in_interrupt());
1233
1234         sysreg_clear_set(sctlr_el1, SCTLR_EL1_SPAN, 0);
1235         asm(SET_PSTATE_PAN(1));
1236 }
1237 #endif /* CONFIG_ARM64_PAN */
1238
1239 #ifdef CONFIG_ARM64_RAS_EXTN
1240 static void cpu_clear_disr(const struct arm64_cpu_capabilities *__unused)
1241 {
1242         /* Firmware may have left a deferred SError in this register. */
1243         write_sysreg_s(0, SYS_DISR_EL1);
1244 }
1245 #endif /* CONFIG_ARM64_RAS_EXTN */
1246
1247 #ifdef CONFIG_ARM64_PTR_AUTH
1248 static void cpu_enable_address_auth(struct arm64_cpu_capabilities const *cap)
1249 {
1250         sysreg_clear_set(sctlr_el1, 0, SCTLR_ELx_ENIA | SCTLR_ELx_ENIB |
1251                                        SCTLR_ELx_ENDA | SCTLR_ELx_ENDB);
1252 }
1253 #endif /* CONFIG_ARM64_PTR_AUTH */
1254
1255 #ifdef CONFIG_ARM64_PSEUDO_NMI
1256 static bool enable_pseudo_nmi;
1257
1258 static int __init early_enable_pseudo_nmi(char *p)
1259 {
1260         return strtobool(p, &enable_pseudo_nmi);
1261 }
1262 early_param("irqchip.gicv3_pseudo_nmi", early_enable_pseudo_nmi);
1263
1264 static bool can_use_gic_priorities(const struct arm64_cpu_capabilities *entry,
1265                                    int scope)
1266 {
1267         return enable_pseudo_nmi && has_useable_gicv3_cpuif(entry, scope);
1268 }
1269 #endif
1270
1271 static const struct arm64_cpu_capabilities arm64_features[] = {
1272         {
1273                 .desc = "GIC system register CPU interface",
1274                 .capability = ARM64_HAS_SYSREG_GIC_CPUIF,
1275                 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
1276                 .matches = has_useable_gicv3_cpuif,
1277                 .sys_reg = SYS_ID_AA64PFR0_EL1,
1278                 .field_pos = ID_AA64PFR0_GIC_SHIFT,
1279                 .sign = FTR_UNSIGNED,
1280                 .min_field_value = 1,
1281         },
1282 #ifdef CONFIG_ARM64_PAN
1283         {
1284                 .desc = "Privileged Access Never",
1285                 .capability = ARM64_HAS_PAN,
1286                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1287                 .matches = has_cpuid_feature,
1288                 .sys_reg = SYS_ID_AA64MMFR1_EL1,
1289                 .field_pos = ID_AA64MMFR1_PAN_SHIFT,
1290                 .sign = FTR_UNSIGNED,
1291                 .min_field_value = 1,
1292                 .cpu_enable = cpu_enable_pan,
1293         },
1294 #endif /* CONFIG_ARM64_PAN */
1295 #if defined(CONFIG_AS_LSE) && defined(CONFIG_ARM64_LSE_ATOMICS)
1296         {
1297                 .desc = "LSE atomic instructions",
1298                 .capability = ARM64_HAS_LSE_ATOMICS,
1299                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1300                 .matches = has_cpuid_feature,
1301                 .sys_reg = SYS_ID_AA64ISAR0_EL1,
1302                 .field_pos = ID_AA64ISAR0_ATOMICS_SHIFT,
1303                 .sign = FTR_UNSIGNED,
1304                 .min_field_value = 2,
1305         },
1306 #endif /* CONFIG_AS_LSE && CONFIG_ARM64_LSE_ATOMICS */
1307         {
1308                 .desc = "Software prefetching using PRFM",
1309                 .capability = ARM64_HAS_NO_HW_PREFETCH,
1310                 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
1311                 .matches = has_no_hw_prefetch,
1312         },
1313 #ifdef CONFIG_ARM64_UAO
1314         {
1315                 .desc = "User Access Override",
1316                 .capability = ARM64_HAS_UAO,
1317                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1318                 .matches = has_cpuid_feature,
1319                 .sys_reg = SYS_ID_AA64MMFR2_EL1,
1320                 .field_pos = ID_AA64MMFR2_UAO_SHIFT,
1321                 .min_field_value = 1,
1322                 /*
1323                  * We rely on stop_machine() calling uao_thread_switch() to set
1324                  * UAO immediately after patching.
1325                  */
1326         },
1327 #endif /* CONFIG_ARM64_UAO */
1328 #ifdef CONFIG_ARM64_PAN
1329         {
1330                 .capability = ARM64_ALT_PAN_NOT_UAO,
1331                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1332                 .matches = cpufeature_pan_not_uao,
1333         },
1334 #endif /* CONFIG_ARM64_PAN */
1335 #ifdef CONFIG_ARM64_VHE
1336         {
1337                 .desc = "Virtualization Host Extensions",
1338                 .capability = ARM64_HAS_VIRT_HOST_EXTN,
1339                 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
1340                 .matches = runs_at_el2,
1341                 .cpu_enable = cpu_copy_el2regs,
1342         },
1343 #endif  /* CONFIG_ARM64_VHE */
1344         {
1345                 .desc = "32-bit EL0 Support",
1346                 .capability = ARM64_HAS_32BIT_EL0,
1347                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1348                 .matches = has_cpuid_feature,
1349                 .sys_reg = SYS_ID_AA64PFR0_EL1,
1350                 .sign = FTR_UNSIGNED,
1351                 .field_pos = ID_AA64PFR0_EL0_SHIFT,
1352                 .min_field_value = ID_AA64PFR0_EL0_32BIT_64BIT,
1353         },
1354         {
1355                 .desc = "Kernel page table isolation (KPTI)",
1356                 .capability = ARM64_UNMAP_KERNEL_AT_EL0,
1357                 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE,
1358                 /*
1359                  * The ID feature fields below are used to indicate that
1360                  * the CPU doesn't need KPTI. See unmap_kernel_at_el0 for
1361                  * more details.
1362                  */
1363                 .sys_reg = SYS_ID_AA64PFR0_EL1,
1364                 .field_pos = ID_AA64PFR0_CSV3_SHIFT,
1365                 .min_field_value = 1,
1366                 .matches = unmap_kernel_at_el0,
1367                 .cpu_enable = kpti_install_ng_mappings,
1368         },
1369         {
1370                 /* FP/SIMD is not implemented */
1371                 .capability = ARM64_HAS_NO_FPSIMD,
1372                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1373                 .min_field_value = 0,
1374                 .matches = has_no_fpsimd,
1375         },
1376 #ifdef CONFIG_ARM64_PMEM
1377         {
1378                 .desc = "Data cache clean to Point of Persistence",
1379                 .capability = ARM64_HAS_DCPOP,
1380                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1381                 .matches = has_cpuid_feature,
1382                 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1383                 .field_pos = ID_AA64ISAR1_DPB_SHIFT,
1384                 .min_field_value = 1,
1385         },
1386         {
1387                 .desc = "Data cache clean to Point of Deep Persistence",
1388                 .capability = ARM64_HAS_DCPODP,
1389                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1390                 .matches = has_cpuid_feature,
1391                 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1392                 .sign = FTR_UNSIGNED,
1393                 .field_pos = ID_AA64ISAR1_DPB_SHIFT,
1394                 .min_field_value = 2,
1395         },
1396 #endif
1397 #ifdef CONFIG_ARM64_SVE
1398         {
1399                 .desc = "Scalable Vector Extension",
1400                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1401                 .capability = ARM64_SVE,
1402                 .sys_reg = SYS_ID_AA64PFR0_EL1,
1403                 .sign = FTR_UNSIGNED,
1404                 .field_pos = ID_AA64PFR0_SVE_SHIFT,
1405                 .min_field_value = ID_AA64PFR0_SVE,
1406                 .matches = has_cpuid_feature,
1407                 .cpu_enable = sve_kernel_enable,
1408         },
1409 #endif /* CONFIG_ARM64_SVE */
1410 #ifdef CONFIG_ARM64_RAS_EXTN
1411         {
1412                 .desc = "RAS Extension Support",
1413                 .capability = ARM64_HAS_RAS_EXTN,
1414                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1415                 .matches = has_cpuid_feature,
1416                 .sys_reg = SYS_ID_AA64PFR0_EL1,
1417                 .sign = FTR_UNSIGNED,
1418                 .field_pos = ID_AA64PFR0_RAS_SHIFT,
1419                 .min_field_value = ID_AA64PFR0_RAS_V1,
1420                 .cpu_enable = cpu_clear_disr,
1421         },
1422 #endif /* CONFIG_ARM64_RAS_EXTN */
1423         {
1424                 .desc = "Data cache clean to the PoU not required for I/D coherence",
1425                 .capability = ARM64_HAS_CACHE_IDC,
1426                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1427                 .matches = has_cache_idc,
1428                 .cpu_enable = cpu_emulate_effective_ctr,
1429         },
1430         {
1431                 .desc = "Instruction cache invalidation not required for I/D coherence",
1432                 .capability = ARM64_HAS_CACHE_DIC,
1433                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1434                 .matches = has_cache_dic,
1435         },
1436         {
1437                 .desc = "Stage-2 Force Write-Back",
1438                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1439                 .capability = ARM64_HAS_STAGE2_FWB,
1440                 .sys_reg = SYS_ID_AA64MMFR2_EL1,
1441                 .sign = FTR_UNSIGNED,
1442                 .field_pos = ID_AA64MMFR2_FWB_SHIFT,
1443                 .min_field_value = 1,
1444                 .matches = has_cpuid_feature,
1445                 .cpu_enable = cpu_has_fwb,
1446         },
1447 #ifdef CONFIG_ARM64_HW_AFDBM
1448         {
1449                 /*
1450                  * Since we turn this on always, we don't want the user to
1451                  * think that the feature is available when it may not be.
1452                  * So hide the description.
1453                  *
1454                  * .desc = "Hardware pagetable Dirty Bit Management",
1455                  *
1456                  */
1457                 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
1458                 .capability = ARM64_HW_DBM,
1459                 .sys_reg = SYS_ID_AA64MMFR1_EL1,
1460                 .sign = FTR_UNSIGNED,
1461                 .field_pos = ID_AA64MMFR1_HADBS_SHIFT,
1462                 .min_field_value = 2,
1463                 .matches = has_hw_dbm,
1464                 .cpu_enable = cpu_enable_hw_dbm,
1465         },
1466 #endif
1467         {
1468                 .desc = "CRC32 instructions",
1469                 .capability = ARM64_HAS_CRC32,
1470                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1471                 .matches = has_cpuid_feature,
1472                 .sys_reg = SYS_ID_AA64ISAR0_EL1,
1473                 .field_pos = ID_AA64ISAR0_CRC32_SHIFT,
1474                 .min_field_value = 1,
1475         },
1476 #ifdef CONFIG_ARM64_SSBD
1477         {
1478                 .desc = "Speculative Store Bypassing Safe (SSBS)",
1479                 .capability = ARM64_SSBS,
1480                 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
1481                 .matches = has_cpuid_feature,
1482                 .sys_reg = SYS_ID_AA64PFR1_EL1,
1483                 .field_pos = ID_AA64PFR1_SSBS_SHIFT,
1484                 .sign = FTR_UNSIGNED,
1485                 .min_field_value = ID_AA64PFR1_SSBS_PSTATE_ONLY,
1486                 .cpu_enable = cpu_enable_ssbs,
1487         },
1488 #endif
1489 #ifdef CONFIG_ARM64_CNP
1490         {
1491                 .desc = "Common not Private translations",
1492                 .capability = ARM64_HAS_CNP,
1493                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1494                 .matches = has_useable_cnp,
1495                 .sys_reg = SYS_ID_AA64MMFR2_EL1,
1496                 .sign = FTR_UNSIGNED,
1497                 .field_pos = ID_AA64MMFR2_CNP_SHIFT,
1498                 .min_field_value = 1,
1499                 .cpu_enable = cpu_enable_cnp,
1500         },
1501 #endif
1502         {
1503                 .desc = "Speculation barrier (SB)",
1504                 .capability = ARM64_HAS_SB,
1505                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1506                 .matches = has_cpuid_feature,
1507                 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1508                 .field_pos = ID_AA64ISAR1_SB_SHIFT,
1509                 .sign = FTR_UNSIGNED,
1510                 .min_field_value = 1,
1511         },
1512 #ifdef CONFIG_ARM64_PTR_AUTH
1513         {
1514                 .desc = "Address authentication (architected algorithm)",
1515                 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH,
1516                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1517                 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1518                 .sign = FTR_UNSIGNED,
1519                 .field_pos = ID_AA64ISAR1_APA_SHIFT,
1520                 .min_field_value = ID_AA64ISAR1_APA_ARCHITECTED,
1521                 .matches = has_cpuid_feature,
1522                 .cpu_enable = cpu_enable_address_auth,
1523         },
1524         {
1525                 .desc = "Address authentication (IMP DEF algorithm)",
1526                 .capability = ARM64_HAS_ADDRESS_AUTH_IMP_DEF,
1527                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1528                 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1529                 .sign = FTR_UNSIGNED,
1530                 .field_pos = ID_AA64ISAR1_API_SHIFT,
1531                 .min_field_value = ID_AA64ISAR1_API_IMP_DEF,
1532                 .matches = has_cpuid_feature,
1533                 .cpu_enable = cpu_enable_address_auth,
1534         },
1535         {
1536                 .desc = "Generic authentication (architected algorithm)",
1537                 .capability = ARM64_HAS_GENERIC_AUTH_ARCH,
1538                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1539                 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1540                 .sign = FTR_UNSIGNED,
1541                 .field_pos = ID_AA64ISAR1_GPA_SHIFT,
1542                 .min_field_value = ID_AA64ISAR1_GPA_ARCHITECTED,
1543                 .matches = has_cpuid_feature,
1544         },
1545         {
1546                 .desc = "Generic authentication (IMP DEF algorithm)",
1547                 .capability = ARM64_HAS_GENERIC_AUTH_IMP_DEF,
1548                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1549                 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1550                 .sign = FTR_UNSIGNED,
1551                 .field_pos = ID_AA64ISAR1_GPI_SHIFT,
1552                 .min_field_value = ID_AA64ISAR1_GPI_IMP_DEF,
1553                 .matches = has_cpuid_feature,
1554         },
1555 #endif /* CONFIG_ARM64_PTR_AUTH */
1556 #ifdef CONFIG_ARM64_PSEUDO_NMI
1557         {
1558                 /*
1559                  * Depends on having GICv3
1560                  */
1561                 .desc = "IRQ priority masking",
1562                 .capability = ARM64_HAS_IRQ_PRIO_MASKING,
1563                 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
1564                 .matches = can_use_gic_priorities,
1565                 .sys_reg = SYS_ID_AA64PFR0_EL1,
1566                 .field_pos = ID_AA64PFR0_GIC_SHIFT,
1567                 .sign = FTR_UNSIGNED,
1568                 .min_field_value = 1,
1569         },
1570 #endif
1571 #ifdef CONFIG_ARCH_RANDOM
1572         {
1573                 .desc = "Random Number Generator",
1574                 .capability = ARM64_HAS_RNG,
1575                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1576                 .matches = has_cpuid_feature,
1577                 .sys_reg = SYS_ID_AA64ISAR0_EL1,
1578                 .field_pos = ID_AA64ISAR0_RNDR_SHIFT,
1579                 .sign = FTR_UNSIGNED,
1580                 .min_field_value = 1,
1581         },
1582 #endif
1583         {},
1584 };
1585
1586 #define HWCAP_CPUID_MATCH(reg, field, s, min_value)                             \
1587                 .matches = has_cpuid_feature,                                   \
1588                 .sys_reg = reg,                                                 \
1589                 .field_pos = field,                                             \
1590                 .sign = s,                                                      \
1591                 .min_field_value = min_value,
1592
1593 #define __HWCAP_CAP(name, cap_type, cap)                                        \
1594                 .desc = name,                                                   \
1595                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,                            \
1596                 .hwcap_type = cap_type,                                         \
1597                 .hwcap = cap,                                                   \
1598
1599 #define HWCAP_CAP(reg, field, s, min_value, cap_type, cap)                      \
1600         {                                                                       \
1601                 __HWCAP_CAP(#cap, cap_type, cap)                                \
1602                 HWCAP_CPUID_MATCH(reg, field, s, min_value)                     \
1603         }
1604
1605 #define HWCAP_MULTI_CAP(list, cap_type, cap)                                    \
1606         {                                                                       \
1607                 __HWCAP_CAP(#cap, cap_type, cap)                                \
1608                 .matches = cpucap_multi_entry_cap_matches,                      \
1609                 .match_list = list,                                             \
1610         }
1611
1612 #ifdef CONFIG_ARM64_PTR_AUTH
1613 static const struct arm64_cpu_capabilities ptr_auth_hwcap_addr_matches[] = {
1614         {
1615                 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_APA_SHIFT,
1616                                   FTR_UNSIGNED, ID_AA64ISAR1_APA_ARCHITECTED)
1617         },
1618         {
1619                 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_API_SHIFT,
1620                                   FTR_UNSIGNED, ID_AA64ISAR1_API_IMP_DEF)
1621         },
1622         {},
1623 };
1624
1625 static const struct arm64_cpu_capabilities ptr_auth_hwcap_gen_matches[] = {
1626         {
1627                 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_GPA_SHIFT,
1628                                   FTR_UNSIGNED, ID_AA64ISAR1_GPA_ARCHITECTED)
1629         },
1630         {
1631                 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_GPI_SHIFT,
1632                                   FTR_UNSIGNED, ID_AA64ISAR1_GPI_IMP_DEF)
1633         },
1634         {},
1635 };
1636 #endif
1637
1638 static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
1639         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_PMULL),
1640         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_AES),
1641         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA1),
1642         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA2),
1643         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_SHA512),
1644         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_CRC32),
1645         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_ATOMICS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ATOMICS),
1646         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_RDM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDRDM),
1647         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA3),
1648         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM3),
1649         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM4_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM4),
1650         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_DP_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDDP),
1651         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_FHM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDFHM),
1652         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_TS_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FLAGM),
1653         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_TS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_FLAGM2),
1654         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_RNDR_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_RNG),
1655         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_FP),
1656         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FPHP),
1657         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_ASIMD),
1658         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDHP),
1659         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_DIT_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DIT),
1660         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DCPOP),
1661         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_DCPODP),
1662         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_JSCVT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_JSCVT),
1663         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FCMA_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FCMA),
1664         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_LRCPC),
1665         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ILRCPC),
1666         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FRINTTS_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FRINT),
1667         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_SB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SB),
1668         HWCAP_CAP(SYS_ID_AA64MMFR2_EL1, ID_AA64MMFR2_AT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_USCAT),
1669 #ifdef CONFIG_ARM64_SVE
1670         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_SVE_SHIFT, FTR_UNSIGNED, ID_AA64PFR0_SVE, CAP_HWCAP, KERNEL_HWCAP_SVE),
1671         HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SVEVER_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SVEVER_SVE2, CAP_HWCAP, KERNEL_HWCAP_SVE2),
1672         HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_AES_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_AES, CAP_HWCAP, KERNEL_HWCAP_SVEAES),
1673         HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_AES_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_AES_PMULL, CAP_HWCAP, KERNEL_HWCAP_SVEPMULL),
1674         HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_BITPERM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_BITPERM, CAP_HWCAP, KERNEL_HWCAP_SVEBITPERM),
1675         HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SHA3_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SHA3, CAP_HWCAP, KERNEL_HWCAP_SVESHA3),
1676         HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SM4_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SM4, CAP_HWCAP, KERNEL_HWCAP_SVESM4),
1677 #endif
1678         HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_SSBS_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_SSBS_PSTATE_INSNS, CAP_HWCAP, KERNEL_HWCAP_SSBS),
1679 #ifdef CONFIG_ARM64_PTR_AUTH
1680         HWCAP_MULTI_CAP(ptr_auth_hwcap_addr_matches, CAP_HWCAP, KERNEL_HWCAP_PACA),
1681         HWCAP_MULTI_CAP(ptr_auth_hwcap_gen_matches, CAP_HWCAP, KERNEL_HWCAP_PACG),
1682 #endif
1683         {},
1684 };
1685
1686 static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = {
1687 #ifdef CONFIG_COMPAT
1688         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL),
1689         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES),
1690         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1),
1691         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2),
1692         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32),
1693 #endif
1694         {},
1695 };
1696
1697 static void __init cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap)
1698 {
1699         switch (cap->hwcap_type) {
1700         case CAP_HWCAP:
1701                 cpu_set_feature(cap->hwcap);
1702                 break;
1703 #ifdef CONFIG_COMPAT
1704         case CAP_COMPAT_HWCAP:
1705                 compat_elf_hwcap |= (u32)cap->hwcap;
1706                 break;
1707         case CAP_COMPAT_HWCAP2:
1708                 compat_elf_hwcap2 |= (u32)cap->hwcap;
1709                 break;
1710 #endif
1711         default:
1712                 WARN_ON(1);
1713                 break;
1714         }
1715 }
1716
1717 /* Check if we have a particular HWCAP enabled */
1718 static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap)
1719 {
1720         bool rc;
1721
1722         switch (cap->hwcap_type) {
1723         case CAP_HWCAP:
1724                 rc = cpu_have_feature(cap->hwcap);
1725                 break;
1726 #ifdef CONFIG_COMPAT
1727         case CAP_COMPAT_HWCAP:
1728                 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0;
1729                 break;
1730         case CAP_COMPAT_HWCAP2:
1731                 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0;
1732                 break;
1733 #endif
1734         default:
1735                 WARN_ON(1);
1736                 rc = false;
1737         }
1738
1739         return rc;
1740 }
1741
1742 static void __init setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps)
1743 {
1744         /* We support emulation of accesses to CPU ID feature registers */
1745         cpu_set_named_feature(CPUID);
1746         for (; hwcaps->matches; hwcaps++)
1747                 if (hwcaps->matches(hwcaps, cpucap_default_scope(hwcaps)))
1748                         cap_set_elf_hwcap(hwcaps);
1749 }
1750
1751 static void update_cpu_capabilities(u16 scope_mask)
1752 {
1753         int i;
1754         const struct arm64_cpu_capabilities *caps;
1755
1756         scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
1757         for (i = 0; i < ARM64_NCAPS; i++) {
1758                 caps = cpu_hwcaps_ptrs[i];
1759                 if (!caps || !(caps->type & scope_mask) ||
1760                     cpus_have_cap(caps->capability) ||
1761                     !caps->matches(caps, cpucap_default_scope(caps)))
1762                         continue;
1763
1764                 if (caps->desc)
1765                         pr_info("detected: %s\n", caps->desc);
1766                 cpus_set_cap(caps->capability);
1767
1768                 if ((scope_mask & SCOPE_BOOT_CPU) && (caps->type & SCOPE_BOOT_CPU))
1769                         set_bit(caps->capability, boot_capabilities);
1770         }
1771 }
1772
1773 /*
1774  * Enable all the available capabilities on this CPU. The capabilities
1775  * with BOOT_CPU scope are handled separately and hence skipped here.
1776  */
1777 static int cpu_enable_non_boot_scope_capabilities(void *__unused)
1778 {
1779         int i;
1780         u16 non_boot_scope = SCOPE_ALL & ~SCOPE_BOOT_CPU;
1781
1782         for_each_available_cap(i) {
1783                 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[i];
1784
1785                 if (WARN_ON(!cap))
1786                         continue;
1787
1788                 if (!(cap->type & non_boot_scope))
1789                         continue;
1790
1791                 if (cap->cpu_enable)
1792                         cap->cpu_enable(cap);
1793         }
1794         return 0;
1795 }
1796
1797 /*
1798  * Run through the enabled capabilities and enable() it on all active
1799  * CPUs
1800  */
1801 static void __init enable_cpu_capabilities(u16 scope_mask)
1802 {
1803         int i;
1804         const struct arm64_cpu_capabilities *caps;
1805         bool boot_scope;
1806
1807         scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
1808         boot_scope = !!(scope_mask & SCOPE_BOOT_CPU);
1809
1810         for (i = 0; i < ARM64_NCAPS; i++) {
1811                 unsigned int num;
1812
1813                 caps = cpu_hwcaps_ptrs[i];
1814                 if (!caps || !(caps->type & scope_mask))
1815                         continue;
1816                 num = caps->capability;
1817                 if (!cpus_have_cap(num))
1818                         continue;
1819
1820                 /* Ensure cpus_have_const_cap(num) works */
1821                 static_branch_enable(&cpu_hwcap_keys[num]);
1822
1823                 if (boot_scope && caps->cpu_enable)
1824                         /*
1825                          * Capabilities with SCOPE_BOOT_CPU scope are finalised
1826                          * before any secondary CPU boots. Thus, each secondary
1827                          * will enable the capability as appropriate via
1828                          * check_local_cpu_capabilities(). The only exception is
1829                          * the boot CPU, for which the capability must be
1830                          * enabled here. This approach avoids costly
1831                          * stop_machine() calls for this case.
1832                          */
1833                         caps->cpu_enable(caps);
1834         }
1835
1836         /*
1837          * For all non-boot scope capabilities, use stop_machine()
1838          * as it schedules the work allowing us to modify PSTATE,
1839          * instead of on_each_cpu() which uses an IPI, giving us a
1840          * PSTATE that disappears when we return.
1841          */
1842         if (!boot_scope)
1843                 stop_machine(cpu_enable_non_boot_scope_capabilities,
1844                              NULL, cpu_online_mask);
1845 }
1846
1847 /*
1848  * Run through the list of capabilities to check for conflicts.
1849  * If the system has already detected a capability, take necessary
1850  * action on this CPU.
1851  *
1852  * Returns "false" on conflicts.
1853  */
1854 static bool verify_local_cpu_caps(u16 scope_mask)
1855 {
1856         int i;
1857         bool cpu_has_cap, system_has_cap;
1858         const struct arm64_cpu_capabilities *caps;
1859
1860         scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
1861
1862         for (i = 0; i < ARM64_NCAPS; i++) {
1863                 caps = cpu_hwcaps_ptrs[i];
1864                 if (!caps || !(caps->type & scope_mask))
1865                         continue;
1866
1867                 cpu_has_cap = caps->matches(caps, SCOPE_LOCAL_CPU);
1868                 system_has_cap = cpus_have_cap(caps->capability);
1869
1870                 if (system_has_cap) {
1871                         /*
1872                          * Check if the new CPU misses an advertised feature,
1873                          * which is not safe to miss.
1874                          */
1875                         if (!cpu_has_cap && !cpucap_late_cpu_optional(caps))
1876                                 break;
1877                         /*
1878                          * We have to issue cpu_enable() irrespective of
1879                          * whether the CPU has it or not, as it is enabeld
1880                          * system wide. It is upto the call back to take
1881                          * appropriate action on this CPU.
1882                          */
1883                         if (caps->cpu_enable)
1884                                 caps->cpu_enable(caps);
1885                 } else {
1886                         /*
1887                          * Check if the CPU has this capability if it isn't
1888                          * safe to have when the system doesn't.
1889                          */
1890                         if (cpu_has_cap && !cpucap_late_cpu_permitted(caps))
1891                                 break;
1892                 }
1893         }
1894
1895         if (i < ARM64_NCAPS) {
1896                 pr_crit("CPU%d: Detected conflict for capability %d (%s), System: %d, CPU: %d\n",
1897                         smp_processor_id(), caps->capability,
1898                         caps->desc, system_has_cap, cpu_has_cap);
1899                 return false;
1900         }
1901
1902         return true;
1903 }
1904
1905 /*
1906  * Check for CPU features that are used in early boot
1907  * based on the Boot CPU value.
1908  */
1909 static void check_early_cpu_features(void)
1910 {
1911         verify_cpu_asid_bits();
1912         /*
1913          * Early features are used by the kernel already. If there
1914          * is a conflict, we cannot proceed further.
1915          */
1916         if (!verify_local_cpu_caps(SCOPE_BOOT_CPU))
1917                 cpu_panic_kernel();
1918 }
1919
1920 static void
1921 verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps)
1922 {
1923
1924         for (; caps->matches; caps++)
1925                 if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) {
1926                         pr_crit("CPU%d: missing HWCAP: %s\n",
1927                                         smp_processor_id(), caps->desc);
1928                         cpu_die_early();
1929                 }
1930 }
1931
1932 static void verify_sve_features(void)
1933 {
1934         u64 safe_zcr = read_sanitised_ftr_reg(SYS_ZCR_EL1);
1935         u64 zcr = read_zcr_features();
1936
1937         unsigned int safe_len = safe_zcr & ZCR_ELx_LEN_MASK;
1938         unsigned int len = zcr & ZCR_ELx_LEN_MASK;
1939
1940         if (len < safe_len || sve_verify_vq_map()) {
1941                 pr_crit("CPU%d: SVE: vector length support mismatch\n",
1942                         smp_processor_id());
1943                 cpu_die_early();
1944         }
1945
1946         /* Add checks on other ZCR bits here if necessary */
1947 }
1948
1949
1950 /*
1951  * Run through the enabled system capabilities and enable() it on this CPU.
1952  * The capabilities were decided based on the available CPUs at the boot time.
1953  * Any new CPU should match the system wide status of the capability. If the
1954  * new CPU doesn't have a capability which the system now has enabled, we
1955  * cannot do anything to fix it up and could cause unexpected failures. So
1956  * we park the CPU.
1957  */
1958 static void verify_local_cpu_capabilities(void)
1959 {
1960         /*
1961          * The capabilities with SCOPE_BOOT_CPU are checked from
1962          * check_early_cpu_features(), as they need to be verified
1963          * on all secondary CPUs.
1964          */
1965         if (!verify_local_cpu_caps(SCOPE_ALL & ~SCOPE_BOOT_CPU))
1966                 cpu_die_early();
1967
1968         verify_local_elf_hwcaps(arm64_elf_hwcaps);
1969
1970         if (system_supports_32bit_el0())
1971                 verify_local_elf_hwcaps(compat_elf_hwcaps);
1972
1973         if (system_supports_sve())
1974                 verify_sve_features();
1975 }
1976
1977 void check_local_cpu_capabilities(void)
1978 {
1979         /*
1980          * All secondary CPUs should conform to the early CPU features
1981          * in use by the kernel based on boot CPU.
1982          */
1983         check_early_cpu_features();
1984
1985         /*
1986          * If we haven't finalised the system capabilities, this CPU gets
1987          * a chance to update the errata work arounds and local features.
1988          * Otherwise, this CPU should verify that it has all the system
1989          * advertised capabilities.
1990          */
1991         if (!sys_caps_initialised)
1992                 update_cpu_capabilities(SCOPE_LOCAL_CPU);
1993         else
1994                 verify_local_cpu_capabilities();
1995 }
1996
1997 static void __init setup_boot_cpu_capabilities(void)
1998 {
1999         /* Detect capabilities with either SCOPE_BOOT_CPU or SCOPE_LOCAL_CPU */
2000         update_cpu_capabilities(SCOPE_BOOT_CPU | SCOPE_LOCAL_CPU);
2001         /* Enable the SCOPE_BOOT_CPU capabilities alone right away */
2002         enable_cpu_capabilities(SCOPE_BOOT_CPU);
2003 }
2004
2005 DEFINE_STATIC_KEY_FALSE(arm64_const_caps_ready);
2006 EXPORT_SYMBOL(arm64_const_caps_ready);
2007
2008 static void __init mark_const_caps_ready(void)
2009 {
2010         static_branch_enable(&arm64_const_caps_ready);
2011 }
2012
2013 bool this_cpu_has_cap(unsigned int n)
2014 {
2015         if (!WARN_ON(preemptible()) && n < ARM64_NCAPS) {
2016                 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[n];
2017
2018                 if (cap)
2019                         return cap->matches(cap, SCOPE_LOCAL_CPU);
2020         }
2021
2022         return false;
2023 }
2024
2025 void cpu_set_feature(unsigned int num)
2026 {
2027         WARN_ON(num >= MAX_CPU_FEATURES);
2028         elf_hwcap |= BIT(num);
2029 }
2030 EXPORT_SYMBOL_GPL(cpu_set_feature);
2031
2032 bool cpu_have_feature(unsigned int num)
2033 {
2034         WARN_ON(num >= MAX_CPU_FEATURES);
2035         return elf_hwcap & BIT(num);
2036 }
2037 EXPORT_SYMBOL_GPL(cpu_have_feature);
2038
2039 unsigned long cpu_get_elf_hwcap(void)
2040 {
2041         /*
2042          * We currently only populate the first 32 bits of AT_HWCAP. Please
2043          * note that for userspace compatibility we guarantee that bits 62
2044          * and 63 will always be returned as 0.
2045          */
2046         return lower_32_bits(elf_hwcap);
2047 }
2048
2049 unsigned long cpu_get_elf_hwcap2(void)
2050 {
2051         return upper_32_bits(elf_hwcap);
2052 }
2053
2054 static void __init setup_system_capabilities(void)
2055 {
2056         /*
2057          * We have finalised the system-wide safe feature
2058          * registers, finalise the capabilities that depend
2059          * on it. Also enable all the available capabilities,
2060          * that are not enabled already.
2061          */
2062         update_cpu_capabilities(SCOPE_SYSTEM);
2063         enable_cpu_capabilities(SCOPE_ALL & ~SCOPE_BOOT_CPU);
2064 }
2065
2066 void __init setup_cpu_features(void)
2067 {
2068         u32 cwg;
2069
2070         setup_system_capabilities();
2071         mark_const_caps_ready();
2072         setup_elf_hwcaps(arm64_elf_hwcaps);
2073
2074         if (system_supports_32bit_el0())
2075                 setup_elf_hwcaps(compat_elf_hwcaps);
2076
2077         if (system_uses_ttbr0_pan())
2078                 pr_info("emulated: Privileged Access Never (PAN) using TTBR0_EL1 switching\n");
2079
2080         sve_setup();
2081         minsigstksz_setup();
2082
2083         /* Advertise that we have computed the system capabilities */
2084         set_sys_caps_initialised();
2085
2086         /*
2087          * Check for sane CTR_EL0.CWG value.
2088          */
2089         cwg = cache_type_cwg();
2090         if (!cwg)
2091                 pr_warn("No Cache Writeback Granule information, assuming %d\n",
2092                         ARCH_DMA_MINALIGN);
2093 }
2094
2095 static bool __maybe_unused
2096 cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused)
2097 {
2098         return (cpus_have_const_cap(ARM64_HAS_PAN) && !cpus_have_const_cap(ARM64_HAS_UAO));
2099 }
2100
2101 static void __maybe_unused cpu_enable_cnp(struct arm64_cpu_capabilities const *cap)
2102 {
2103         cpu_replace_ttbr1(lm_alias(swapper_pg_dir));
2104 }
2105
2106 /*
2107  * We emulate only the following system register space.
2108  * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 4 - 7]
2109  * See Table C5-6 System instruction encodings for System register accesses,
2110  * ARMv8 ARM(ARM DDI 0487A.f) for more details.
2111  */
2112 static inline bool __attribute_const__ is_emulated(u32 id)
2113 {
2114         return (sys_reg_Op0(id) == 0x3 &&
2115                 sys_reg_CRn(id) == 0x0 &&
2116                 sys_reg_Op1(id) == 0x0 &&
2117                 (sys_reg_CRm(id) == 0 ||
2118                  ((sys_reg_CRm(id) >= 4) && (sys_reg_CRm(id) <= 7))));
2119 }
2120
2121 /*
2122  * With CRm == 0, reg should be one of :
2123  * MIDR_EL1, MPIDR_EL1 or REVIDR_EL1.
2124  */
2125 static inline int emulate_id_reg(u32 id, u64 *valp)
2126 {
2127         switch (id) {
2128         case SYS_MIDR_EL1:
2129                 *valp = read_cpuid_id();
2130                 break;
2131         case SYS_MPIDR_EL1:
2132                 *valp = SYS_MPIDR_SAFE_VAL;
2133                 break;
2134         case SYS_REVIDR_EL1:
2135                 /* IMPLEMENTATION DEFINED values are emulated with 0 */
2136                 *valp = 0;
2137                 break;
2138         default:
2139                 return -EINVAL;
2140         }
2141
2142         return 0;
2143 }
2144
2145 static int emulate_sys_reg(u32 id, u64 *valp)
2146 {
2147         struct arm64_ftr_reg *regp;
2148
2149         if (!is_emulated(id))
2150                 return -EINVAL;
2151
2152         if (sys_reg_CRm(id) == 0)
2153                 return emulate_id_reg(id, valp);
2154
2155         regp = get_arm64_ftr_reg(id);
2156         if (regp)
2157                 *valp = arm64_ftr_reg_user_value(regp);
2158         else
2159                 /*
2160                  * The untracked registers are either IMPLEMENTATION DEFINED
2161                  * (e.g, ID_AFR0_EL1) or reserved RAZ.
2162                  */
2163                 *valp = 0;
2164         return 0;
2165 }
2166
2167 int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt)
2168 {
2169         int rc;
2170         u64 val;
2171
2172         rc = emulate_sys_reg(sys_reg, &val);
2173         if (!rc) {
2174                 pt_regs_write_reg(regs, rt, val);
2175                 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
2176         }
2177         return rc;
2178 }
2179
2180 static int emulate_mrs(struct pt_regs *regs, u32 insn)
2181 {
2182         u32 sys_reg, rt;
2183
2184         /*
2185          * sys_reg values are defined as used in mrs/msr instruction.
2186          * shift the imm value to get the encoding.
2187          */
2188         sys_reg = (u32)aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16, insn) << 5;
2189         rt = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn);
2190         return do_emulate_mrs(regs, sys_reg, rt);
2191 }
2192
2193 static struct undef_hook mrs_hook = {
2194         .instr_mask = 0xfff00000,
2195         .instr_val  = 0xd5300000,
2196         .pstate_mask = PSR_AA32_MODE_MASK,
2197         .pstate_val = PSR_MODE_EL0t,
2198         .fn = emulate_mrs,
2199 };
2200
2201 static int __init enable_mrs_emulation(void)
2202 {
2203         register_undef_hook(&mrs_hook);
2204         return 0;
2205 }
2206
2207 core_initcall(enable_mrs_emulation);
2208
2209 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr,
2210                           char *buf)
2211 {
2212         if (__meltdown_safe)
2213                 return sprintf(buf, "Not affected\n");
2214
2215         if (arm64_kernel_unmapped_at_el0())
2216                 return sprintf(buf, "Mitigation: PTI\n");
2217
2218         return sprintf(buf, "Vulnerable\n");
2219 }