arch/arm64/kernel/cpufeature.c

   1 /*
   2  * Contains CPU feature definitions
   3  *
   4  * Copyright (C) 2015 ARM Ltd.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  17  */
  18
  19 #define pr_fmt(fmt) "CPU features: " fmt
  20
  21 #include <linux/bsearch.h>
  22 #include <linux/cpumask.h>
  23 #include <linux/sort.h>
  24 #include <linux/stop_machine.h>
  25 #include <linux/types.h>
  26 #include <linux/mm.h>
  27 #include <asm/cpu.h>
  28 #include <asm/cpufeature.h>
  29 #include <asm/cpu_ops.h>
  30 #include <asm/mmu_context.h>
  31 #include <asm/processor.h>
  32 #include <asm/sysreg.h>
  33 #include <asm/traps.h>
  34 #include <asm/virt.h>
  35
  36 unsigned long elf_hwcap __read_mostly;
  37 EXPORT_SYMBOL_GPL(elf_hwcap);
  38
  39 #ifdef CONFIG_COMPAT
  40 #define COMPAT_ELF_HWCAP_DEFAULT        \
  41                                 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\
  42                                  COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\
  43                                  COMPAT_HWCAP_TLS|COMPAT_HWCAP_VFP|\
  44                                  COMPAT_HWCAP_VFPv3|COMPAT_HWCAP_VFPv4|\
  45                                  COMPAT_HWCAP_NEON|COMPAT_HWCAP_IDIV|\
  46                                  COMPAT_HWCAP_LPAE)
  47 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT;
  48 unsigned int compat_elf_hwcap2 __read_mostly;
  49 #endif
  50
  51 DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS);
  52 EXPORT_SYMBOL(cpu_hwcaps);
  53
  54 static int dump_cpu_hwcaps(struct notifier_block *self, unsigned long v, void *p)
  55 {
  56         /* file-wide pr_fmt adds "CPU features: " prefix */
  57         pr_emerg("0x%*pb\n", ARM64_NCAPS, &cpu_hwcaps);
  58         return 0;
  59 }
  60
  61 static struct notifier_block cpu_hwcaps_notifier = {
  62         .notifier_call = dump_cpu_hwcaps
  63 };
  64
  65 static int __init register_cpu_hwcaps_dumper(void)
  66 {
  67         atomic_notifier_chain_register(&panic_notifier_list,
  68                                        &cpu_hwcaps_notifier);
  69         return 0;
  70 }
  71 __initcall(register_cpu_hwcaps_dumper);
  72
  73 DEFINE_STATIC_KEY_ARRAY_FALSE(cpu_hwcap_keys, ARM64_NCAPS);
  74 EXPORT_SYMBOL(cpu_hwcap_keys);
  75
  76 #define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
  77         {                                               \
  78                 .sign = SIGNED,                         \
  79                 .visible = VISIBLE,                     \
  80                 .strict = STRICT,                       \
  81                 .type = TYPE,                           \
  82                 .shift = SHIFT,                         \
  83                 .width = WIDTH,                         \
  84                 .safe_val = SAFE_VAL,                   \
  85         }
  86
  87 /* Define a feature with unsigned values */
  88 #define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
  89         __ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
  90
  91 /* Define a feature with a signed value */
  92 #define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
  93         __ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
  94
  95 #define ARM64_FTR_END                                   \
  96         {                                               \
  97                 .width = 0,                             \
  98         }
  99
 100 /* meta feature for alternatives */
 101 static bool __maybe_unused
 102 cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused);
 103
 104
 105 /*
 106  * NOTE: Any changes to the visibility of features should be kept in
 107  * sync with the documentation of the CPU feature register ABI.
 108  */
 109 static const struct arm64_ftr_bits ftr_id_aa64isar0[] = {
 110         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64ISAR0_RDM_SHIFT, 4, 0),
 111         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_ATOMICS_SHIFT, 4, 0),
 112         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_CRC32_SHIFT, 4, 0),
 113         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA2_SHIFT, 4, 0),
 114         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA1_SHIFT, 4, 0),
 115         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_AES_SHIFT, 4, 0),
 116         ARM64_FTR_END,
 117 };
 118
 119 static const struct arm64_ftr_bits ftr_id_aa64isar1[] = {
 120         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_LRCPC_SHIFT, 4, 0),
 121         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_FCMA_SHIFT, 4, 0),
 122         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_JSCVT_SHIFT, 4, 0),
 123         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_DPB_SHIFT, 4, 0),
 124         ARM64_FTR_END,
 125 };
 126
 127 static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = {
 128         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64PFR0_GIC_SHIFT, 4, 0),
 129         S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_ASIMD_SHIFT, 4, ID_AA64PFR0_ASIMD_NI),
 130         S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI),
 131         /* Linux doesn't care about the EL3 */
 132         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64PFR0_EL3_SHIFT, 4, 0),
 133         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64PFR0_EL2_SHIFT, 4, 0),
 134         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64PFR0_EL1_SHIFT, 4, ID_AA64PFR0_EL1_64BIT_ONLY),
 135         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64PFR0_EL0_SHIFT, 4, ID_AA64PFR0_EL0_64BIT_ONLY),
 136         ARM64_FTR_END,
 137 };
 138
 139 static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = {
 140         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN4_SHIFT, 4, ID_AA64MMFR0_TGRAN4_NI),
 141         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN64_SHIFT, 4, ID_AA64MMFR0_TGRAN64_NI),
 142         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN16_SHIFT, 4, ID_AA64MMFR0_TGRAN16_NI),
 143         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_BIGENDEL0_SHIFT, 4, 0),
 144         /* Linux shouldn't care about secure memory */
 145         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_SNSMEM_SHIFT, 4, 0),
 146         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_BIGENDEL_SHIFT, 4, 0),
 147         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_ASID_SHIFT, 4, 0),
 148         /*
 149          * Differing PARange is fine as long as all peripherals and memory are mapped
 150          * within the minimum PARange of all CPUs
 151          */
 152         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_PARANGE_SHIFT, 4, 0),
 153         ARM64_FTR_END,
 154 };
 155
 156 static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = {
 157         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_PAN_SHIFT, 4, 0),
 158         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_LOR_SHIFT, 4, 0),
 159         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_HPD_SHIFT, 4, 0),
 160         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_VHE_SHIFT, 4, 0),
 161         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_VMIDBITS_SHIFT, 4, 0),
 162         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_HADBS_SHIFT, 4, 0),
 163         ARM64_FTR_END,
 164 };
 165
 166 static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = {
 167         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR2_LVA_SHIFT, 4, 0),
 168         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR2_IESB_SHIFT, 4, 0),
 169         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR2_LSM_SHIFT, 4, 0),
 170         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR2_UAO_SHIFT, 4, 0),
 171         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR2_CNP_SHIFT, 4, 0),
 172         ARM64_FTR_END,
 173 };
 174
 175 static const struct arm64_ftr_bits ftr_ctr[] = {
 176         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1),   /* RAO */
 177         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_SAFE, 24, 4, 0),     /* CWG */
 178         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),      /* ERG */
 179         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 1),      /* DminLine */
 180         /*
 181          * Linux can handle differing I-cache policies. Userspace JITs will
 182          * make use of *minLine.
 183          * If we have differing I-cache policies, report it as the weakest - VIPT.
 184          */
 185         ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, 14, 2, ICACHE_POLICY_VIPT),       /* L1Ip */
 186         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),       /* IminLine */
 187         ARM64_FTR_END,
 188 };
 189
 190 struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = {
 191         .name           = "SYS_CTR_EL0",
 192         .ftr_bits       = ftr_ctr
 193 };
 194
 195 static const struct arm64_ftr_bits ftr_id_mmfr0[] = {
 196         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 28, 4, 0xf),        /* InnerShr */
 197         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 24, 4, 0),    /* FCSE */
 198         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, 20, 4, 0),    /* AuxReg */
 199         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 16, 4, 0),    /* TCM */
 200         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 12, 4, 0),    /* ShareLvl */
 201         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 8, 4, 0xf), /* OuterShr */
 202         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 4, 4, 0),     /* PMSA */
 203         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 4, 0),     /* VMSA */
 204         ARM64_FTR_END,
 205 };
 206
 207 static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = {
 208         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 36, 28, 0),
 209         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_PMSVER_SHIFT, 4, 0),
 210         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_CTX_CMPS_SHIFT, 4, 0),
 211         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_WRPS_SHIFT, 4, 0),
 212         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_BRPS_SHIFT, 4, 0),
 213         /*
 214          * We can instantiate multiple PMU instances with different levels
 215          * of support.
 216          */
 217         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_PMUVER_SHIFT, 4, 0),
 218         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_TRACEVER_SHIFT, 4, 0),
 219         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_DEBUGVER_SHIFT, 4, 0x6),
 220         ARM64_FTR_END,
 221 };
 222
 223 static const struct arm64_ftr_bits ftr_mvfr2[] = {
 224         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 4, 4, 0),             /* FPMisc */
 225         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 4, 0),             /* SIMDMisc */
 226         ARM64_FTR_END,
 227 };
 228
 229 static const struct arm64_ftr_bits ftr_dczid[] = {
 230         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 4, 1, 1),            /* DZP */
 231         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),       /* BS */
 232         ARM64_FTR_END,
 233 };
 234
 235
 236 static const struct arm64_ftr_bits ftr_id_isar5[] = {
 237         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_ISAR5_RDM_SHIFT, 4, 0),
 238         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_ISAR5_CRC32_SHIFT, 4, 0),
 239         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_ISAR5_SHA2_SHIFT, 4, 0),
 240         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_ISAR5_SHA1_SHIFT, 4, 0),
 241         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_ISAR5_AES_SHIFT, 4, 0),
 242         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_ISAR5_SEVL_SHIFT, 4, 0),
 243         ARM64_FTR_END,
 244 };
 245
 246 static const struct arm64_ftr_bits ftr_id_mmfr4[] = {
 247         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 4, 4, 0),             /* ac2 */
 248         ARM64_FTR_END,
 249 };
 250
 251 static const struct arm64_ftr_bits ftr_id_pfr0[] = {
 252         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 12, 4, 0),    /* State3 */
 253         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 8, 4, 0),             /* State2 */
 254         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 4, 4, 0),             /* State1 */
 255         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 4, 0),             /* State0 */
 256         ARM64_FTR_END,
 257 };
 258
 259 static const struct arm64_ftr_bits ftr_id_dfr0[] = {
 260         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
 261         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0xf),   /* PerfMon */
 262         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
 263         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
 264         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
 265         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
 266         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
 267         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
 268         ARM64_FTR_END,
 269 };
 270
 271 /*
 272  * Common ftr bits for a 32bit register with all hidden, strict
 273  * attributes, with 4bit feature fields and a default safe value of
 274  * 0. Covers the following 32bit registers:
 275  * id_isar[0-4], id_mmfr[1-3], id_pfr1, mvfr[0-1]
 276  */
 277 static const struct arm64_ftr_bits ftr_generic_32bits[] = {
 278         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
 279         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0),
 280         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
 281         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
 282         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
 283         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
 284         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
 285         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
 286         ARM64_FTR_END,
 287 };
 288
 289 /* Table for a single 32bit feature value */
 290 static const struct arm64_ftr_bits ftr_single32[] = {
 291         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 32, 0),
 292         ARM64_FTR_END,
 293 };
 294
 295 static const struct arm64_ftr_bits ftr_raz[] = {
 296         ARM64_FTR_END,
 297 };
 298
 299 #define ARM64_FTR_REG(id, table) {              \
 300         .sys_id = id,                           \
 301         .reg =  &(struct arm64_ftr_reg){        \
 302                 .name = #id,                    \
 303                 .ftr_bits = &((table)[0]),      \
 304         }}
 305
 306 static const struct __ftr_reg_entry {
 307         u32                     sys_id;
 308         struct arm64_ftr_reg    *reg;
 309 } arm64_ftr_regs[] = {
 310
 311         /* Op1 = 0, CRn = 0, CRm = 1 */
 312         ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0),
 313         ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_generic_32bits),
 314         ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0),
 315         ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0),
 316         ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits),
 317         ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits),
 318         ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits),
 319
 320         /* Op1 = 0, CRn = 0, CRm = 2 */
 321         ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_generic_32bits),
 322         ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits),
 323         ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits),
 324         ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits),
 325         ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_generic_32bits),
 326         ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5),
 327         ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4),
 328
 329         /* Op1 = 0, CRn = 0, CRm = 3 */
 330         ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_generic_32bits),
 331         ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_generic_32bits),
 332         ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2),
 333
 334         /* Op1 = 0, CRn = 0, CRm = 4 */
 335         ARM64_FTR_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0),
 336         ARM64_FTR_REG(SYS_ID_AA64PFR1_EL1, ftr_raz),
 337
 338         /* Op1 = 0, CRn = 0, CRm = 5 */
 339         ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0),
 340         ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz),
 341
 342         /* Op1 = 0, CRn = 0, CRm = 6 */
 343         ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0),
 344         ARM64_FTR_REG(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1),
 345
 346         /* Op1 = 0, CRn = 0, CRm = 7 */
 347         ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0),
 348         ARM64_FTR_REG(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1),
 349         ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2),
 350
 351         /* Op1 = 3, CRn = 0, CRm = 0 */
 352         { SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 },
 353         ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid),
 354
 355         /* Op1 = 3, CRn = 14, CRm = 0 */
 356         ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_single32),
 357 };
 358
 359 static int search_cmp_ftr_reg(const void *id, const void *regp)
 360 {
 361         return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id;
 362 }
 363
 364 /*
 365  * get_arm64_ftr_reg - Lookup a feature register entry using its
 366  * sys_reg() encoding. With the array arm64_ftr_regs sorted in the
 367  * ascending order of sys_id , we use binary search to find a matching
 368  * entry.
 369  *
 370  * returns - Upon success,  matching ftr_reg entry for id.
 371  *         - NULL on failure. It is upto the caller to decide
 372  *           the impact of a failure.
 373  */
 374 static struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id)
 375 {
 376         const struct __ftr_reg_entry *ret;
 377
 378         ret = bsearch((const void *)(unsigned long)sys_id,
 379                         arm64_ftr_regs,
 380                         ARRAY_SIZE(arm64_ftr_regs),
 381                         sizeof(arm64_ftr_regs[0]),
 382                         search_cmp_ftr_reg);
 383         if (ret)
 384                 return ret->reg;
 385         return NULL;
 386 }
 387
 388 static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg,
 389                                s64 ftr_val)
 390 {
 391         u64 mask = arm64_ftr_mask(ftrp);
 392
 393         reg &= ~mask;
 394         reg |= (ftr_val << ftrp->shift) & mask;
 395         return reg;
 396 }
 397
 398 static s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new,
 399                                 s64 cur)
 400 {
 401         s64 ret = 0;
 402
 403         switch (ftrp->type) {
 404         case FTR_EXACT:
 405                 ret = ftrp->safe_val;
 406                 break;
 407         case FTR_LOWER_SAFE:
 408                 ret = new < cur ? new : cur;
 409                 break;
 410         case FTR_HIGHER_SAFE:
 411                 ret = new > cur ? new : cur;
 412                 break;
 413         default:
 414                 BUG();
 415         }
 416
 417         return ret;
 418 }
 419
 420 static void __init sort_ftr_regs(void)
 421 {
 422         int i;
 423
 424         /* Check that the array is sorted so that we can do the binary search */
 425         for (i = 1; i < ARRAY_SIZE(arm64_ftr_regs); i++)
 426                 BUG_ON(arm64_ftr_regs[i].sys_id < arm64_ftr_regs[i - 1].sys_id);
 427 }
 428
 429 /*
 430  * Initialise the CPU feature register from Boot CPU values.
 431  * Also initiliases the strict_mask for the register.
 432  * Any bits that are not covered by an arm64_ftr_bits entry are considered
 433  * RES0 for the system-wide value, and must strictly match.
 434  */
 435 static void __init init_cpu_ftr_reg(u32 sys_reg, u64 new)
 436 {
 437         u64 val = 0;
 438         u64 strict_mask = ~0x0ULL;
 439         u64 user_mask = 0;
 440         u64 valid_mask = 0;
 441
 442         const struct arm64_ftr_bits *ftrp;
 443         struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg);
 444
 445         BUG_ON(!reg);
 446
 447         for (ftrp  = reg->ftr_bits; ftrp->width; ftrp++) {
 448                 u64 ftr_mask = arm64_ftr_mask(ftrp);
 449                 s64 ftr_new = arm64_ftr_value(ftrp, new);
 450
 451                 val = arm64_ftr_set_value(ftrp, val, ftr_new);
 452
 453                 valid_mask |= ftr_mask;
 454                 if (!ftrp->strict)
 455                         strict_mask &= ~ftr_mask;
 456                 if (ftrp->visible)
 457                         user_mask |= ftr_mask;
 458                 else
 459                         reg->user_val = arm64_ftr_set_value(ftrp,
 460                                                             reg->user_val,
 461                                                             ftrp->safe_val);
 462         }
 463
 464         val &= valid_mask;
 465
 466         reg->sys_val = val;
 467         reg->strict_mask = strict_mask;
 468         reg->user_mask = user_mask;
 469 }
 470
 471 void __init init_cpu_features(struct cpuinfo_arm64 *info)
 472 {
 473         /* Before we start using the tables, make sure it is sorted */
 474         sort_ftr_regs();
 475
 476         init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr);
 477         init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid);
 478         init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq);
 479         init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0);
 480         init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1);
 481         init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0);
 482         init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1);
 483         init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0);
 484         init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1);
 485         init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2);
 486         init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0);
 487         init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1);
 488
 489         if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
 490                 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0);
 491                 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0);
 492                 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1);
 493                 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2);
 494                 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3);
 495                 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4);
 496                 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5);
 497                 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0);
 498                 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1);
 499                 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2);
 500                 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3);
 501                 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0);
 502                 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1);
 503                 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0);
 504                 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1);
 505                 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2);
 506         }
 507
 508 }
 509
 510 static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new)
 511 {
 512         const struct arm64_ftr_bits *ftrp;
 513
 514         for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
 515                 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val);
 516                 s64 ftr_new = arm64_ftr_value(ftrp, new);
 517
 518                 if (ftr_cur == ftr_new)
 519                         continue;
 520                 /* Find a safe value */
 521                 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur);
 522                 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new);
 523         }
 524
 525 }
 526
 527 static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot)
 528 {
 529         struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id);
 530
 531         BUG_ON(!regp);
 532         update_cpu_ftr_reg(regp, val);
 533         if ((boot & regp->strict_mask) == (val & regp->strict_mask))
 534                 return 0;
 535         pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n",
 536                         regp->name, boot, cpu, val);
 537         return 1;
 538 }
 539
 540 /*
 541  * Update system wide CPU feature registers with the values from a
 542  * non-boot CPU. Also performs SANITY checks to make sure that there
 543  * aren't any insane variations from that of the boot CPU.
 544  */
 545 void update_cpu_features(int cpu,
 546                          struct cpuinfo_arm64 *info,
 547                          struct cpuinfo_arm64 *boot)
 548 {
 549         int taint = 0;
 550
 551         /*
 552          * The kernel can handle differing I-cache policies, but otherwise
 553          * caches should look identical. Userspace JITs will make use of
 554          * *minLine.
 555          */
 556         taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu,
 557                                       info->reg_ctr, boot->reg_ctr);
 558
 559         /*
 560          * Userspace may perform DC ZVA instructions. Mismatched block sizes
 561          * could result in too much or too little memory being zeroed if a
 562          * process is preempted and migrated between CPUs.
 563          */
 564         taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu,
 565                                       info->reg_dczid, boot->reg_dczid);
 566
 567         /* If different, timekeeping will be broken (especially with KVM) */
 568         taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu,
 569                                       info->reg_cntfrq, boot->reg_cntfrq);
 570
 571         /*
 572          * The kernel uses self-hosted debug features and expects CPUs to
 573          * support identical debug features. We presently need CTX_CMPs, WRPs,
 574          * and BRPs to be identical.
 575          * ID_AA64DFR1 is currently RES0.
 576          */
 577         taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu,
 578                                       info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0);
 579         taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu,
 580                                       info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1);
 581         /*
 582          * Even in big.LITTLE, processors should be identical instruction-set
 583          * wise.
 584          */
 585         taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu,
 586                                       info->reg_id_aa64isar0, boot->reg_id_aa64isar0);
 587         taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu,
 588                                       info->reg_id_aa64isar1, boot->reg_id_aa64isar1);
 589
 590         /*
 591          * Differing PARange support is fine as long as all peripherals and
 592          * memory are mapped within the minimum PARange of all CPUs.
 593          * Linux should not care about secure memory.
 594          */
 595         taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu,
 596                                       info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0);
 597         taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu,
 598                                       info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1);
 599         taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu,
 600                                       info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2);
 601
 602         /*
 603          * EL3 is not our concern.
 604          * ID_AA64PFR1 is currently RES0.
 605          */
 606         taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu,
 607                                       info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0);
 608         taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu,
 609                                       info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1);
 610
 611         /*
 612          * If we have AArch32, we care about 32-bit features for compat.
 613          * If the system doesn't support AArch32, don't update them.
 614          */
 615         if (id_aa64pfr0_32bit_el0(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1)) &&
 616                 id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
 617
 618                 taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu,
 619                                         info->reg_id_dfr0, boot->reg_id_dfr0);
 620                 taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu,
 621                                         info->reg_id_isar0, boot->reg_id_isar0);
 622                 taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu,
 623                                         info->reg_id_isar1, boot->reg_id_isar1);
 624                 taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu,
 625                                         info->reg_id_isar2, boot->reg_id_isar2);
 626                 taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu,
 627                                         info->reg_id_isar3, boot->reg_id_isar3);
 628                 taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu,
 629                                         info->reg_id_isar4, boot->reg_id_isar4);
 630                 taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu,
 631                                         info->reg_id_isar5, boot->reg_id_isar5);
 632
 633                 /*
 634                  * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and
 635                  * ACTLR formats could differ across CPUs and therefore would have to
 636                  * be trapped for virtualization anyway.
 637                  */
 638                 taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu,
 639                                         info->reg_id_mmfr0, boot->reg_id_mmfr0);
 640                 taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu,
 641                                         info->reg_id_mmfr1, boot->reg_id_mmfr1);
 642                 taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu,
 643                                         info->reg_id_mmfr2, boot->reg_id_mmfr2);
 644                 taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu,
 645                                         info->reg_id_mmfr3, boot->reg_id_mmfr3);
 646                 taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu,
 647                                         info->reg_id_pfr0, boot->reg_id_pfr0);
 648                 taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu,
 649                                         info->reg_id_pfr1, boot->reg_id_pfr1);
 650                 taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu,
 651                                         info->reg_mvfr0, boot->reg_mvfr0);
 652                 taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu,
 653                                         info->reg_mvfr1, boot->reg_mvfr1);
 654                 taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu,
 655                                         info->reg_mvfr2, boot->reg_mvfr2);
 656         }
 657
 658         /*
 659          * Mismatched CPU features are a recipe for disaster. Don't even
 660          * pretend to support them.
 661          */
 662         if (taint) {
 663                 pr_warn_once("Unsupported CPU feature variation detected.\n");
 664                 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK);
 665         }
 666 }
 667
 668 u64 read_sanitised_ftr_reg(u32 id)
 669 {
 670         struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id);
 671
 672         /* We shouldn't get a request for an unsupported register */
 673         BUG_ON(!regp);
 674         return regp->sys_val;
 675 }
 676
 677 #define read_sysreg_case(r)     \
 678         case r:         return read_sysreg_s(r)
 679
 680 /*
 681  * __read_sysreg_by_encoding() - Used by a STARTING cpu before cpuinfo is populated.
 682  * Read the system register on the current CPU
 683  */
 684 static u64 __read_sysreg_by_encoding(u32 sys_id)
 685 {
 686         switch (sys_id) {
 687         read_sysreg_case(SYS_ID_PFR0_EL1);
 688         read_sysreg_case(SYS_ID_PFR1_EL1);
 689         read_sysreg_case(SYS_ID_DFR0_EL1);
 690         read_sysreg_case(SYS_ID_MMFR0_EL1);
 691         read_sysreg_case(SYS_ID_MMFR1_EL1);
 692         read_sysreg_case(SYS_ID_MMFR2_EL1);
 693         read_sysreg_case(SYS_ID_MMFR3_EL1);
 694         read_sysreg_case(SYS_ID_ISAR0_EL1);
 695         read_sysreg_case(SYS_ID_ISAR1_EL1);
 696         read_sysreg_case(SYS_ID_ISAR2_EL1);
 697         read_sysreg_case(SYS_ID_ISAR3_EL1);
 698         read_sysreg_case(SYS_ID_ISAR4_EL1);
 699         read_sysreg_case(SYS_ID_ISAR5_EL1);
 700         read_sysreg_case(SYS_MVFR0_EL1);
 701         read_sysreg_case(SYS_MVFR1_EL1);
 702         read_sysreg_case(SYS_MVFR2_EL1);
 703
 704         read_sysreg_case(SYS_ID_AA64PFR0_EL1);
 705         read_sysreg_case(SYS_ID_AA64PFR1_EL1);
 706         read_sysreg_case(SYS_ID_AA64DFR0_EL1);
 707         read_sysreg_case(SYS_ID_AA64DFR1_EL1);
 708         read_sysreg_case(SYS_ID_AA64MMFR0_EL1);
 709         read_sysreg_case(SYS_ID_AA64MMFR1_EL1);
 710         read_sysreg_case(SYS_ID_AA64MMFR2_EL1);
 711         read_sysreg_case(SYS_ID_AA64ISAR0_EL1);
 712         read_sysreg_case(SYS_ID_AA64ISAR1_EL1);
 713
 714         read_sysreg_case(SYS_CNTFRQ_EL0);
 715         read_sysreg_case(SYS_CTR_EL0);
 716         read_sysreg_case(SYS_DCZID_EL0);
 717
 718         default:
 719                 BUG();
 720                 return 0;
 721         }
 722 }
 723
 724 #include <linux/irqchip/arm-gic-v3.h>
 725
 726 static bool
 727 feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry)
 728 {
 729         int val = cpuid_feature_extract_field(reg, entry->field_pos, entry->sign);
 730
 731         return val >= entry->min_field_value;
 732 }
 733
 734 static bool
 735 has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope)
 736 {
 737         u64 val;
 738
 739         WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible());
 740         if (scope == SCOPE_SYSTEM)
 741                 val = read_sanitised_ftr_reg(entry->sys_reg);
 742         else
 743                 val = __read_sysreg_by_encoding(entry->sys_reg);
 744
 745         return feature_matches(val, entry);
 746 }
 747
 748 static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope)
 749 {
 750         bool has_sre;
 751
 752         if (!has_cpuid_feature(entry, scope))
 753                 return false;
 754
 755         has_sre = gic_enable_sre();
 756         if (!has_sre)
 757                 pr_warn_once("%s present but disabled by higher exception level\n",
 758                              entry->desc);
 759
 760         return has_sre;
 761 }
 762
 763 static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities *entry, int __unused)
 764 {
 765         u32 midr = read_cpuid_id();
 766
 767         /* Cavium ThunderX pass 1.x and 2.x */
 768         return MIDR_IS_CPU_MODEL_RANGE(midr, MIDR_THUNDERX,
 769                 MIDR_CPU_VAR_REV(0, 0),
 770                 MIDR_CPU_VAR_REV(1, MIDR_REVISION_MASK));
 771 }
 772
 773 static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused)
 774 {
 775         return is_kernel_in_hyp_mode();
 776 }
 777
 778 static bool hyp_offset_low(const struct arm64_cpu_capabilities *entry,
 779                            int __unused)
 780 {
 781         phys_addr_t idmap_addr = __pa_symbol(__hyp_idmap_text_start);
 782
 783         /*
 784          * Activate the lower HYP offset only if:
 785          * - the idmap doesn't clash with it,
 786          * - the kernel is not running at EL2.
 787          */
 788         return idmap_addr > GENMASK(VA_BITS - 2, 0) && !is_kernel_in_hyp_mode();
 789 }
 790
 791 static bool has_no_fpsimd(const struct arm64_cpu_capabilities *entry, int __unused)
 792 {
 793         u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
 794
 795         return cpuid_feature_extract_signed_field(pfr0,
 796                                         ID_AA64PFR0_FP_SHIFT) < 0;
 797 }
 798
 799 static const struct arm64_cpu_capabilities arm64_features[] = {
 800         {
 801                 .desc = "GIC system register CPU interface",
 802                 .capability = ARM64_HAS_SYSREG_GIC_CPUIF,
 803                 .def_scope = SCOPE_SYSTEM,
 804                 .matches = has_useable_gicv3_cpuif,
 805                 .sys_reg = SYS_ID_AA64PFR0_EL1,
 806                 .field_pos = ID_AA64PFR0_GIC_SHIFT,
 807                 .sign = FTR_UNSIGNED,
 808                 .min_field_value = 1,
 809         },
 810 #ifdef CONFIG_ARM64_PAN
 811         {
 812                 .desc = "Privileged Access Never",
 813                 .capability = ARM64_HAS_PAN,
 814                 .def_scope = SCOPE_SYSTEM,
 815                 .matches = has_cpuid_feature,
 816                 .sys_reg = SYS_ID_AA64MMFR1_EL1,
 817                 .field_pos = ID_AA64MMFR1_PAN_SHIFT,
 818                 .sign = FTR_UNSIGNED,
 819                 .min_field_value = 1,
 820                 .enable = cpu_enable_pan,
 821         },
 822 #endif /* CONFIG_ARM64_PAN */
 823 #if defined(CONFIG_AS_LSE) && defined(CONFIG_ARM64_LSE_ATOMICS)
 824         {
 825                 .desc = "LSE atomic instructions",
 826                 .capability = ARM64_HAS_LSE_ATOMICS,
 827                 .def_scope = SCOPE_SYSTEM,
 828                 .matches = has_cpuid_feature,
 829                 .sys_reg = SYS_ID_AA64ISAR0_EL1,
 830                 .field_pos = ID_AA64ISAR0_ATOMICS_SHIFT,
 831                 .sign = FTR_UNSIGNED,
 832                 .min_field_value = 2,
 833         },
 834 #endif /* CONFIG_AS_LSE && CONFIG_ARM64_LSE_ATOMICS */
 835         {
 836                 .desc = "Software prefetching using PRFM",
 837                 .capability = ARM64_HAS_NO_HW_PREFETCH,
 838                 .def_scope = SCOPE_SYSTEM,
 839                 .matches = has_no_hw_prefetch,
 840         },
 841 #ifdef CONFIG_ARM64_UAO
 842         {
 843                 .desc = "User Access Override",
 844                 .capability = ARM64_HAS_UAO,
 845                 .def_scope = SCOPE_SYSTEM,
 846                 .matches = has_cpuid_feature,
 847                 .sys_reg = SYS_ID_AA64MMFR2_EL1,
 848                 .field_pos = ID_AA64MMFR2_UAO_SHIFT,
 849                 .min_field_value = 1,
 850                 /*
 851                  * We rely on stop_machine() calling uao_thread_switch() to set
 852                  * UAO immediately after patching.
 853                  */
 854         },
 855 #endif /* CONFIG_ARM64_UAO */
 856 #ifdef CONFIG_ARM64_PAN
 857         {
 858                 .capability = ARM64_ALT_PAN_NOT_UAO,
 859                 .def_scope = SCOPE_SYSTEM,
 860                 .matches = cpufeature_pan_not_uao,
 861         },
 862 #endif /* CONFIG_ARM64_PAN */
 863         {
 864                 .desc = "Virtualization Host Extensions",
 865                 .capability = ARM64_HAS_VIRT_HOST_EXTN,
 866                 .def_scope = SCOPE_SYSTEM,
 867                 .matches = runs_at_el2,
 868         },
 869         {
 870                 .desc = "32-bit EL0 Support",
 871                 .capability = ARM64_HAS_32BIT_EL0,
 872                 .def_scope = SCOPE_SYSTEM,
 873                 .matches = has_cpuid_feature,
 874                 .sys_reg = SYS_ID_AA64PFR0_EL1,
 875                 .sign = FTR_UNSIGNED,
 876                 .field_pos = ID_AA64PFR0_EL0_SHIFT,
 877                 .min_field_value = ID_AA64PFR0_EL0_32BIT_64BIT,
 878         },
 879         {
 880                 .desc = "Reduced HYP mapping offset",
 881                 .capability = ARM64_HYP_OFFSET_LOW,
 882                 .def_scope = SCOPE_SYSTEM,
 883                 .matches = hyp_offset_low,
 884         },
 885         {
 886                 /* FP/SIMD is not implemented */
 887                 .capability = ARM64_HAS_NO_FPSIMD,
 888                 .def_scope = SCOPE_SYSTEM,
 889                 .min_field_value = 0,
 890                 .matches = has_no_fpsimd,
 891         },
 892         {},
 893 };
 894
 895 #define HWCAP_CAP(reg, field, s, min_value, type, cap)  \
 896         {                                                       \
 897                 .desc = #cap,                                   \
 898                 .def_scope = SCOPE_SYSTEM,                      \
 899                 .matches = has_cpuid_feature,                   \
 900                 .sys_reg = reg,                                 \
 901                 .field_pos = field,                             \
 902                 .sign = s,                                      \
 903                 .min_field_value = min_value,                   \
 904                 .hwcap_type = type,                             \
 905                 .hwcap = cap,                                   \
 906         }
 907
 908 static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
 909         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_PMULL),
 910         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_AES),
 911         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SHA1),
 912         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SHA2),
 913         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_CRC32),
 914         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_ATOMICS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_ATOMICS),
 915         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_RDM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_ASIMDRDM),
 916         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, HWCAP_FP),
 917         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, HWCAP_FPHP),
 918         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, HWCAP_ASIMD),
 919         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, HWCAP_ASIMDHP),
 920         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_DCPOP),
 921         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_JSCVT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_JSCVT),
 922         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FCMA_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_FCMA),
 923         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_LRCPC),
 924         {},
 925 };
 926
 927 static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = {
 928 #ifdef CONFIG_COMPAT
 929         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL),
 930         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES),
 931         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1),
 932         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2),
 933         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32),
 934 #endif
 935         {},
 936 };
 937
 938 static void __init cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap)
 939 {
 940         switch (cap->hwcap_type) {
 941         case CAP_HWCAP:
 942                 elf_hwcap |= cap->hwcap;
 943                 break;
 944 #ifdef CONFIG_COMPAT
 945         case CAP_COMPAT_HWCAP:
 946                 compat_elf_hwcap |= (u32)cap->hwcap;
 947                 break;
 948         case CAP_COMPAT_HWCAP2:
 949                 compat_elf_hwcap2 |= (u32)cap->hwcap;
 950                 break;
 951 #endif
 952         default:
 953                 WARN_ON(1);
 954                 break;
 955         }
 956 }
 957
 958 /* Check if we have a particular HWCAP enabled */
 959 static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap)
 960 {
 961         bool rc;
 962
 963         switch (cap->hwcap_type) {
 964         case CAP_HWCAP:
 965                 rc = (elf_hwcap & cap->hwcap) != 0;
 966                 break;
 967 #ifdef CONFIG_COMPAT
 968         case CAP_COMPAT_HWCAP:
 969                 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0;
 970                 break;
 971         case CAP_COMPAT_HWCAP2:
 972                 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0;
 973                 break;
 974 #endif
 975         default:
 976                 WARN_ON(1);
 977                 rc = false;
 978         }
 979
 980         return rc;
 981 }
 982
 983 static void __init setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps)
 984 {
 985         /* We support emulation of accesses to CPU ID feature registers */
 986         elf_hwcap |= HWCAP_CPUID;
 987         for (; hwcaps->matches; hwcaps++)
 988                 if (hwcaps->matches(hwcaps, hwcaps->def_scope))
 989                         cap_set_elf_hwcap(hwcaps);
 990 }
 991
 992 void update_cpu_capabilities(const struct arm64_cpu_capabilities *caps,
 993                             const char *info)
 994 {
 995         for (; caps->matches; caps++) {
 996                 if (!caps->matches(caps, caps->def_scope))
 997                         continue;
 998
 999                 if (!cpus_have_cap(caps->capability) && caps->desc)
1000                         pr_info("%s %s\n", info, caps->desc);
1001                 cpus_set_cap(caps->capability);
1002         }
1003 }
1004
1005 /*
1006  * Run through the enabled capabilities and enable() it on all active
1007  * CPUs
1008  */
1009 void __init enable_cpu_capabilities(const struct arm64_cpu_capabilities *caps)
1010 {
1011         for (; caps->matches; caps++) {
1012                 unsigned int num = caps->capability;
1013
1014                 if (!cpus_have_cap(num))
1015                         continue;
1016
1017                 /* Ensure cpus_have_const_cap(num) works */
1018                 static_branch_enable(&cpu_hwcap_keys[num]);
1019
1020                 if (caps->enable) {
1021                         /*
1022                          * Use stop_machine() as it schedules the work allowing
1023                          * us to modify PSTATE, instead of on_each_cpu() which
1024                          * uses an IPI, giving us a PSTATE that disappears when
1025                          * we return.
1026                          */
1027                         stop_machine(caps->enable, NULL, cpu_online_mask);
1028                 }
1029         }
1030 }
1031
1032 /*
1033  * Flag to indicate if we have computed the system wide
1034  * capabilities based on the boot time active CPUs. This
1035  * will be used to determine if a new booting CPU should
1036  * go through the verification process to make sure that it
1037  * supports the system capabilities, without using a hotplug
1038  * notifier.
1039  */
1040 static bool sys_caps_initialised;
1041
1042 static inline void set_sys_caps_initialised(void)
1043 {
1044         sys_caps_initialised = true;
1045 }
1046
1047 /*
1048  * Check for CPU features that are used in early boot
1049  * based on the Boot CPU value.
1050  */
1051 static void check_early_cpu_features(void)
1052 {
1053         verify_cpu_run_el();
1054         verify_cpu_asid_bits();
1055 }
1056
1057 static void
1058 verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps)
1059 {
1060
1061         for (; caps->matches; caps++)
1062                 if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) {
1063                         pr_crit("CPU%d: missing HWCAP: %s\n",
1064                                         smp_processor_id(), caps->desc);
1065                         cpu_die_early();
1066                 }
1067 }
1068
1069 static void
1070 verify_local_cpu_features(const struct arm64_cpu_capabilities *caps)
1071 {
1072         for (; caps->matches; caps++) {
1073                 if (!cpus_have_cap(caps->capability))
1074                         continue;
1075                 /*
1076                  * If the new CPU misses an advertised feature, we cannot proceed
1077                  * further, park the cpu.
1078                  */
1079                 if (!caps->matches(caps, SCOPE_LOCAL_CPU)) {
1080                         pr_crit("CPU%d: missing feature: %s\n",
1081                                         smp_processor_id(), caps->desc);
1082                         cpu_die_early();
1083                 }
1084                 if (caps->enable)
1085                         caps->enable(NULL);
1086         }
1087 }
1088
1089 /*
1090  * Run through the enabled system capabilities and enable() it on this CPU.
1091  * The capabilities were decided based on the available CPUs at the boot time.
1092  * Any new CPU should match the system wide status of the capability. If the
1093  * new CPU doesn't have a capability which the system now has enabled, we
1094  * cannot do anything to fix it up and could cause unexpected failures. So
1095  * we park the CPU.
1096  */
1097 static void verify_local_cpu_capabilities(void)
1098 {
1099         verify_local_cpu_errata_workarounds();
1100         verify_local_cpu_features(arm64_features);
1101         verify_local_elf_hwcaps(arm64_elf_hwcaps);
1102         if (system_supports_32bit_el0())
1103                 verify_local_elf_hwcaps(compat_elf_hwcaps);
1104 }
1105
1106 void check_local_cpu_capabilities(void)
1107 {
1108         /*
1109          * All secondary CPUs should conform to the early CPU features
1110          * in use by the kernel based on boot CPU.
1111          */
1112         check_early_cpu_features();
1113
1114         /*
1115          * If we haven't finalised the system capabilities, this CPU gets
1116          * a chance to update the errata work arounds.
1117          * Otherwise, this CPU should verify that it has all the system
1118          * advertised capabilities.
1119          */
1120         if (!sys_caps_initialised)
1121                 update_cpu_errata_workarounds();
1122         else
1123                 verify_local_cpu_capabilities();
1124 }
1125
1126 static void __init setup_feature_capabilities(void)
1127 {
1128         update_cpu_capabilities(arm64_features, "detected feature:");
1129         enable_cpu_capabilities(arm64_features);
1130 }
1131
1132 DEFINE_STATIC_KEY_FALSE(arm64_const_caps_ready);
1133 EXPORT_SYMBOL(arm64_const_caps_ready);
1134
1135 static void __init mark_const_caps_ready(void)
1136 {
1137         static_branch_enable(&arm64_const_caps_ready);
1138 }
1139
1140 /*
1141  * Check if the current CPU has a given feature capability.
1142  * Should be called from non-preemptible context.
1143  */
1144 static bool __this_cpu_has_cap(const struct arm64_cpu_capabilities *cap_array,
1145                                unsigned int cap)
1146 {
1147         const struct arm64_cpu_capabilities *caps;
1148
1149         if (WARN_ON(preemptible()))
1150                 return false;
1151
1152         for (caps = cap_array; caps->desc; caps++)
1153                 if (caps->capability == cap && caps->matches)
1154                         return caps->matches(caps, SCOPE_LOCAL_CPU);
1155
1156         return false;
1157 }
1158
1159 extern const struct arm64_cpu_capabilities arm64_errata[];
1160
1161 bool this_cpu_has_cap(unsigned int cap)
1162 {
1163         return (__this_cpu_has_cap(arm64_features, cap) ||
1164                 __this_cpu_has_cap(arm64_errata, cap));
1165 }
1166
1167 void __init setup_cpu_features(void)
1168 {
1169         u32 cwg;
1170         int cls;
1171
1172         /* Set the CPU feature capabilies */
1173         setup_feature_capabilities();
1174         enable_errata_workarounds();
1175         mark_const_caps_ready();
1176         setup_elf_hwcaps(arm64_elf_hwcaps);
1177
1178         if (system_supports_32bit_el0())
1179                 setup_elf_hwcaps(compat_elf_hwcaps);
1180
1181         /* Advertise that we have computed the system capabilities */
1182         set_sys_caps_initialised();
1183
1184         /*
1185          * Check for sane CTR_EL0.CWG value.
1186          */
1187         cwg = cache_type_cwg();
1188         cls = cache_line_size();
1189         if (!cwg)
1190                 pr_warn("No Cache Writeback Granule information, assuming cache line size %d\n",
1191                         cls);
1192         if (L1_CACHE_BYTES < cls)
1193                 pr_warn("L1_CACHE_BYTES smaller than the Cache Writeback Granule (%d < %d)\n",
1194                         L1_CACHE_BYTES, cls);
1195 }
1196
1197 static bool __maybe_unused
1198 cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused)
1199 {
1200         return (cpus_have_const_cap(ARM64_HAS_PAN) && !cpus_have_const_cap(ARM64_HAS_UAO));
1201 }
1202
1203 /*
1204  * We emulate only the following system register space.
1205  * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 4 - 7]
1206  * See Table C5-6 System instruction encodings for System register accesses,
1207  * ARMv8 ARM(ARM DDI 0487A.f) for more details.
1208  */
1209 static inline bool __attribute_const__ is_emulated(u32 id)
1210 {
1211         return (sys_reg_Op0(id) == 0x3 &&
1212                 sys_reg_CRn(id) == 0x0 &&
1213                 sys_reg_Op1(id) == 0x0 &&
1214                 (sys_reg_CRm(id) == 0 ||
1215                  ((sys_reg_CRm(id) >= 4) && (sys_reg_CRm(id) <= 7))));
1216 }
1217
1218 /*
1219  * With CRm == 0, reg should be one of :
1220  * MIDR_EL1, MPIDR_EL1 or REVIDR_EL1.
1221  */
1222 static inline int emulate_id_reg(u32 id, u64 *valp)
1223 {
1224         switch (id) {
1225         case SYS_MIDR_EL1:
1226                 *valp = read_cpuid_id();
1227                 break;
1228         case SYS_MPIDR_EL1:
1229                 *valp = SYS_MPIDR_SAFE_VAL;
1230                 break;
1231         case SYS_REVIDR_EL1:
1232                 /* IMPLEMENTATION DEFINED values are emulated with 0 */
1233                 *valp = 0;
1234                 break;
1235         default:
1236                 return -EINVAL;
1237         }
1238
1239         return 0;
1240 }
1241
1242 static int emulate_sys_reg(u32 id, u64 *valp)
1243 {
1244         struct arm64_ftr_reg *regp;
1245
1246         if (!is_emulated(id))
1247                 return -EINVAL;
1248
1249         if (sys_reg_CRm(id) == 0)
1250                 return emulate_id_reg(id, valp);
1251
1252         regp = get_arm64_ftr_reg(id);
1253         if (regp)
1254                 *valp = arm64_ftr_reg_user_value(regp);
1255         else
1256                 /*
1257                  * The untracked registers are either IMPLEMENTATION DEFINED
1258                  * (e.g, ID_AFR0_EL1) or reserved RAZ.
1259                  */
1260                 *valp = 0;
1261         return 0;
1262 }
1263
1264 static int emulate_mrs(struct pt_regs *regs, u32 insn)
1265 {
1266         int rc;
1267         u32 sys_reg, dst;
1268         u64 val;
1269
1270         /*
1271          * sys_reg values are defined as used in mrs/msr instruction.
1272          * shift the imm value to get the encoding.
1273          */
1274         sys_reg = (u32)aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16, insn) << 5;
1275         rc = emulate_sys_reg(sys_reg, &val);
1276         if (!rc) {
1277                 dst = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn);
1278                 pt_regs_write_reg(regs, dst, val);
1279                 regs->pc += 4;
1280         }
1281
1282         return rc;
1283 }
1284
1285 static struct undef_hook mrs_hook = {
1286         .instr_mask = 0xfff00000,
1287         .instr_val  = 0xd5300000,
1288         .pstate_mask = COMPAT_PSR_MODE_MASK,
1289         .pstate_val = PSR_MODE_EL0t,
1290         .fn = emulate_mrs,
1291 };
1292
1293 static int __init enable_mrs_emulation(void)
1294 {
1295         register_undef_hook(&mrs_hook);
1296         return 0;
1297 }
1298
1299 late_initcall(enable_mrs_emulation);